diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-25 13:14:42 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-25 13:14:42 -0400 |
| commit | 8fe556338db4cc50a3f1ba20306bc5e464941f2b (patch) | |
| tree | d95b1933c18d142f9c533f32ac7b84bd1f2d0da5 /tests/quick | |
| parent | 66e331c7bb7d503c35808325e1bfaa9f18f4bdb9 (diff) | |
| download | gem5-8fe556338db4cc50a3f1ba20306bc5e464941f2b.tar.xz | |
stats: Update stats to reflect use of SimpleDRAM
This patch bumps the stats to match the use of SimpleDRAM instead of
SimpleMemory in all inorder and O3 regressions, and also all
full-system regressions. A number of performance-related stats change,
and a whole bunch of stats are added for the memory controller.
Diffstat (limited to 'tests/quick')
25 files changed, 14989 insertions, 10560 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index b9451bcf6..0cbad844c 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.870325 # Nu sim_ticks 1870325497500 # Number of ticks simulated final_tick 1870325497500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2529303 # Simulator instruction rate (inst/s) -host_op_rate 2529302 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 74909435310 # Simulator tick rate (ticks/s) -host_mem_usage 298360 # Number of bytes of host memory used -host_seconds 24.97 # Real time elapsed on the host +host_inst_rate 1528286 # Simulator instruction rate (inst/s) +host_op_rate 1528286 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45262701867 # Simulator tick rate (ticks/s) +host_mem_usage 296828 # Number of bytes of host memory used +host_seconds 41.32 # Real time elapsed on the host sim_insts 63151114 # Number of instructions simulated sim_ops 63151114 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 760896 # Number of bytes read from this memory @@ -48,16 +48,174 @@ system.physmem.bw_total::tsunami.ide 1416652 # To system.physmem.bw_total::cpu1.inst 59438 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 364531 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 42090265 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 0 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 0 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 0 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 0 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 0 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 0 # Sum of mem lat for all requests +system.physmem.totBusLat 0 # Total cycles spent in databus access +system.physmem.totBankLat 0 # Total cycles spent in bank access +system.physmem.avgQLat nan # Average queueing delay per request +system.physmem.avgBankLat nan # Average bank access latency per request +system.physmem.avgBusLat nan # Average bus latency per request +system.physmem.avgMemAccLat nan # Average memory access latency +system.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.00 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.00 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 0 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate nan # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap nan # Average gap between requests system.l2c.replacements 1000406 # number of replacements -system.l2c.tagsinuse 65381.817479 # Cycle average of tags in use -system.l2c.total_refs 2465974 # Total number of references to valid blocks. +system.l2c.tagsinuse 65381.817483 # Cycle average of tags in use +system.l2c.total_refs 2465980 # Total number of references to valid blocks. system.l2c.sampled_refs 1065550 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.314273 # Average number of references to valid blocks. +system.l2c.avg_refs 2.314279 # Average number of references to valid blocks. system.l2c.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 56158.126687 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4894.240577 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4135.004263 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 174.436812 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 56158.126694 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4894.240575 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4135.004261 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 174.436811 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.data 20.009142 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.856905 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.inst 0.074680 # Average percentage of cache occupancy @@ -66,10 +224,10 @@ system.l2c.occ_percent::cpu1.inst 0.002662 # Av system.l2c.occ_percent::cpu1.data 0.000305 # Average percentage of cache occupancy system.l2c.occ_percent::total 0.997647 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.inst 872724 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 763058 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 763064 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 102911 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.data 36889 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1775582 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1775588 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 816811 # number of Writeback hits system.l2c.Writeback_hits::total 816811 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 138 # number of UpgradeReq hits @@ -82,15 +240,15 @@ system.l2c.ReadExReq_hits::cpu0.data 166434 # nu system.l2c.ReadExReq_hits::cpu1.data 14300 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 180734 # number of ReadExReq hits system.l2c.demand_hits::cpu0.inst 872724 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 929492 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 929498 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 102911 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 51189 # number of demand (read+write) hits -system.l2c.demand_hits::total 1956316 # number of demand (read+write) hits +system.l2c.demand_hits::total 1956322 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.inst 872724 # number of overall hits -system.l2c.overall_hits::cpu0.data 929492 # number of overall hits +system.l2c.overall_hits::cpu0.data 929498 # number of overall hits system.l2c.overall_hits::cpu1.inst 102911 # number of overall hits system.l2c.overall_hits::cpu1.data 51189 # number of overall hits -system.l2c.overall_hits::total 1956316 # number of overall hits +system.l2c.overall_hits::total 1956322 # number of overall hits system.l2c.ReadReq_misses::cpu0.inst 11889 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 926770 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 1737 # number of ReadReq misses @@ -116,10 +274,10 @@ system.l2c.overall_misses::cpu1.inst 1737 # nu system.l2c.overall_misses::cpu1.data 10780 # number of overall misses system.l2c.overall_misses::total 1066458 # number of overall misses system.l2c.ReadReq_accesses::cpu0.inst 884613 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1689828 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 1689834 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 104648 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.data 37807 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2716896 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2716902 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 816811 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 816811 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 2579 # number of UpgradeReq accesses(hits+misses) @@ -132,20 +290,20 @@ system.l2c.ReadExReq_accesses::cpu0.data 281716 # nu system.l2c.ReadExReq_accesses::cpu1.data 24162 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 305878 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.inst 884613 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1971544 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1971550 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 104648 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.data 61969 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 3022774 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3022780 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.inst 884613 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1971544 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1971550 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 104648 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.data 61969 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 3022774 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3022780 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.013440 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.548440 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.548438 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.016599 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.024281 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.346467 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.346466 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.946491 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.939542 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.945158 # miss rate for UpgradeReq accesses @@ -156,15 +314,15 @@ system.l2c.ReadExReq_miss_rate::cpu0.data 0.409214 # m system.l2c.ReadExReq_miss_rate::cpu1.data 0.408162 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 0.409130 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.013440 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.528546 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.528545 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.016599 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.173958 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.352808 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.352807 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.013440 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.528546 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.528545 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.016599 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.173958 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.352808 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.352807 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -282,8 +440,8 @@ system.cpu0.num_fp_register_writes 150767 # nu system.cpu0.num_mem_refs 15124548 # number of memory refs system.cpu0.num_load_insts 9178366 # Number of load instructions system.cpu0.num_store_insts 5946182 # Number of store instructions -system.cpu0.num_idle_cycles 3683454679.572560 # Number of idle cycles -system.cpu0.num_busy_cycles 57196203.427440 # Number of busy cycles +system.cpu0.num_idle_cycles 3683454681.836560 # Number of idle cycles +system.cpu0.num_busy_cycles 57196201.163440 # Number of busy cycles system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed @@ -449,39 +607,39 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1978242 # number of replacements +system.cpu0.dcache.replacements 1978248 # number of replacements system.cpu0.dcache.tagsinuse 507.129590 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13113201 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1978754 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 6.626999 # Average number of references to valid blocks. +system.cpu0.dcache.total_refs 13113195 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1978760 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 6.626976 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. system.cpu0.dcache.occ_blocks::cpu0.data 507.129590 # Average occupied blocks per requestor system.cpu0.dcache.occ_percent::cpu0.data 0.990487 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.990487 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7292600 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7292600 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu0.data 7292594 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7292594 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 5457787 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 5457787 # number of WriteReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 171977 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 171977 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186443 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 186443 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12750387 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12750387 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12750387 # number of overall hits -system.cpu0.dcache.overall_hits::total 12750387 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1683130 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1683130 # number of ReadReq misses +system.cpu0.dcache.demand_hits::cpu0.data 12750381 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12750381 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12750381 # number of overall hits +system.cpu0.dcache.overall_hits::total 12750381 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1683136 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1683136 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 285798 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 285798 # number of WriteReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16152 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 16152 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 726 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 726 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1968928 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1968928 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1968928 # number of overall misses -system.cpu0.dcache.overall_misses::total 1968928 # number of overall misses +system.cpu0.dcache.demand_misses::cpu0.data 1968934 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1968934 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1968934 # number of overall misses +system.cpu0.dcache.overall_misses::total 1968934 # number of overall misses system.cpu0.dcache.ReadReq_accesses::cpu0.data 8975730 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 8975730 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 5743585 # number of WriteReq accesses(hits+misses) @@ -494,8 +652,8 @@ system.cpu0.dcache.demand_accesses::cpu0.data 14719315 system.cpu0.dcache.demand_accesses::total 14719315 # number of demand (read+write) accesses system.cpu0.dcache.overall_accesses::cpu0.data 14719315 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 14719315 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187520 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.187520 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187521 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.187521 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049760 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.049760 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085856 # miss rate for LoadLockedReq accesses diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index cf5c30619..99b74717c 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.829331 # Nu sim_ticks 1829330593000 # Number of ticks simulated final_tick 1829330593000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2569577 # Simulator instruction rate (inst/s) -host_op_rate 2569575 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 78294086451 # Simulator tick rate (ticks/s) -host_mem_usage 295292 # Number of bytes of host memory used -host_seconds 23.37 # Real time elapsed on the host +host_inst_rate 1577718 # Simulator instruction rate (inst/s) +host_op_rate 1577717 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48072530632 # Simulator tick rate (ticks/s) +host_mem_usage 294780 # Number of bytes of host memory used +host_seconds 38.05 # Real time elapsed on the host sim_insts 60037737 # Number of instructions simulated sim_ops 60037737 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 857856 # Number of bytes read from this memory @@ -38,6 +38,164 @@ system.physmem.bw_total::cpu.inst 468945 # To system.physmem.bw_total::cpu.data 36537571 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 1449868 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 42507667 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 0 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 0 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 0 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 0 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 0 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 0 # Sum of mem lat for all requests +system.physmem.totBusLat 0 # Total cycles spent in databus access +system.physmem.totBankLat 0 # Total cycles spent in bank access +system.physmem.avgQLat nan # Average queueing delay per request +system.physmem.avgBankLat nan # Average bank access latency per request +system.physmem.avgBusLat nan # Average bus latency per request +system.physmem.avgMemAccLat nan # Average memory access latency +system.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.00 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.00 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 0 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate nan # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap nan # Average gap between requests system.iocache.replacements 41686 # number of replacements system.iocache.tagsinuse 1.225558 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -144,8 +302,8 @@ system.cpu.num_fp_register_writes 166520 # nu system.cpu.num_mem_refs 16115688 # number of memory refs system.cpu.num_load_insts 9747503 # Number of load instructions system.cpu.num_store_insts 6368185 # Number of store instructions -system.cpu.num_idle_cycles 3598606247.544791 # Number of idle cycles -system.cpu.num_busy_cycles 60054830.455209 # Number of busy cycles +system.cpu.num_idle_cycles 3598606250.520791 # Number of idle cycles +system.cpu.num_busy_cycles 60054827.479209 # Number of busy cycles system.cpu.not_idle_fraction 0.016414 # Percentage of non-idle cycles system.cpu.idle_fraction 0.983586 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed @@ -306,37 +464,37 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2042708 # number of replacements +system.cpu.dcache.replacements 2042707 # number of replacements system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use -system.cpu.dcache.total_refs 14038404 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2043220 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 6.870726 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 14038405 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2043219 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 6.870729 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7807768 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7807768 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 7807769 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7807769 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 5848199 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 5848199 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 199281 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 199281 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13655967 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13655967 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13655967 # number of overall hits -system.cpu.dcache.overall_hits::total 13655967 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1721710 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1721710 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 13655968 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13655968 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13655968 # number of overall hits +system.cpu.dcache.overall_hits::total 13655968 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1721709 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1721709 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 304365 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 304365 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2026075 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2026075 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2026075 # number of overall misses -system.cpu.dcache.overall_misses::total 2026075 # number of overall misses +system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses +system.cpu.dcache.overall_misses::total 2026074 # number of overall misses system.cpu.dcache.ReadReq_accesses::cpu.data 9529478 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 9529478 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6152564 # number of WriteReq accesses(hits+misses) @@ -372,20 +530,20 @@ system.cpu.dcache.writebacks::total 833491 # nu system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 992297 # number of replacements system.cpu.l2cache.tagsinuse 65424.375500 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2433229 # Total number of references to valid blocks. +system.cpu.l2cache.total_refs 2433228 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 1057460 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.301013 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.301012 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 56309.097195 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 4867.351144 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 4247.927161 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 56309.097197 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 4867.351143 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 4247.927159 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.998297 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 906782 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 811232 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1718014 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 811231 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1718013 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 833491 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 833491 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits @@ -393,11 +551,11 @@ system.cpu.l2cache.UpgradeReq_hits::total 4 # n system.cpu.l2cache.ReadExReq_hits::cpu.data 187234 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 187234 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 906782 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 998466 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1905248 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 998465 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1905247 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 906782 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 998466 # number of overall hits -system.cpu.l2cache.overall_hits::total 1905248 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 998465 # number of overall hits +system.cpu.l2cache.overall_hits::total 1905247 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 13404 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 941044 # number of ReadReq misses @@ -412,8 +570,8 @@ system.cpu.l2cache.overall_misses::cpu.inst 13404 # system.cpu.l2cache.overall_misses::cpu.data 1044755 # number of overall misses system.cpu.l2cache.overall_misses::total 1058159 # number of overall misses system.cpu.l2cache.ReadReq_accesses::cpu.inst 920186 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1738872 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2659058 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1738871 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2659057 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 833491 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 833491 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) @@ -421,23 +579,23 @@ system.cpu.l2cache.UpgradeReq_accesses::total 16 system.cpu.l2cache.ReadExReq_accesses::cpu.data 304349 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 304349 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 920186 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2043221 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2963407 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2043220 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2963406 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 920186 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2043221 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2963407 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2043220 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2963406 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014567 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533472 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533473 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.353901 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384805 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.384805 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014567 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.511327 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.511328 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.357075 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014567 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.511327 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.511328 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.357075 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index ba361e6db..e568ced30 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,218 +1,376 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.955746 # Number of seconds simulated -sim_ticks 1955746240500 # Number of ticks simulated -final_tick 1955746240500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.950813 # Number of seconds simulated +sim_ticks 1950813247500 # Number of ticks simulated +final_tick 1950813247500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1240365 # Simulator instruction rate (inst/s) -host_op_rate 1240364 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39831169965 # Simulator tick rate (ticks/s) -host_mem_usage 291792 # Number of bytes of host memory used -host_seconds 49.10 # Real time elapsed on the host -sim_insts 60902973 # Number of instructions simulated -sim_ops 60902973 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 830080 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24726528 # Number of bytes read from this memory +host_inst_rate 1287440 # Simulator instruction rate (inst/s) +host_op_rate 1287440 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41184614921 # Simulator tick rate (ticks/s) +host_mem_usage 325660 # Number of bytes of host memory used +host_seconds 47.37 # Real time elapsed on the host +sim_insts 60982794 # Number of instructions simulated +sim_ops 60982794 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 827264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24727680 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 35200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 438464 # Number of bytes read from this memory -system.physmem.bytes_read::total 28681152 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 830080 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 35200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 865280 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7699072 # Number of bytes written to this memory -system.physmem.bytes_written::total 7699072 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12970 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 386352 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 38464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 439808 # Number of bytes read from this memory +system.physmem.bytes_read::total 28684096 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 827264 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 38464 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 865728 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7706368 # Number of bytes written to this memory +system.physmem.bytes_written::total 7706368 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12926 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386370 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 550 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6851 # Number of read requests responded to by this memory -system.physmem.num_reads::total 448143 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120298 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120298 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 424431 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12643014 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1355431 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 17998 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 224193 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14665068 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 424431 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 17998 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 442430 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3936642 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3936642 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3936642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 424431 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12643014 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1355431 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 17998 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 224193 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18601710 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 341281 # number of replacements -system.l2c.tagsinuse 65229.882617 # Cycle average of tags in use -system.l2c.total_refs 2441318 # Total number of references to valid blocks. -system.l2c.sampled_refs 406256 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.009309 # Average number of references to valid blocks. -system.l2c.warmup_cycle 7648586000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55341.365970 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4865.877793 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4868.452553 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 116.161458 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 38.024844 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.844442 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.074247 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.074287 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.001772 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000580 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.995329 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 685804 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 664321 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 316190 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 108937 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1775252 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 793334 # number of Writeback hits -system.l2c.Writeback_hits::total 793334 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 183 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 549 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 732 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 35 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 22 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 57 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 126580 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 47318 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 173898 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 685804 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 790901 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 316190 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 156255 # number of demand (read+write) hits -system.l2c.demand_hits::total 1949150 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 685804 # number of overall hits -system.l2c.overall_hits::cpu0.data 790901 # number of overall hits -system.l2c.overall_hits::cpu1.inst 316190 # number of overall hits -system.l2c.overall_hits::cpu1.data 156255 # number of overall hits -system.l2c.overall_hits::total 1949150 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 12970 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 271621 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 561 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 244 # number of ReadReq misses -system.l2c.ReadReq_misses::total 285396 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2948 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1741 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4689 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 892 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 895 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1787 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 115480 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 6627 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 122107 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 12970 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 387101 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 561 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 6871 # number of demand (read+write) misses -system.l2c.demand_misses::total 407503 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 12970 # number of overall misses -system.l2c.overall_misses::cpu0.data 387101 # number of overall misses -system.l2c.overall_misses::cpu1.inst 561 # number of overall misses -system.l2c.overall_misses::cpu1.data 6871 # number of overall misses -system.l2c.overall_misses::total 407503 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 679344500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 14131444000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 29382500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 12805500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 14852976500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 2720000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 22059498 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 24779498 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2047000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 521500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 2568500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 6014286500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 347569000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6361855500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 679344500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 20145730500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 29382500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 360374500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 21214832000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 679344500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 20145730500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 29382500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 360374500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 21214832000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 698774 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 935942 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 316751 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 109181 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2060648 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 793334 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 793334 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3131 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 2290 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 5421 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 927 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 917 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1844 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 242060 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 53945 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 296005 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 698774 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1178002 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 316751 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 163126 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2356653 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 698774 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1178002 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 316751 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 163126 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2356653 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.018561 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.290211 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.001771 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.002235 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.138498 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.941552 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.760262 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.864970 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.962244 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.976009 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.969089 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.477072 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.122847 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.412517 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.018561 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.328608 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.001771 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.042121 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.172916 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.018561 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.328608 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.001771 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.042121 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.172916 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52378.141866 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52026.330807 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52375.222816 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52481.557377 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52043.394091 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 922.659430 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 12670.590465 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 5284.601834 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2294.843049 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 582.681564 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1437.325126 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52080.762903 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52447.412102 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52100.661715 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52378.141866 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52042.568994 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 52375.222816 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52448.624654 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52060.554155 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52378.141866 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52042.568994 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 52375.222816 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52448.624654 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52060.554155 # average overall miss latency +system.physmem.num_reads::cpu1.inst 601 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6872 # Number of read requests responded to by this memory +system.physmem.num_reads::total 448189 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120412 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120412 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 424061 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12675575 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1358859 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 19717 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 225449 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14703661 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 424061 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 19717 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 443778 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3950336 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3950336 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3950336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 424061 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12675575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1358859 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 19717 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 225449 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18653997 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 448189 # Total number of read requests seen +system.physmem.writeReqs 120412 # Total number of write requests seen +system.physmem.cpureqs 599134 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28684096 # Total number of bytes read from memory +system.physmem.bytesWritten 7706368 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28684096 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7706368 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 57 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 7172 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28371 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 27660 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28102 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27702 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 28190 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 28020 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27664 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27960 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28118 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 28027 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 27925 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 28196 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 28402 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28329 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27819 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27647 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7817 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7270 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7535 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7656 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7513 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7150 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7412 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7610 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7562 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7469 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7772 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 8034 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7948 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7345 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7157 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 522 # Number of times wr buffer was full causing retry +system.physmem.totGap 1950759532000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 448189 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 120934 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 7172 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 409832 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7493 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2367 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2815 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1774 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1998 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1671 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1947 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1601 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1562 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1645 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1753 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1208 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1428 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 874 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 246 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 138 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 95 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 4346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 2865774804 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 10947900804 # Sum of mem lat for all requests +system.physmem.totBusLat 1792528000 # Total cycles spent in databus access +system.physmem.totBankLat 6289598000 # Total cycles spent in bank access +system.physmem.avgQLat 6394.93 # Average queueing delay per request +system.physmem.avgBankLat 14035.15 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 24430.08 # Average memory access latency +system.physmem.avgRdBW 14.70 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 14.70 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 3.95 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.12 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.01 # Average read queue length over time +system.physmem.avgWrQLen 10.50 # Average write queue length over time +system.physmem.readRowHits 428033 # Number of row buffer hits during reads +system.physmem.writeRowHits 76777 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.51 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 63.76 # Row buffer hit rate for writes +system.physmem.avgGap 3430805.67 # Average gap between requests +system.l2c.replacements 341333 # number of replacements +system.l2c.tagsinuse 65247.038846 # Cycle average of tags in use +system.l2c.total_refs 2438074 # Total number of references to valid blocks. +system.l2c.sampled_refs 406309 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.000541 # Average number of references to valid blocks. +system.l2c.warmup_cycle 6891280002 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 55545.297156 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4807.218464 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4686.690338 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 164.376104 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 43.456784 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.847554 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.073352 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.071513 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.002508 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.000663 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.995591 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 674220 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 658221 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 328583 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 113537 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1774561 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 791464 # number of Writeback hits +system.l2c.Writeback_hits::total 791464 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 176 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 567 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 743 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 36 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 23 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 59 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 123896 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 48958 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 172854 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 674220 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 782117 # 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number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 18130000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1388519500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2151186500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 682990000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2834176500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3521576000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 701120000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4222696000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018811 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.292123 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001826 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002171 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.138548 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.944003 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.761163 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.865325 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.963077 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.976166 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.969588 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.482473 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.119476 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.414056 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018811 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.331096 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001826 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.040677 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.173060 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018811 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.331096 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001826 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.040677 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.173060 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42535.926582 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 29361.065158 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 43256.514143 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 48825.809717 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 30003.861239 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10052.565554 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10007.915883 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10035.665270 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10016.957401 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10008.965976 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 36385.548336 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 51698.021075 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 37218.321604 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42535.926582 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 31456.860953 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 43256.514143 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51595.055007 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 32166.099899 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42535.926582 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 31456.860953 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 43256.514143 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51595.055007 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 32166.099899 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -345,14 +503,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41696 # number of replacements -system.iocache.tagsinuse 0.569930 # Cycle average of tags in use +system.iocache.tagsinuse 0.562945 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41712 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1749614950000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.569930 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.035621 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.035621 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1745713328000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 0.562945 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.035184 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.035184 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses system.iocache.ReadReq_misses::total 176 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -361,14 +519,14 @@ system.iocache.demand_misses::tsunami.ide 41728 # n system.iocache.demand_misses::total 41728 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses system.iocache.overall_misses::total 41728 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21013998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21013998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 11453563806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 11453563806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 11474577804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 11474577804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 11474577804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 11474577804 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21268998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21268998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 9455401806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 9455401806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 9476670804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9476670804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 9476670804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9476670804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -385,19 +543,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119397.715909 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 119397.715909 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275644.103918 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 275644.103918 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 274985.089245 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 274985.089245 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 274985.089245 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 274985.089245 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 199825 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120846.579545 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 120846.579545 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 227555.877118 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 227555.877118 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 227105.799559 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 227105.799559 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 227105.799559 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 227105.799559 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 186741 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 24712 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 23044 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.086152 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.103671 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -411,14 +569,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41728 system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41728 # 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number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7292629022 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7292629022 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 7304745022 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7304745022 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 7304745022 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7304745022 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -427,14 +585,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67397.715909 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67397.715909 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223644.103918 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 223644.103918 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222985.089245 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 222985.089245 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222985.089245 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 222985.089245 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68840.909091 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68840.909091 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 175506.089286 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 175506.089286 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 175056.197805 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 175056.197805 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 175056.197805 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 175056.197805 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -452,22 +610,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7486542 # DTB read hits +system.cpu0.dtb.read_hits 7424678 # DTB read hits system.cpu0.dtb.read_misses 7443 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 490673 # DTB read accesses -system.cpu0.dtb.write_hits 5063820 # DTB write hits +system.cpu0.dtb.write_hits 5011102 # DTB write hits system.cpu0.dtb.write_misses 813 # DTB write misses system.cpu0.dtb.write_acv 134 # DTB write access violations system.cpu0.dtb.write_accesses 187452 # DTB write accesses -system.cpu0.dtb.data_hits 12550362 # DTB hits +system.cpu0.dtb.data_hits 12435780 # DTB hits system.cpu0.dtb.data_misses 8256 # DTB misses system.cpu0.dtb.data_acv 344 # DTB access violations system.cpu0.dtb.data_accesses 678125 # DTB accesses -system.cpu0.itb.fetch_hits 3500956 # ITB hits +system.cpu0.itb.fetch_hits 3481701 # ITB hits system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3504827 # ITB accesses +system.cpu0.itb.fetch_accesses 3485572 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -480,55 +638,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3910167080 # number of cpu cycles simulated +system.cpu0.numCycles 3900399022 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47719039 # Number of instructions committed -system.cpu0.committedOps 47719039 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44257119 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 210954 # Number of float alu accesses -system.cpu0.num_func_calls 1200899 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5607083 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44257119 # number of integer instructions -system.cpu0.num_fp_insts 210954 # number of float instructions -system.cpu0.num_int_register_reads 60839484 # number of times the integer registers were read -system.cpu0.num_int_register_writes 32982631 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 102466 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 104326 # number of times the floating registers were written -system.cpu0.num_mem_refs 12590587 # number of memory refs -system.cpu0.num_load_insts 7513713 # Number of load instructions -system.cpu0.num_store_insts 5076874 # Number of store instructions -system.cpu0.num_idle_cycles 3701181001.496715 # Number of idle cycles -system.cpu0.num_busy_cycles 208986078.503285 # Number of busy cycles -system.cpu0.not_idle_fraction 0.053447 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.946553 # Percentage of idle cycles +system.cpu0.committedInsts 47350752 # Number of instructions committed +system.cpu0.committedOps 47350752 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 43919757 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 206365 # Number of float alu accesses +system.cpu0.num_func_calls 1188579 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5567605 # number of instructions that are conditional controls +system.cpu0.num_int_insts 43919757 # number of integer instructions +system.cpu0.num_fp_insts 206365 # number of float instructions +system.cpu0.num_int_register_reads 60378447 # number of times the integer registers were read +system.cpu0.num_int_register_writes 32741783 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 100221 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 101982 # number of times the floating registers were written +system.cpu0.num_mem_refs 12475681 # number of memory refs +system.cpu0.num_load_insts 7451619 # Number of load instructions +system.cpu0.num_store_insts 5024062 # Number of store instructions +system.cpu0.num_idle_cycles 3698907701.219057 # Number of idle cycles +system.cpu0.num_busy_cycles 201491320.780943 # Number of busy cycles +system.cpu0.not_idle_fraction 0.051659 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.948341 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6789 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 164868 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 56806 40.18% 40.18% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1972 1.39% 41.67% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 420 0.30% 41.97% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 82040 58.03% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 141369 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 56268 49.08% 49.08% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1972 1.72% 50.92% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 420 0.37% 51.28% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 55848 48.72% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 114639 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1899887304000 97.18% 97.18% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 92906000 0.00% 97.18% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 760170500 0.04% 97.22% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 309335500 0.02% 97.24% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 54033794000 2.76% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1955083510000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.990529 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6813 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 162790 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 55943 40.16% 40.16% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.25% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1971 1.41% 41.66% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 443 0.32% 41.98% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 80829 58.02% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 139317 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 55450 49.07% 49.07% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1971 1.74% 50.93% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 443 0.39% 51.32% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 55007 48.68% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 113002 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1898626830000 97.36% 97.36% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 93050500 0.00% 97.36% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 759970000 0.04% 97.40% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 326793000 0.02% 97.42% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 50392837500 2.58% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1950199481000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.991187 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.680741 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810920 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.680535 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.811114 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed @@ -560,37 +718,37 @@ system.cpu0.kern.syscall::144 2 0.90% 99.10% # nu system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 222 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 503 0.34% 0.34% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3070 2.05% 2.39% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.43% # number of callpals executed -system.cpu0.kern.callpal::swpipl 134512 89.86% 92.29% # number of callpals executed -system.cpu0.kern.callpal::rdps 6676 4.46% 96.75% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.75% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed -system.cpu0.kern.callpal::rti 4333 2.89% 99.65% # number of callpals executed -system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed +system.cpu0.kern.callpal::wripir 525 0.36% 0.36% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3024 2.05% 2.41% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed +system.cpu0.kern.callpal::swpipl 132461 89.75% 92.20% # number of callpals executed +system.cpu0.kern.callpal::rdps 6674 4.52% 96.72% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.72% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.72% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.73% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.73% # number of callpals executed +system.cpu0.kern.callpal::rti 4310 2.92% 99.65% # number of callpals executed +system.cpu0.kern.callpal::callsys 381 0.26% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 149688 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6889 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1285 # number of protection mode switches +system.cpu0.kern.callpal::total 147588 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6865 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1285 -system.cpu0.kern.mode_good::user 1285 +system.cpu0.kern.mode_good::kernel 1283 +system.cpu0.kern.mode_good::user 1283 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.186529 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.186890 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.314412 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1951516113500 99.83% 99.83% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3347061000 0.17% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.314924 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1946498286500 99.83% 99.83% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3408187000 0.17% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3071 # number of times the context was actually changed +system.cpu0.kern.swap_context 3025 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -622,51 +780,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 698187 # number of replacements -system.cpu0.icache.tagsinuse 508.830635 # Cycle average of tags in use -system.cpu0.icache.total_refs 47028847 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 698699 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 67.309166 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 35739052000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 508.830635 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.993810 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.993810 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 47028847 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47028847 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47028847 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47028847 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47028847 # number of overall hits -system.cpu0.icache.overall_hits::total 47028847 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 698792 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 698792 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 698792 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 698792 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 698792 # number of overall misses -system.cpu0.icache.overall_misses::total 698792 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9694162500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 9694162500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 9694162500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 9694162500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 9694162500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 9694162500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47727639 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47727639 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47727639 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47727639 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47727639 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47727639 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014641 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014641 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014641 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014641 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014641 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014641 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13872.743964 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13872.743964 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13872.743964 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13872.743964 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13872.743964 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13872.743964 # average overall miss latency +system.cpu0.icache.replacements 686559 # number of replacements +system.cpu0.icache.tagsinuse 509.179293 # Cycle average of tags in use +system.cpu0.icache.total_refs 46672188 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 687071 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 67.929207 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 32409447000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.179293 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.994491 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.994491 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 46672188 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 46672188 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 46672188 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 46672188 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 46672188 # number of overall hits +system.cpu0.icache.overall_hits::total 46672188 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 687164 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 687164 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 687164 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 687164 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 687164 # number of overall misses +system.cpu0.icache.overall_misses::total 687164 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9577778500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 9577778500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 9577778500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 9577778500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 9577778500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 9577778500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47359352 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47359352 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47359352 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47359352 # 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average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13938.126124 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13938.126124 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13938.126124 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -675,112 +833,112 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 698792 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 698792 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 698792 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 698792 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 698792 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 698792 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8296578500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8296578500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8296578500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8296578500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8296578500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8296578500 # 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miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088494 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037878 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037878 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097377 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.097377 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097377 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097377 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22315.102246 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 22315.102246 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31136.087933 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 31136.087933 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10754.874963 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10754.874963 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7581.050427 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7581.050427 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24174.916266 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 24174.916266 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24174.916266 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 24174.916266 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -789,62 +947,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 679069 # number of writebacks -system.cpu0.dcache.writebacks::total 679069 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 938249 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 938249 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251643 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 251643 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13638 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13638 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5458 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5458 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1189892 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1189892 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1189892 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1189892 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21646065000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21646065000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7698041000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7698041000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 120630000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 120630000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 56880500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 56880500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 29344106000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 29344106000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 29344106000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 29344106000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465334500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465334500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2275733500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2275733500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3741068000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3741068000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127739 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127739 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051278 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051278 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088602 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088602 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035586 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035586 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097115 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097115 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097115 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097115 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 23070.704046 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 23070.704046 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30591.119165 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30591.119165 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8845.138583 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8845.138583 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 10421.491389 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 10421.491389 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24661.150760 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24661.150760 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24661.150760 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24661.150760 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 672349 # number of writebacks +system.cpu0.dcache.writebacks::total 672349 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 933040 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 933040 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249280 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 249280 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13436 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13436 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5731 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5731 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1182320 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1182320 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1182320 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1182320 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 18954803000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 18954803000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7263044000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7263044000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 117630500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 117630500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31985000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31985000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 26217847000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 26217847000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 26217847000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 26217847000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465453500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465453500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2285524000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2285524000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3750977500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3750977500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128076 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128076 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051328 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051328 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088494 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088494 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037878 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037878 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097377 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097377 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097377 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097377 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 20315.102246 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 20315.102246 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29136.087933 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29136.087933 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8754.874963 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8754.874963 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5581.050427 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5581.050427 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22174.916266 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22174.916266 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22174.916266 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22174.916266 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -856,22 +1014,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2425080 # DTB read hits +system.cpu1.dtb.read_hits 2500235 # DTB read hits system.cpu1.dtb.read_misses 2992 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 239363 # DTB read accesses -system.cpu1.dtb.write_hits 1761000 # DTB write hits +system.cpu1.dtb.write_hits 1820988 # DTB write hits system.cpu1.dtb.write_misses 341 # DTB write misses system.cpu1.dtb.write_acv 29 # DTB write access violations system.cpu1.dtb.write_accesses 105247 # DTB write accesses -system.cpu1.dtb.data_hits 4186080 # DTB hits +system.cpu1.dtb.data_hits 4321223 # DTB hits system.cpu1.dtb.data_misses 3333 # DTB misses system.cpu1.dtb.data_acv 29 # DTB access violations system.cpu1.dtb.data_accesses 344610 # DTB accesses -system.cpu1.itb.fetch_hits 1964871 # ITB hits +system.cpu1.itb.fetch_hits 1990033 # ITB hits system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1966087 # ITB accesses +system.cpu1.itb.fetch_accesses 1991249 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -884,51 +1042,51 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3911492481 # number of cpu cycles simulated +system.cpu1.numCycles 3901626495 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 13183934 # Number of instructions committed -system.cpu1.committedOps 13183934 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12160396 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 172922 # Number of float alu accesses -system.cpu1.num_func_calls 412685 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1307407 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12160396 # number of integer instructions -system.cpu1.num_fp_insts 172922 # number of float instructions -system.cpu1.num_int_register_reads 16740645 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8924669 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 90471 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 92344 # number of times the floating registers were written -system.cpu1.num_mem_refs 4209624 # number of memory refs -system.cpu1.num_load_insts 2439377 # Number of load instructions -system.cpu1.num_store_insts 1770247 # Number of store instructions -system.cpu1.num_idle_cycles 3861803254.998025 # Number of idle cycles -system.cpu1.num_busy_cycles 49689226.001975 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012703 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987297 # Percentage of idle cycles +system.cpu1.committedInsts 13632042 # Number of instructions committed +system.cpu1.committedOps 13632042 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12571491 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 180459 # Number of float alu accesses +system.cpu1.num_func_calls 426717 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1355011 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12571491 # number of integer instructions +system.cpu1.num_fp_insts 180459 # number of float instructions +system.cpu1.num_int_register_reads 17311598 # number of times the integer registers were read +system.cpu1.num_int_register_writes 9221787 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 94168 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 96184 # number of times the floating registers were written +system.cpu1.num_mem_refs 4345531 # number of memory refs +system.cpu1.num_load_insts 2514982 # Number of load instructions +system.cpu1.num_store_insts 1830549 # Number of store instructions +system.cpu1.num_idle_cycles 3850258507.998026 # Number of idle cycles +system.cpu1.num_busy_cycles 51367987.001974 # Number of busy cycles +system.cpu1.not_idle_fraction 0.013166 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.986834 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2704 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 78634 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 26575 38.36% 38.36% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1967 2.84% 41.20% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 503 0.73% 41.93% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 40225 58.07% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 69270 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 25736 48.16% 48.16% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1967 3.68% 51.84% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 503 0.94% 52.78% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25233 47.22% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 53439 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1909053778500 97.61% 97.61% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 705460500 0.04% 97.65% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 351339000 0.02% 97.67% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 45634904500 2.33% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1955745482500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968429 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2717 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 80899 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 27499 38.50% 38.50% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1966 2.75% 41.25% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 525 0.74% 41.99% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 41433 58.01% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 71423 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 26615 48.22% 48.22% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1966 3.56% 51.78% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 525 0.95% 52.73% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 26090 47.27% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 55196 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1907138262500 97.76% 97.76% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 705201000 0.04% 97.80% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 364168000 0.02% 97.82% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 42604858000 2.18% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1950812489500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.967853 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.627296 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.771460 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.629691 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.772804 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed @@ -944,81 +1102,81 @@ system.cpu1.kern.syscall::74 10 9.62% 97.12% # nu system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 420 0.59% 0.59% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1995 2.79% 3.38% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.38% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.39% # number of callpals executed -system.cpu1.kern.callpal::swpipl 63027 88.05% 91.44% # number of callpals executed -system.cpu1.kern.callpal::rdps 2168 3.03% 94.47% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.47% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 94.47% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.48% # number of callpals executed -system.cpu1.kern.callpal::rti 3772 5.27% 99.75% # number of callpals executed -system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed +system.cpu1.kern.callpal::wripir 443 0.60% 0.60% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.60% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed +system.cpu1.kern.callpal::swpctx 2085 2.82% 3.43% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.43% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.44% # number of callpals executed +system.cpu1.kern.callpal::swpipl 65093 88.17% 91.61% # number of callpals executed +system.cpu1.kern.callpal::rdps 2167 2.94% 94.55% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.55% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.55% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.56% # number of callpals executed +system.cpu1.kern.callpal::rti 3838 5.20% 99.75% # number of callpals executed +system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 71584 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2065 # number of protection mode switches -system.cpu1.kern.mode_switch::user 464 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2874 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 891 -system.cpu1.kern.mode_good::user 464 -system.cpu1.kern.mode_good::idle 427 -system.cpu1.kern.mode_switch_good::kernel 0.431477 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 73828 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2126 # number of protection mode switches +system.cpu1.kern.mode_switch::user 465 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2924 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 915 +system.cpu1.kern.mode_good::user 465 +system.cpu1.kern.mode_good::idle 450 +system.cpu1.kern.mode_switch_good::kernel 0.430386 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.148573 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.329817 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 17893399500 0.91% 0.91% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1709951500 0.09% 1.00% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1936142128000 99.00% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1996 # number of times the context was actually changed -system.cpu1.icache.replacements 316204 # number of replacements -system.cpu1.icache.tagsinuse 447.456269 # Cycle average of tags in use -system.cpu1.icache.total_refs 12870545 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 316716 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 40.637495 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1953875803000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 447.456269 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.873938 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.873938 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 12870545 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12870545 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12870545 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12870545 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12870545 # number of overall hits -system.cpu1.icache.overall_hits::total 12870545 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 316752 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 316752 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 316752 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 316752 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 316752 # number of overall misses -system.cpu1.icache.overall_misses::total 316752 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4179857000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4179857000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4179857000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4179857000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4179857000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4179857000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13187297 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13187297 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13187297 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13187297 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13187297 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13187297 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024019 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024019 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024019 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024019 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024019 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024019 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13195.992448 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13195.992448 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13195.992448 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13195.992448 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13195.992448 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13195.992448 # average overall miss latency +system.cpu1.kern.mode_switch_good::idle 0.153899 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.331822 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 18665784500 0.96% 0.96% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1711228500 0.09% 1.04% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1930435473000 98.96% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2086 # number of times the context was actually changed +system.cpu1.icache.replacements 328648 # number of replacements +system.cpu1.icache.tagsinuse 446.257828 # Cycle average of tags in use +system.cpu1.icache.total_refs 13306209 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 329160 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 40.424745 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1948917036000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 446.257828 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.871597 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.871597 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 13306209 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 13306209 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 13306209 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 13306209 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 13306209 # number of overall hits +system.cpu1.icache.overall_hits::total 13306209 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 329196 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 329196 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 329196 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 329196 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 329196 # number of overall misses +system.cpu1.icache.overall_misses::total 329196 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4347354500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4347354500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4347354500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4347354500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4347354500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4347354500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13635405 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13635405 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13635405 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13635405 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13635405 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13635405 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024143 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024143 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024143 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024143 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024143 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024143 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13205.976075 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13205.976075 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13205.976075 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13205.976075 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13205.976075 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13205.976075 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1027,112 +1185,112 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316752 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 316752 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 316752 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 316752 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 316752 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 316752 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3546353000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3546353000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3546353000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3546353000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3546353000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3546353000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024019 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024019 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024019 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024019 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024019 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024019 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11195.992448 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11195.992448 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11195.992448 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11195.992448 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11195.992448 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11195.992448 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 329196 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 329196 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 329196 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 329196 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 329196 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 329196 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3688962500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3688962500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3688962500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3688962500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3688962500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3688962500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024143 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024143 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024143 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024143 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024143 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024143 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11205.976075 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11205.976075 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11205.976075 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11205.976075 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11205.976075 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11205.976075 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 166318 # number of replacements -system.cpu1.dcache.tagsinuse 487.121043 # Cycle average of tags in use -system.cpu1.dcache.total_refs 4017452 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 166830 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 24.081113 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 63885131000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 487.121043 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.951408 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.951408 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 2260833 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2260833 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1643465 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1643465 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48243 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 48243 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50839 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 50839 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3904298 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3904298 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3904298 # number of overall hits -system.cpu1.dcache.overall_hits::total 3904298 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 118301 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 118301 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 62725 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 62725 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8915 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 8915 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5846 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 5846 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 181026 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 181026 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 181026 # number of overall misses -system.cpu1.dcache.overall_misses::total 181026 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1440550500 # 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number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9347 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6143 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 6143 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 187990 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 187990 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 187990 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 187990 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1247220000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1247220000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1036791500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1036791500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 66696000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 66696000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32229500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32229500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2284011500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2284011500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2284011500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2284011500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19381000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19381000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 723171500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 723171500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742552500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742552500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050253 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050253 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036709 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036709 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.156916 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.156916 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103995 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103995 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044586 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.044586 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044586 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.044586 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10120.581648 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10120.581648 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16011.234827 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16011.234827 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7135.551514 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7135.551514 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5246.540778 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5246.540778 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12149.643598 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12149.643598 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12149.643598 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12149.643598 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 369a1e336..997f2e448 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,52 +1,210 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.914421 # Number of seconds simulated -sim_ticks 1914420945000 # Number of ticks simulated -final_tick 1914420945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.910582 # Number of seconds simulated +sim_ticks 1910582068000 # Number of ticks simulated +final_tick 1910582068000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1299276 # Simulator instruction rate (inst/s) -host_op_rate 1299275 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44286723014 # Simulator tick rate (ticks/s) -host_mem_usage 288696 # Number of bytes of host memory used -host_seconds 43.23 # Real time elapsed on the host -sim_insts 56164879 # Number of instructions simulated -sim_ops 56164879 # Number of ops (including micro ops) simulated +host_inst_rate 1092208 # Simulator instruction rate (inst/s) +host_op_rate 1092208 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37180157619 # Simulator tick rate (ticks/s) +host_mem_usage 321564 # Number of bytes of host memory used +host_seconds 51.39 # Real time elapsed on the host +sim_insts 56125446 # Number of instructions simulated +sim_ops 56125446 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24860096 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652096 # Number of bytes read from this memory -system.physmem.bytes_read::total 28362752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24847488 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory +system.physmem.bytes_read::total 28350400 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7404800 # Number of bytes written to this memory -system.physmem.bytes_written::total 7404800 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 7392192 # Number of bytes written to this memory +system.physmem.bytes_written::total 7392192 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 13290 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388439 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41439 # Number of read requests responded to by this memory -system.physmem.num_reads::total 443168 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115700 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115700 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 444291 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12985700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1385325 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14815316 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 444291 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 444291 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3867906 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3867906 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3867906 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 444291 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12985700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1385325 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18683222 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 388242 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory +system.physmem.num_reads::total 442975 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115503 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115503 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 445184 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13005193 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1388243 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14838619 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 445184 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 445184 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3869078 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3869078 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3869078 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 445184 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13005193 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1388243 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18707698 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 442975 # Total number of read requests seen +system.physmem.writeReqs 115503 # Total number of write requests seen +system.physmem.cpureqs 559567 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28350400 # Total number of bytes read from memory +system.physmem.bytesWritten 7392192 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28350400 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7392192 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 51 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 130 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28021 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 27576 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 27724 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27399 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 28096 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27946 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27736 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27622 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 27577 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27238 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 27723 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27886 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27600 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 27483 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27641 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27656 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7552 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7244 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7137 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6901 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7584 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7386 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7208 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7095 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7184 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6832 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7257 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7441 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7265 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7126 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7165 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7126 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 404 # Number of times wr buffer was full causing retry +system.physmem.totGap 1910570168000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 442975 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 115907 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 130 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 404639 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5269 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2334 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2835 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2403 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1793 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2009 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1658 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1931 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1592 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1535 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1623 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1782 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1204 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1459 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 903 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 267 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 101 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 4142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4753 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4893 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4987 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 2804911869 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 10779125869 # Sum of mem lat for all requests +system.physmem.totBusLat 1771696000 # Total cycles spent in databus access +system.physmem.totBankLat 6202518000 # Total cycles spent in bank access +system.physmem.avgQLat 6332.72 # Average queueing delay per request +system.physmem.avgBankLat 14003.57 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 24336.29 # Average memory access latency +system.physmem.avgRdBW 14.84 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 3.87 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 14.84 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 3.87 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.12 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.01 # Average read queue length over time +system.physmem.avgWrQLen 14.48 # Average write queue length over time +system.physmem.readRowHits 423327 # Number of row buffer hits during reads +system.physmem.writeRowHits 74914 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.58 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 64.86 # Row buffer hit rate for writes +system.physmem.avgGap 3421030.31 # Average gap between requests system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.347664 # Cycle average of tags in use +system.iocache.tagsinuse 1.342666 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1748614160000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.347664 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.084229 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.084229 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1745691885000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.342666 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.083917 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.083917 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -55,14 +213,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 11444054806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 11444054806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 11464727804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 11464727804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 11464727804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 11464727804 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 9475235806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 9475235806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 9496163804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9496163804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 9496163804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9496163804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -79,19 +237,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275415.258134 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 275415.258134 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 274768.790989 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 274768.790989 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 274768.790989 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 274768.790989 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 199052 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228033.206729 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 228033.206729 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 227589.306267 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 227589.306267 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 227589.306267 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 227589.306267 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 189601 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 24614 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 23064 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.086942 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.220647 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -105,14 +263,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676998 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11676998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9283350806 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 9283350806 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 9295027804 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9295027804 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 9295027804 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9295027804 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11931000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7312468500 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7312468500 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 7324399500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7324399500 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 7324399500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7324399500 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -121,14 +279,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67497.098266 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67497.098266 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223415.258134 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 223415.258134 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222768.790989 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 222768.790989 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222768.790989 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 222768.790989 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68965.317919 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68965.317919 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 175983.550732 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 175983.550732 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 175539.832235 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 175539.832235 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 175539.832235 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 175539.832235 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -146,22 +304,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9062432 # DTB read hits +system.cpu.dtb.read_hits 9055970 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_accesses 728856 # DTB read accesses -system.cpu.dtb.write_hits 6354530 # DTB write hits +system.cpu.dtb.write_hits 6351685 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 15416962 # DTB hits +system.cpu.dtb.data_hits 15407655 # DTB hits system.cpu.dtb.data_misses 11471 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020787 # DTB accesses -system.cpu.itb.fetch_hits 4974475 # ITB hits +system.cpu.itb.fetch_hits 4974178 # ITB hits system.cpu.itb.fetch_misses 5006 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979481 # ITB accesses +system.cpu.itb.fetch_accesses 4979184 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -174,51 +332,51 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3828841890 # number of cpu cycles simulated +system.cpu.numCycles 3821164136 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56164879 # Number of instructions committed -system.cpu.committedOps 56164879 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52037464 # Number of integer alu accesses +system.cpu.committedInsts 56125446 # Number of instructions committed +system.cpu.committedOps 56125446 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 51999916 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses -system.cpu.num_func_calls 1482804 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6466141 # number of instructions that are conditional controls -system.cpu.num_int_insts 52037464 # number of integer instructions +system.cpu.num_func_calls 1482010 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6463546 # number of instructions that are conditional controls +system.cpu.num_int_insts 51999916 # number of integer instructions system.cpu.num_fp_insts 324393 # number of float instructions -system.cpu.num_int_register_reads 71294843 # number of times the integer registers were read -system.cpu.num_int_register_writes 38508157 # number of times the integer registers were written +system.cpu.num_int_register_reads 71242345 # number of times the integer registers were read +system.cpu.num_int_register_writes 38476410 # number of times the integer registers were written system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written -system.cpu.num_mem_refs 15469580 # number of memory refs -system.cpu.num_load_insts 9099291 # Number of load instructions -system.cpu.num_store_insts 6370289 # Number of store instructions -system.cpu.num_idle_cycles 3589214946.998125 # Number of idle cycles -system.cpu.num_busy_cycles 239626943.001875 # Number of busy cycles -system.cpu.not_idle_fraction 0.062585 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.937415 # Percentage of idle cycles +system.cpu.num_mem_refs 15460271 # number of memory refs +system.cpu.num_load_insts 9092827 # Number of load instructions +system.cpu.num_store_insts 6367444 # Number of store instructions +system.cpu.num_idle_cycles 3587332264.998123 # Number of idle cycles +system.cpu.num_busy_cycles 233831871.001878 # Number of busy cycles +system.cpu.not_idle_fraction 0.061194 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.938806 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211993 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74900 40.89% 40.89% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 133 0.07% 40.96% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211969 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74892 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1930 1.05% 42.02% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106213 57.98% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183176 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73533 49.31% 49.31% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 133 0.09% 49.40% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 106200 57.98% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183153 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73525 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1930 1.29% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73534 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149130 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1856400078000 96.97% 96.97% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 92059500 0.00% 96.97% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 736279500 0.04% 97.01% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 57191794000 2.99% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1914420211000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73525 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149111 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1855918085500 97.14% 97.14% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 91164500 0.00% 97.14% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 736454000 0.04% 97.18% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 53835630000 2.82% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1910581334000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981747 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::31 0.692326 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814135 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814134 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -254,32 +412,32 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed +system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175957 91.22% 93.41% # number of callpals executed -system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175936 91.22% 93.42% # number of callpals executed +system.cpu.kern.callpal::rdps 6831 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5155 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192901 # number of callpals executed +system.cpu.kern.callpal::total 192878 # number of callpals executed system.cpu.kern.mode_switch::kernel 5901 # number of protection mode switches -system.cpu.kern.mode_switch::user 1740 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1910 -system.cpu.kern.mode_good::user 1740 +system.cpu.kern.mode_switch::user 1741 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1911 +system.cpu.kern.mode_good::user 1741 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.323674 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.323843 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392278 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 45169028500 2.36% 2.36% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5015931500 0.26% 2.62% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1864235249000 97.38% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392483 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 45587423000 2.39% 2.39% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5075517000 0.27% 2.65% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1859918392000 97.35% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -312,51 +470,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 927876 # number of replacements -system.cpu.icache.tagsinuse 508.762321 # Cycle average of tags in use -system.cpu.icache.total_refs 55248171 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 928387 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 59.509850 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 35489468000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 508.762321 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.993676 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.993676 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 55248171 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55248171 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55248171 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55248171 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55248171 # number of overall hits -system.cpu.icache.overall_hits::total 55248171 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 928547 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 928547 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 928547 # 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average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13647.123628 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13647.123628 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13647.123628 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -365,104 +523,104 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928547 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 928547 # 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number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15027234 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15027234 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15027234 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120435 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120435 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049452 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049452 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086010 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086010 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091375 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091375 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091375 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091375 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21247.653610 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21247.653610 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28263.090339 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28263.090339 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13220.519073 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13220.519073 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22802.025405 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22802.025405 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22802.025405 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22802.025405 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -471,54 +629,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 835360 # number of writebacks -system.cpu.dcache.writebacks::total 835360 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069478 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069478 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304397 # 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number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 192755000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 192755000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31447748000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 31447748000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31447748000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 31447748000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424905500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424905500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011694000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011694000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3436599500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3436599500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120416 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120416 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049456 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049456 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086264 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086264 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091369 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091369 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091369 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091369 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21683.271185 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21683.271185 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27128.935239 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27128.935239 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11158.031838 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11158.031838 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22889.817487 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 44990.809162 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -629,66 +787,66 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74188 # number of writebacks -system.cpu.l2cache.writebacks::total 74188 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 73991 # number of writebacks +system.cpu.l2cache.writebacks::total 73991 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13290 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12299252211 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12860525290 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1331550000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1331550000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1891670000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1891670000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3223220000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3223220000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014319 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250366 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141600 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383925 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383925 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014313 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279505 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173353 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014313 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279505 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173353 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40021.369451 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40020.127220 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40020.185094 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 43076.923077 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 43076.923077 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40007.355018 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40007.355018 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40021.369451 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40016.288651 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40016.456571 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40021.369451 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40016.288651 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40016.456571 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383643 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383643 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014319 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279528 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173360 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014319 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279528 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173360 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42232.737321 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 29437.969642 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 30034.166374 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36795.652729 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36795.652729 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42232.737321 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31647.554013 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31997.564926 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42232.737321 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31647.554013 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31997.564926 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index b7f76478e..3841577ac 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.912097 # Nu sim_ticks 912096763500 # Number of ticks simulated final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1783031 # Simulator instruction rate (inst/s) -host_op_rate 2295648 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26389770183 # Simulator tick rate (ticks/s) -host_mem_usage 380112 # Number of bytes of host memory used -host_seconds 34.56 # Real time elapsed on the host +host_inst_rate 1752000 # Simulator instruction rate (inst/s) +host_op_rate 2255696 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25930494646 # Simulator tick rate (ticks/s) +host_mem_usage 382232 # Number of bytes of host memory used +host_seconds 35.17 # Real time elapsed on the host sim_insts 61625970 # Number of instructions simulated sim_ops 79343340 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory @@ -66,6 +66,164 @@ system.physmem.bw_total::cpu1.dtb.walker 211 # To system.physmem.bw_total::cpu1.inst 235234 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 6988969 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 62341162 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 0 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 0 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 0 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 0 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 0 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 0 # Sum of mem lat for all requests +system.physmem.totBusLat 0 # Total cycles spent in databus access +system.physmem.totBankLat 0 # Total cycles spent in bank access +system.physmem.avgQLat nan # Average queueing delay per request +system.physmem.avgBankLat nan # Average bank access latency per request +system.physmem.avgBusLat nan # Average bus latency per request +system.physmem.avgMemAccLat nan # Average memory access latency +system.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.00 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.00 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 0 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate nan # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap nan # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 206441d13..ccb9a5402 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.332810 # Nu sim_ticks 2332810264000 # Number of ticks simulated final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1681370 # Simulator instruction rate (inst/s) -host_op_rate 2162138 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64929680145 # Simulator tick rate (ticks/s) -host_mem_usage 380112 # Number of bytes of host memory used -host_seconds 35.93 # Real time elapsed on the host +host_inst_rate 1184768 # Simulator instruction rate (inst/s) +host_op_rate 1523538 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45752340761 # Simulator tick rate (ticks/s) +host_mem_usage 382236 # Number of bytes of host memory used +host_seconds 50.99 # Real time elapsed on the host sim_insts 60408639 # Number of instructions simulated sim_ops 77681819 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory @@ -49,6 +49,164 @@ system.physmem.bw_total::cpu.itb.walker 82 # To system.physmem.bw_total::cpu.inst 302262 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 5181496 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 54942169 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 0 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 0 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 0 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 0 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 0 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 0 # Sum of mem lat for all requests +system.physmem.totBusLat 0 # Total cycles spent in databus access +system.physmem.totBankLat 0 # Total cycles spent in bank access +system.physmem.avgQLat nan # Average queueing delay per request +system.physmem.avgBankLat nan # Average bank access latency per request +system.physmem.avgBusLat nan # Average bus latency per request +system.physmem.avgMemAccLat nan # Average memory access latency +system.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.00 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.00 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 0 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate nan # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap nan # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -61,114 +219,6 @@ system.realview.nvmem.bw_inst_read::cpu.inst 9 system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) -system.cpu.l2cache.replacements 62243 # number of replacements -system.cpu.l2cache.tagsinuse 50007.272909 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1669922 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 127628 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 13.084292 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 36899.582990 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 7014.720482 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6089.015357 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.107036 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.092911 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.763050 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7507 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3129 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 838871 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 366771 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1216278 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 592643 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 592643 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 113739 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 113739 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 7507 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 3129 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 838871 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 480510 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1330017 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 7507 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 3129 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 838871 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 480510 # number of overall hits -system.cpu.l2cache.overall_hits::total 1330017 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 10604 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 9871 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 20483 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2919 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2919 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133468 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133468 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 10604 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143339 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 153951 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 10604 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143339 # number of overall misses -system.cpu.l2cache.overall_misses::total 153951 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7512 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3132 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 849475 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 376642 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1236761 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 592643 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 592643 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2945 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2945 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 247207 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 247207 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7512 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 3132 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 849475 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 623849 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1483968 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7512 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 3132 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 849475 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 623849 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1483968 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000666 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000958 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012483 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026208 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016562 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991171 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539904 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.539904 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000666 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000958 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012483 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.229766 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.103743 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000666 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000958 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012483 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.229766 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.103743 # miss rate for overall accesses -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 57863 # number of writebacks -system.cpu.l2cache.writebacks::total 57863 # number of writebacks -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -347,6 +397,114 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.writebacks::writebacks 592643 # number of writebacks system.cpu.dcache.writebacks::total 592643 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 62243 # number of replacements +system.cpu.l2cache.tagsinuse 50007.272909 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1669922 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 127628 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 13.084292 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 36899.582990 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 7014.720482 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6089.015357 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.107036 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.092911 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.763050 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7507 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3129 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 838871 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 366771 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1216278 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 592643 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 592643 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 113739 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 113739 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 7507 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 3129 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 838871 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 480510 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1330017 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 7507 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 3129 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 838871 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 480510 # number of overall hits +system.cpu.l2cache.overall_hits::total 1330017 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 10604 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 9871 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 20483 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2919 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2919 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133468 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133468 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 10604 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143339 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 153951 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 10604 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143339 # number of overall misses +system.cpu.l2cache.overall_misses::total 153951 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7512 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3132 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 849475 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 376642 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1236761 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 592643 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 592643 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2945 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2945 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 247207 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 247207 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7512 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 3132 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 849475 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 623849 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1483968 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7512 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 3132 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 849475 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 623849 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1483968 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000666 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000958 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012483 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026208 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.016562 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991171 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539904 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.539904 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000666 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000958 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012483 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.229766 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.103743 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000666 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000958 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012483 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.229766 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.103743 # miss rate for overall accesses +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 57863 # number of writebacks +system.cpu.l2cache.writebacks::total 57863 # number of writebacks +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index db4dfffca..70af125f4 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,71 +1,229 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.203606 # Number of seconds simulated -sim_ticks 1203606499000 # Number of ticks simulated -final_tick 1203606499000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.182883 # Number of seconds simulated +sim_ticks 1182883077500 # Number of ticks simulated +final_tick 1182883077500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 418240 # Simulator instruction rate (inst/s) -host_op_rate 532998 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8191230777 # Simulator tick rate (ticks/s) -host_mem_usage 386340 # Number of bytes of host memory used -host_seconds 146.94 # Real time elapsed on the host -sim_insts 61455549 # Number of instructions simulated -sim_ops 78317886 # Number of ops (including micro ops) simulated +host_inst_rate 330156 # Simulator instruction rate (inst/s) +host_op_rate 420694 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6355289452 # Simulator tick rate (ticks/s) +host_mem_usage 400808 # Number of bytes of host memory used +host_seconds 186.13 # Real time elapsed on the host +sim_insts 61450599 # Number of instructions simulated +sim_ops 78301940 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 354084 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4259252 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 364956 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5307824 # Number of bytes read from this memory -system.physmem.bytes_read::total 62191076 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 354084 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 364956 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 719040 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4163904 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 393380 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4712308 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 323164 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4776304 # Number of bytes read from this memory +system.physmem.bytes_read::total 62110116 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 393380 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 323164 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 716544 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4085952 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7191248 # Number of bytes written to this memory +system.physmem.bytes_written::total 7113296 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 11751 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 66623 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5784 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82961 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6655190 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 65061 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12365 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73702 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5131 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 74656 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6653925 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 63843 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821897 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43124154 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 294186 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3538741 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 303219 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4409933 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51670605 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 294186 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 303219 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 597405 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3459523 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14124 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2501103 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5974750 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3459523 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43124154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 294186 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3552865 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 303219 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6911036 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 57645355 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::total 820679 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43879664 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 108 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 332560 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3983748 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 216 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 273200 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4037850 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52507401 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 332560 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 273200 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 605761 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3454232 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14372 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2544921 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6013524 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3454232 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43879664 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 108 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 332560 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3998120 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 216 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 273200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6582771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 58520925 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6653925 # Total number of read requests seen +system.physmem.writeReqs 820679 # Total number of write requests seen +system.physmem.cpureqs 271820 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 425851200 # Total number of bytes read from memory +system.physmem.bytesWritten 52523456 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 62110116 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7113296 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 132 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 11750 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 415519 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 415704 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 415458 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 415465 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 415493 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 415211 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 415304 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 415265 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 422311 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 415383 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 415455 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 415586 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 415355 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 415574 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 415386 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 415324 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50680 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50792 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50611 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50651 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51629 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51413 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51506 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51453 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51654 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51491 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51429 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51462 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51424 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51618 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51455 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51411 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 1182878628500 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 6825 # Categorize read packet sizes +system.physmem.readPktSize::3 6488064 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 159036 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 756836 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 63843 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 11750 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 6597380 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 40502 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 11414 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1777 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 643 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 481 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 367 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 201 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 155 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 117 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 69 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 44 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 35674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 35682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 3516126974 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 123045854974 # Sum of mem lat for all requests +system.physmem.totBusLat 26615172000 # Total cycles spent in databus access +system.physmem.totBankLat 92914556000 # Total cycles spent in bank access +system.physmem.avgQLat 528.44 # Average queueing delay per request +system.physmem.avgBankLat 13964.15 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 18492.59 # Average memory access latency +system.physmem.avgRdBW 360.01 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 44.40 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 52.51 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.01 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 2.53 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.10 # Average read queue length over time +system.physmem.avgWrQLen 15.12 # Average write queue length over time +system.physmem.readRowHits 6625021 # Number of row buffer hits during reads +system.physmem.writeRowHits 788582 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.57 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 96.09 # Row buffer hit rate for writes +system.physmem.avgGap 158253.02 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -76,245 +234,245 @@ system.realview.nvmem.num_reads::cpu0.inst 5 # system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 56 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 56 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 56 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 70188 # number of replacements -system.l2c.tagsinuse 53228.072476 # Cycle average of tags in use -system.l2c.total_refs 1643838 # Total number of references to valid blocks. -system.l2c.sampled_refs 135351 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.145001 # Average number of references to valid blocks. +system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 68923 # number of replacements +system.l2c.tagsinuse 53039.119781 # Cycle average of tags in use +system.l2c.total_refs 1673706 # Total number of references to valid blocks. +system.l2c.sampled_refs 134114 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.479726 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 40453.574010 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 0.000402 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.003089 # 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number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13448680359 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3031674 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 162498448983 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 176148132599 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000241 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001102 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013475 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036694 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024611 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017540 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.801371 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.848843 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.821333 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.724005 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.830123 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.768889 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.540897 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.577062 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.559043 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000241 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001102 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013475 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.221647 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.278314 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.106353 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000241 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001102 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013475 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.221647 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.278314 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.106353 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 37040.715108 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 38590.549561 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 49002 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 39071.170301 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45826.746479 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 39478.424022 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10031.671086 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10030.762382 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10031.276179 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10025.812057 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10063.204641 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10042.887283 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 32165.809682 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34622.318054 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 33438.062745 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 37040.715108 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32839.279207 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 49002 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 39071.170301 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35158.109968 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 34270.848407 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 37040.715108 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32839.279207 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 49002 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 39071.170301 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35158.109968 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 34270.848407 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -498,27 +656,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 4800569 # DTB read hits -system.cpu0.dtb.read_misses 2116 # DTB read misses -system.cpu0.dtb.write_hits 4101188 # DTB write hits -system.cpu0.dtb.write_misses 405 # DTB write misses +system.cpu0.dtb.read_hits 7072899 # DTB read hits +system.cpu0.dtb.read_misses 3762 # DTB read misses +system.cpu0.dtb.write_hits 5658444 # DTB write hits +system.cpu0.dtb.write_misses 809 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1539 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1807 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 91 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 139 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 203 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 4802685 # DTB read accesses -system.cpu0.dtb.write_accesses 4101593 # DTB write accesses +system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7076661 # DTB read accesses +system.cpu0.dtb.write_accesses 5659253 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 8901757 # DTB hits -system.cpu0.dtb.misses 2521 # DTB misses -system.cpu0.dtb.accesses 8904278 # DTB accesses -system.cpu0.itb.inst_hits 19425317 # ITB inst hits -system.cpu0.itb.inst_misses 1350 # ITB inst misses +system.cpu0.dtb.hits 12731343 # DTB hits +system.cpu0.dtb.misses 4571 # DTB misses +system.cpu0.dtb.accesses 12735914 # DTB accesses +system.cpu0.itb.inst_hits 29570664 # ITB inst hits +system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -527,86 +685,86 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1347 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # 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Number of instructions committed -system.cpu0.committedOps 25051835 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 22684157 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4364 # Number of float alu accesses -system.cpu0.num_func_calls 868672 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 2620308 # number of instructions that are conditional controls -system.cpu0.num_int_insts 22684157 # number of integer instructions -system.cpu0.num_fp_insts 4364 # number of float instructions -system.cpu0.num_int_register_reads 128951400 # number of times the integer registers were read -system.cpu0.num_int_register_writes 23731440 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3980 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 384 # number of times the floating registers were written -system.cpu0.num_mem_refs 9388218 # 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number of float instructions +system.cpu0.num_int_register_reads 190095843 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36231130 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written +system.cpu0.num_mem_refs 13399483 # number of memory refs +system.cpu0.num_load_insts 7410404 # Number of load instructions +system.cpu0.num_store_insts 5989079 # Number of store instructions +system.cpu0.num_idle_cycles 2224921697.356119 # Number of idle cycles +system.cpu0.num_busy_cycles 140844457.643881 # Number of busy cycles +system.cpu0.not_idle_fraction 0.059534 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.940466 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 34019 # number of quiesce instructions executed -system.cpu0.icache.replacements 283204 # number of replacements -system.cpu0.icache.tagsinuse 509.502445 # Cycle average of tags in use -system.cpu0.icache.total_refs 19141584 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 283716 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 67.467411 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 75588601000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.502445 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.995122 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.995122 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 19141584 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 19141584 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 19141584 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 19141584 # 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number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 3929859500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 3929859500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 19425300 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 19425300 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 19425300 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 19425300 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 19425300 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 19425300 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014605 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014605 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014605 # 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number of replacements +system.cpu0.icache.tagsinuse 509.627794 # Cycle average of tags in use +system.cpu0.icache.total_refs 29144714 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 425933 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 68.425583 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 74931906000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.627794 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.995367 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.995367 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 29144714 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 29144714 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29144714 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 29144714 # 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number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5794506500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5794506500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 29570647 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 29570647 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 29570647 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 29570647 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 29570647 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 29570647 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014404 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014404 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014404 # 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number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12325579 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033402 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.033402 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025786 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.025786 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059319 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059319 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047690 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047690 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030007 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.030007 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030007 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.030007 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13738.038886 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13738.038886 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 29156.888484 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 29156.888484 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9466.395112 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9466.395112 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5936.099253 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5936.099253 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19645.160593 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19645.160593 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19645.160593 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 19645.160593 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -737,66 +895,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 205058 # number of writebacks -system.cpu0.dcache.writebacks::total 205058 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 146457 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 146457 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 116961 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 116961 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7881 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7881 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7690 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7690 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 263418 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 263418 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 263418 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 263418 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1698225500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1698225500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3965521500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3965521500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 54497000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 54497000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 50753000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 50753000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.writebacks::writebacks 306622 # number of writebacks +system.cpu0.dcache.writebacks::total 306622 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228156 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 228156 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141693 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 141693 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9329 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9329 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7493 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7493 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 369849 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 369849 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 369849 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 369849 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2678104000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2678104000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3847941000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3847941000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69654000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69654000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29513000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29513000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5663747000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 5663747000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5663747000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 5663747000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12130745000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12130745000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1193494500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1193494500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13324239500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13324239500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031846 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031846 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029465 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029465 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062741 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062741 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.061252 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.061252 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030743 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.030743 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030743 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.030743 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11595.386359 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11595.386359 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33904.647703 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33904.647703 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 6914.985408 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6914.985408 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6599.869961 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6599.869961 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6526045000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6526045000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6526045000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6526045000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13559793500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13559793500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128518500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128518500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14688312000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14688312000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033402 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033402 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025786 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025786 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059319 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059319 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047671 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047671 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030007 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.030007 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030007 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.030007 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11738.038886 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11738.038886 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27156.888484 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27156.888484 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7466.395112 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7466.395112 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3938.742827 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3938.742827 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21500.987024 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21500.987024 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21500.987024 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21500.987024 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17645.160593 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17645.160593 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17645.160593 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17645.160593 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -806,27 +964,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 10589201 # DTB read hits -system.cpu1.dtb.read_misses 5231 # DTB read misses -system.cpu1.dtb.write_hits 7383574 # DTB write hits -system.cpu1.dtb.write_misses 1834 # DTB write misses +system.cpu1.dtb.read_hits 8308478 # DTB read hits +system.cpu1.dtb.read_misses 3644 # DTB read misses +system.cpu1.dtb.write_hits 5825596 # DTB write hits +system.cpu1.dtb.write_misses 1434 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2257 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1965 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 193 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 10594432 # DTB read accesses -system.cpu1.dtb.write_accesses 7385408 # DTB write accesses +system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 8312122 # DTB read accesses +system.cpu1.dtb.write_accesses 5827030 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 17972775 # DTB hits -system.cpu1.dtb.misses 7065 # DTB misses -system.cpu1.dtb.accesses 17979840 # DTB accesses -system.cpu1.itb.inst_hits 43338256 # ITB inst hits -system.cpu1.itb.inst_misses 3017 # ITB inst misses +system.cpu1.dtb.hits 14134074 # DTB hits +system.cpu1.dtb.misses 5078 # DTB misses +system.cpu1.dtb.accesses 14139152 # DTB accesses +system.cpu1.itb.inst_hits 33188345 # ITB inst hits +system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -835,86 +993,86 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1458 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 43341273 # ITB inst accesses -system.cpu1.itb.hits 43338256 # DTB hits -system.cpu1.itb.misses 3017 # DTB misses -system.cpu1.itb.accesses 43341273 # DTB accesses -system.cpu1.numCycles 2407212998 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 33190516 # ITB inst accesses +system.cpu1.itb.hits 33188345 # DTB hits +system.cpu1.itb.misses 2171 # DTB misses +system.cpu1.itb.accesses 33190516 # DTB accesses +system.cpu1.numCycles 2364324255 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 42407344 # Number of instructions committed -system.cpu1.committedOps 53266051 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 47734651 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5457 # Number of float alu accesses -system.cpu1.num_func_calls 1334953 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 5482869 # number of instructions that are conditional controls -system.cpu1.num_int_insts 47734651 # number of integer instructions -system.cpu1.num_fp_insts 5457 # number of float instructions -system.cpu1.num_int_register_reads 274813771 # number of times the integer registers were read -system.cpu1.num_int_register_writes 51971016 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3577 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1884 # number of times the floating registers were written -system.cpu1.num_mem_refs 18681443 # number of memory refs -system.cpu1.num_load_insts 10999206 # Number of load instructions -system.cpu1.num_store_insts 7682237 # Number of store instructions -system.cpu1.num_idle_cycles 1827286039.250482 # Number of idle cycles -system.cpu1.num_busy_cycles 579926958.749518 # Number of busy cycles -system.cpu1.not_idle_fraction 0.240912 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.759088 # Percentage of idle cycles +system.cpu1.committedInsts 32577871 # Number of instructions committed +system.cpu1.committedOps 41082259 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 37307050 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses +system.cpu1.num_func_calls 961975 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3732476 # number of instructions that are conditional controls +system.cpu1.num_int_insts 37307050 # number of integer instructions +system.cpu1.num_fp_insts 6793 # number of float instructions +system.cpu1.num_int_register_reads 213626787 # number of times the integer registers were read +system.cpu1.num_int_register_writes 39450306 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written +system.cpu1.num_mem_refs 14671800 # number of memory refs +system.cpu1.num_load_insts 8630367 # Number of load instructions +system.cpu1.num_store_insts 6041433 # Number of store instructions +system.cpu1.num_idle_cycles 1868325738.966939 # Number of idle cycles +system.cpu1.num_busy_cycles 495998516.033061 # Number of busy cycles +system.cpu1.not_idle_fraction 0.209784 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.790216 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 56704 # number of quiesce instructions executed -system.cpu1.icache.replacements 582576 # number of replacements -system.cpu1.icache.tagsinuse 479.066528 # Cycle average of tags in use -system.cpu1.icache.total_refs 42755164 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 583088 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 73.325405 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 92849627500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 479.066528 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.935677 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.935677 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 42755164 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 42755164 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 42755164 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 42755164 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 42755164 # number of overall hits -system.cpu1.icache.overall_hits::total 42755164 # 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number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 33188341 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 33188341 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 33188341 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 33188341 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 33188341 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014154 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014154 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014154 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014154 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014154 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.014154 # 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Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 6944275 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 6944275 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4825543 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4825543 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81753 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 81753 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82700 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 82700 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 11769818 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 11769818 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 11769818 # number of overall hits +system.cpu1.dcache.overall_hits::total 11769818 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 170271 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 170271 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 149767 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 149767 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11060 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 11060 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10038 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10038 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 320038 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 320038 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 320038 # number of overall misses +system.cpu1.dcache.overall_misses::total 320038 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2152137500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2152137500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4507881000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 4507881000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 91883000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 91883000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 51759500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 51759500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6660018500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6660018500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6660018500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6660018500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 7114546 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 7114546 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4975310 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4975310 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92813 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 92813 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92738 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 92738 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 12089856 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 12089856 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 12089856 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 12089856 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023933 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.023933 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030102 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.030102 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119164 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119164 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108240 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108240 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026472 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.026472 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026472 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.026472 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12639.483529 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12639.483529 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30099.294237 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 30099.294237 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8307.685353 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8307.685353 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5156.355848 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5156.355848 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20810.086615 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20810.086615 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20810.086615 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20810.086615 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1045,66 +1203,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 366504 # number of writebacks -system.cpu1.dcache.writebacks::total 366504 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 253127 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 253127 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 178055 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 178055 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13099 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13099 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10394 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10394 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 431182 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 431182 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 431182 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 431182 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2770994500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2770994500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5292766500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5292766500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89595500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89595500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 42224000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 42224000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8063761000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 8063761000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8063761000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 8063761000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 170066366500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 170066366500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40314514000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40314514000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 210380880500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 210380880500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027062 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.027062 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027390 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027390 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.104844 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.104844 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.083244 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.083244 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027196 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027196 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027196 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027196 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10947.052270 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10947.052270 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29725.458426 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29725.458426 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6839.873273 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6839.873273 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4062.343660 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4062.343660 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 265110 # number of writebacks +system.cpu1.dcache.writebacks::total 265110 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170271 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 170271 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149767 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 149767 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11060 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11060 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10034 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10034 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 320038 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 320038 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 320038 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 320038 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1811595500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1811595500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4208347000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4208347000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 69763000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 69763000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31693500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31693500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6019942500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 6019942500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6019942500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6019942500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168625975500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168625975500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17666930000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17666930000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186292905500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186292905500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023933 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023933 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030102 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030102 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119164 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119164 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108197 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108197 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026472 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026472 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026472 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026472 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10639.483529 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10639.483529 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28099.294237 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28099.294237 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6307.685353 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6307.685353 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3158.610724 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3158.610724 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18701.525110 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18701.525110 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18701.525110 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18701.525110 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18810.086615 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18810.086615 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18810.086615 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18810.086615 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1126,10 +1284,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 522347967555 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 522347967555 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 522347967555 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 522347967555 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 446709885400 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 446709885400 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 446709885400 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 446709885400 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index d1abeb8c8..e97027568 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,54 +1,212 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.624627 # Number of seconds simulated -sim_ticks 2624627401000 # Number of ticks simulated -final_tick 2624627401000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.603636 # Number of seconds simulated +sim_ticks 2603636076000 # Number of ticks simulated +final_tick 2603636076000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 463403 # Simulator instruction rate (inst/s) -host_op_rate 589674 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20203281292 # Simulator tick rate (ticks/s) -host_mem_usage 381220 # Number of bytes of host memory used -host_seconds 129.91 # Real time elapsed on the host -sim_insts 60201162 # Number of instructions simulated -sim_ops 76605148 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 123834568 # Number of bytes read from this memory +host_inst_rate 485506 # Simulator instruction rate (inst/s) +host_op_rate 617798 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20998999798 # Simulator tick rate (ticks/s) +host_mem_usage 395692 # Number of bytes of host memory used +host_seconds 123.99 # Real time elapsed on the host +sim_insts 60197128 # Number of instructions simulated +sim_ops 76599899 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 705824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9049808 # Number of bytes read from this memory -system.physmem.bytes_read::total 133590712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 705824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 705824 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3677120 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 704800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9050128 # Number of bytes read from this memory +system.physmem.bytes_read::total 132438832 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 704800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704800 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3677504 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6693192 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15479321 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 6693576 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17231 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141437 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15637997 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57455 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 17215 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141442 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494089 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57461 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811473 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47181771 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 73 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 268924 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3448035 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50898925 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 268924 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 268924 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1401006 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1149143 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2550149 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1401006 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47181771 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 73 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 268924 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4597178 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53449074 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::total 811479 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47120023 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 270698 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3475957 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50866875 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 270698 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 270698 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1412449 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1158408 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2570857 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1412449 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47120023 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 270698 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4634365 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53437732 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15494089 # Total number of read requests seen +system.physmem.writeReqs 811479 # Total number of write requests seen +system.physmem.cpureqs 213984 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 991621696 # Total number of bytes read from memory +system.physmem.bytesWritten 51934656 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 132438832 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6693576 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 336 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4510 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 968203 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 968434 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 967969 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 967930 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 967593 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 967540 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 967550 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 967729 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 974541 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 967896 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 968053 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 968056 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 968172 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 968177 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 968121 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 967789 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50184 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50353 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 49939 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 49917 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50620 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50586 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50545 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50763 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 50925 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50957 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50984 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51005 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51208 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51196 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51260 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51037 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 2603631716000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 6652 # Categorize read packet sizes +system.physmem.readPktSize::3 15335424 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 152013 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 754018 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 57461 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4510 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 15419651 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 56393 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 11796 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2238 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1067 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 810 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 578 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 393 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 217 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 134 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 89 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 74 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 49 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 35279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 3755940486 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 281915228486 # Sum of mem lat for all requests +system.physmem.totBusLat 61975012000 # Total cycles spent in databus access +system.physmem.totBankLat 216184276000 # Total cycles spent in bank access +system.physmem.avgQLat 242.42 # Average queueing delay per request +system.physmem.avgBankLat 13953.00 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 18195.41 # Average memory access latency +system.physmem.avgRdBW 380.86 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 19.95 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 50.87 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 2.51 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.11 # Average read queue length over time +system.physmem.avgWrQLen 12.38 # Average write queue length over time +system.physmem.readRowHits 15449465 # Number of row buffer hits during reads +system.physmem.writeRowHits 784611 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 96.69 # Row buffer hit rate for writes +system.physmem.avgGap 159677.46 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -69,26 +227,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14996727 # DTB read hits -system.cpu.dtb.read_misses 7361 # DTB read misses -system.cpu.dtb.write_hits 11231610 # DTB write hits -system.cpu.dtb.write_misses 2211 # DTB write misses +system.cpu.dtb.read_hits 14995523 # DTB read hits +system.cpu.dtb.read_misses 7332 # DTB read misses +system.cpu.dtb.write_hits 11230789 # DTB write hits +system.cpu.dtb.write_misses 2203 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 3487 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 186 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15004088 # DTB read accesses -system.cpu.dtb.write_accesses 11233821 # DTB write accesses +system.cpu.dtb.read_accesses 15002855 # DTB read accesses +system.cpu.dtb.write_accesses 11232992 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26228337 # DTB hits -system.cpu.dtb.misses 9572 # DTB misses -system.cpu.dtb.accesses 26237909 # DTB accesses -system.cpu.itb.inst_hits 61495131 # ITB inst hits +system.cpu.dtb.hits 26226312 # DTB hits +system.cpu.dtb.misses 9535 # DTB misses +system.cpu.dtb.accesses 26235847 # DTB accesses +system.cpu.itb.inst_hits 61491068 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -105,79 +263,79 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61499602 # ITB inst accesses -system.cpu.itb.hits 61495131 # DTB hits +system.cpu.itb.inst_accesses 61495539 # ITB inst accesses +system.cpu.itb.hits 61491068 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61499602 # DTB accesses -system.cpu.numCycles 5249254802 # number of cpu cycles simulated +system.cpu.itb.accesses 61495539 # DTB accesses +system.cpu.numCycles 5207272152 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60201162 # Number of instructions committed -system.cpu.committedOps 76605148 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68872531 # Number of integer alu accesses +system.cpu.committedInsts 60197128 # Number of instructions committed +system.cpu.committedOps 76599899 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68867725 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2139915 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7948068 # number of instructions that are conditional controls -system.cpu.num_int_insts 68872531 # number of integer instructions +system.cpu.num_func_calls 2139710 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7947746 # number of instructions that are conditional controls +system.cpu.num_int_insts 68867725 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 394780405 # number of times the integer registers were read -system.cpu.num_int_register_writes 74180740 # number of times the integer registers were written +system.cpu.num_int_register_reads 394752708 # number of times the integer registers were read +system.cpu.num_int_register_writes 74175592 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27395680 # number of memory refs -system.cpu.num_load_insts 15660706 # Number of load instructions -system.cpu.num_store_insts 11734974 # Number of store instructions -system.cpu.num_idle_cycles 4573851223.612257 # Number of idle cycles -system.cpu.num_busy_cycles 675403578.387743 # Number of busy cycles -system.cpu.not_idle_fraction 0.128667 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.871333 # Percentage of idle cycles +system.cpu.num_mem_refs 27393681 # number of memory refs +system.cpu.num_load_insts 15659530 # Number of load instructions +system.cpu.num_store_insts 11734151 # Number of store instructions +system.cpu.num_idle_cycles 4579082960.576241 # Number of idle cycles +system.cpu.num_busy_cycles 628189191.423759 # Number of busy cycles +system.cpu.not_idle_fraction 0.120637 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.879363 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83018 # number of quiesce instructions executed -system.cpu.icache.replacements 855895 # number of replacements -system.cpu.icache.tagsinuse 510.920698 # Cycle average of tags in use -system.cpu.icache.total_refs 60638724 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 856407 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 70.805965 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 19300651000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.920698 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.997892 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.997892 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 60638724 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60638724 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60638724 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60638724 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60638724 # number of overall hits -system.cpu.icache.overall_hits::total 60638724 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 856407 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 856407 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 856407 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 856407 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 856407 # number of overall misses -system.cpu.icache.overall_misses::total 856407 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11564476500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11564476500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11564476500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11564476500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11564476500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11564476500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 61495131 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61495131 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61495131 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61495131 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61495131 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61495131 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013926 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.013926 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.013926 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.013926 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.013926 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.013926 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13503.481989 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13503.481989 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13503.481989 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13503.481989 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13503.481989 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13503.481989 # average overall miss latency +system.cpu.kern.inst.quiesce 83000 # number of quiesce instructions executed +system.cpu.icache.replacements 855498 # number of replacements +system.cpu.icache.tagsinuse 510.984783 # Cycle average of tags in use +system.cpu.icache.total_refs 60635058 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 856010 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 70.834521 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 18657050000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.984783 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.998017 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.998017 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 60635058 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60635058 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60635058 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60635058 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60635058 # number of overall hits +system.cpu.icache.overall_hits::total 60635058 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 856010 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 856010 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 856010 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 856010 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 856010 # number of overall misses +system.cpu.icache.overall_misses::total 856010 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11542526000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11542526000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11542526000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11542526000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11542526000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11542526000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 61491068 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61491068 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61491068 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61491068 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61491068 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61491068 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013921 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.013921 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.013921 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.013921 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.013921 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.013921 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13484.101821 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13484.101821 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13484.101821 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13484.101821 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13484.101821 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13484.101821 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -186,112 +344,112 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856407 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 856407 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 856407 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 856407 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 856407 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 856407 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9851662500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9851662500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9851662500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9851662500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9851662500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9851662500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 353004500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 353004500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 353004500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 353004500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013926 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.013926 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.013926 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11503.481989 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11503.481989 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11503.481989 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11503.481989 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11503.481989 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11503.481989 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856010 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 856010 # 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number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 288141500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 288141500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 288141500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013921 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.013921 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.013921 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11484.101821 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11484.101821 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11484.101821 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11484.101821 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11484.101821 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11484.101821 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 627232 # number of replacements -system.cpu.dcache.tagsinuse 511.878513 # Cycle average of tags in use -system.cpu.dcache.total_refs 23656893 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 627744 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37.685574 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 653137000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.878513 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999763 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999763 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13196266 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13196266 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9973744 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9973744 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236294 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236294 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247690 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247690 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23170010 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23170010 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23170010 # number of overall hits -system.cpu.dcache.overall_hits::total 23170010 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 368699 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 368699 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250547 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250547 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 11397 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 11397 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 619246 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 619246 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 619246 # number of overall misses -system.cpu.dcache.overall_misses::total 619246 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5200667500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5200667500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8968842000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8968842000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154755000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 154755000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14169509500 # 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average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13558.859649 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21425.015139 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 21425.015139 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21425.015139 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21425.015139 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -300,54 +458,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # 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number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4463269500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4463269500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8467748000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8467748000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131961000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131961000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12931017500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12931017500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12931017500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12931017500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182084322500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182084322500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41323476000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41323476000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 223407798500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 223407798500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027180 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027180 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024505 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024505 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046013 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046013 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026030 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026030 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026030 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.026030 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12105.455941 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12105.455941 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33797.044068 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33797.044068 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11578.573309 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11578.573309 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20881.874893 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20881.874893 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20881.874893 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20881.874893 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 596013 # number of writebacks +system.cpu.dcache.writebacks::total 596013 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368763 # 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number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18708092000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18708092000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200795832500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 200795832500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027187 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027187 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024503 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024503 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046028 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046028 # 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number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 31792706500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198477942500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198742782500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 10599 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143044 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 153651 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 224010 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 98006 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4761203811 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5158872406 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 224010 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 98006 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 397346579 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4761203811 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5158872406 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 197466551 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166688827565 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166886294116 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 9174375606 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 9174375606 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 197466551 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 175863203171 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 176060669722 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025938 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016422 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991031 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991031 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537775 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537775 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for demand accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012405 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025931 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016414 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991028 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991028 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537899 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537899 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227860 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.102794 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012405 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227862 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.102817 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227860 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.102794 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40003.203015 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40001.521452 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40002.392344 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40004.872955 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40004.872955 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40002.162503 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40002.162503 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40003.203015 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40002.118318 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40002.193139 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40003.203015 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40002.118318 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40002.193139 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012405 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227862 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.102817 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37489.063025 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39492.807466 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38455.347716 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10032.142758 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10032.142758 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32825.399929 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 32825.399929 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37489.063025 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33284.890041 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33575.260857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37489.063025 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33284.890041 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33575.260857 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -607,10 +765,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1246144703911 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1246144703911 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1246144703911 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1246144703911 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1052670853165 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1052670853165 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1052670853165 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1052670853165 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 551274795..867a605e4 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,13 +4,13 @@ sim_seconds 5.112041 # Nu sim_ticks 5112040968500 # Number of ticks simulated final_tick 5112040968500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 923075 # Simulator instruction rate (inst/s) -host_op_rate 1890063 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23616389220 # Simulator tick rate (ticks/s) -host_mem_usage 353316 # Number of bytes of host memory used -host_seconds 216.46 # Real time elapsed on the host +host_inst_rate 468346 # Simulator instruction rate (inst/s) +host_op_rate 958973 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11982395829 # Simulator tick rate (ticks/s) +host_mem_usage 354180 # Number of bytes of host memory used +host_seconds 426.63 # Real time elapsed on the host sim_insts 199810236 # Number of instructions simulated -sim_ops 409125915 # Number of ops (including micro ops) simulated +sim_ops 409125920 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2464640 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory @@ -46,6 +46,164 @@ system.physmem.bw_total::cpu.itb.walker 63 # To system.physmem.bw_total::cpu.inst 167022 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2073561 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 4540583 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 0 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 0 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 0 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 0 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 0 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 0 # Sum of mem lat for all requests +system.physmem.totBusLat 0 # Total cycles spent in databus access +system.physmem.totBankLat 0 # Total cycles spent in bank access +system.physmem.avgQLat nan # Average queueing delay per request +system.physmem.avgBankLat nan # Average bank access latency per request +system.physmem.avgBusLat nan # Average bus latency per request +system.physmem.avgMemAccLat nan # Average memory access latency +system.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.00 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.00 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 0 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate nan # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap nan # Average gap between requests system.iocache.replacements 47569 # number of replacements system.iocache.tagsinuse 0.042402 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -106,22 +264,22 @@ system.cpu.numCycles 10224081960 # nu system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 199810236 # Number of instructions committed -system.cpu.committedOps 409125915 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 374289906 # Number of integer alu accesses +system.cpu.committedOps 409125920 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 374289911 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 39954535 # number of instructions that are conditional controls -system.cpu.num_int_insts 374289906 # number of integer instructions +system.cpu.num_conditional_control_insts 39954536 # number of instructions that are conditional controls +system.cpu.num_int_insts 374289911 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 915450684 # number of times the integer registers were read -system.cpu.num_int_register_writes 480322735 # number of times the integer registers were written +system.cpu.num_int_register_reads 915450709 # number of times the integer registers were read +system.cpu.num_int_register_writes 480322748 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 35624588 # number of memory refs system.cpu.num_load_insts 27216588 # Number of load instructions system.cpu.num_store_insts 8408000 # Number of store instructions -system.cpu.num_idle_cycles 9770609605.299961 # Number of idle cycles -system.cpu.num_busy_cycles 453472354.700038 # Number of busy cycles +system.cpu.num_idle_cycles 9770609595.971962 # Number of idle cycles +system.cpu.num_busy_cycles 453472364.028039 # Number of busy cycles system.cpu.not_idle_fraction 0.044353 # Percentage of non-idle cycles system.cpu.idle_fraction 0.955647 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed @@ -173,7 +331,7 @@ system.cpu.itb_walker_cache.tagsinuse 3.026483 # Cy system.cpu.itb_walker_cache.total_refs 8029 # Total number of references to valid blocks. system.cpu.itb_walker_cache.sampled_refs 3346 # Sample count of references to valid blocks. system.cpu.itb_walker_cache.avg_refs 2.399582 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5102019603000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.warmup_cycle 5102019608500 # Cycle when the warmup percentage was hit. system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026483 # Average occupied blocks per requestor system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189155 # Average percentage of cache occupancy system.cpu.itb_walker_cache.occ_percent::total 0.189155 # Average percentage of cache occupancy @@ -221,7 +379,7 @@ system.cpu.dtb_walker_cache.tagsinuse 5.013746 # Cy system.cpu.dtb_walker_cache.total_refs 13015 # Total number of references to valid blocks. system.cpu.dtb_walker_cache.sampled_refs 7611 # Sample count of references to valid blocks. system.cpu.dtb_walker_cache.avg_refs 1.710025 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5101206381500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.warmup_cycle 5101206384000 # Cycle when the warmup percentage was hit. system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013746 # Average occupied blocks per requestor system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313359 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.occ_percent::total 0.313359 # Average percentage of cache occupancy @@ -313,7 +471,7 @@ system.cpu.dcache.writebacks::writebacks 1534848 # nu system.cpu.dcache.writebacks::total 1534848 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 106558 # number of replacements -system.cpu.l2cache.tagsinuse 64822.149249 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 64822.149247 # Cycle average of tags in use system.cpu.l2cache.total_refs 3456224 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 170677 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 20.250086 # Average number of references to valid blocks. @@ -321,8 +479,8 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.occ_blocks::writebacks 51981.453140 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132114 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2434.994085 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 10405.564956 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2434.994083 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 10405.564957 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index b8216d15c..11970e7f1 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,80 +1,238 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.187896 # Number of seconds simulated -sim_ticks 5187896410000 # Number of ticks simulated -final_tick 5187896410000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.191113 # Number of seconds simulated +sim_ticks 5191112864000 # Number of ticks simulated +final_tick 5191112864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 812782 # Simulator instruction rate (inst/s) -host_op_rate 1566838 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32873266023 # Simulator tick rate (ticks/s) -host_mem_usage 347504 # Number of bytes of host memory used -host_seconds 157.82 # Real time elapsed on the host -sim_insts 128269216 # Number of instructions simulated -sim_ops 247270559 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2867328 # Number of bytes read from this memory +host_inst_rate 414932 # Simulator instruction rate (inst/s) +host_op_rate 799857 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 16795720800 # Simulator tick rate (ticks/s) +host_mem_usage 384032 # Number of bytes of host memory used +host_seconds 309.07 # Real time elapsed on the host +sim_insts 128244614 # Number of instructions simulated +sim_ops 247214605 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2852352 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 826944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8996288 # Number of bytes read from this memory -system.physmem.bytes_read::total 12690880 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 826944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 826944 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8107200 # Number of bytes written to this memory -system.physmem.bytes_written::total 8107200 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 44802 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 825984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9026368 # Number of bytes read from this memory +system.physmem.bytes_read::total 12705024 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 825984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 825984 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8129280 # Number of bytes written to this memory +system.physmem.bytes_written::total 8129280 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 44568 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12921 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140567 # Number of read requests responded to by this memory -system.physmem.num_reads::total 198295 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126675 # Number of write requests responded to by this memory -system.physmem.num_writes::total 126675 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 552696 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 12906 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141037 # Number of read requests responded to by this memory +system.physmem.num_reads::total 198516 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 127020 # Number of write requests responded to by this memory +system.physmem.num_writes::total 127020 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 549468 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 159399 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1734092 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2446248 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 159399 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 159399 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1562714 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1562714 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1562714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 552696 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 159115 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1738812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2447457 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 159115 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 159115 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1565999 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1565999 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1565999 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 549468 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 159399 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1734092 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4008962 # Total bandwidth to/from this memory (bytes/s) -system.iocache.replacements 47503 # number of replacements -system.iocache.tagsinuse 0.106662 # Cycle average of tags in use +system.physmem.bw_total::cpu.inst 159115 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1738812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4013456 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 198516 # Total number of read requests seen +system.physmem.writeReqs 127020 # Total number of write requests seen +system.physmem.cpureqs 331314 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 12705024 # Total number of bytes read from memory +system.physmem.bytesWritten 8129280 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 12705024 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 8129280 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 88 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 1599 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 12028 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 12411 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 11776 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 12503 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 12483 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 12755 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 12240 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 12788 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 12663 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 12687 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 12141 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 12548 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 12236 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 12474 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 11907 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 12788 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7431 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7966 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7373 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 8083 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7981 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 8219 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7719 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 8332 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 8225 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 8161 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7712 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 8125 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7893 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7991 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7528 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 8281 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 5191112800500 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 198516 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 127020 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 1599 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 158090 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11440 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 7599 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2597 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3245 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2511 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1497 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1744 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1556 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1514 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1291 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1281 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1081 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 569 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 355 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 264 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 88 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 4625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5480 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5523 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5523 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5523 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5523 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5523 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5523 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 898 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 2876260269 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 6438486269 # Sum of mem lat for all requests +system.physmem.totBusLat 793712000 # Total cycles spent in databus access +system.physmem.totBankLat 2768514000 # Total cycles spent in bank access +system.physmem.avgQLat 14495.23 # Average queueing delay per request +system.physmem.avgBankLat 13952.23 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 32447.47 # Average memory access latency +system.physmem.avgRdBW 2.45 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 2.45 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 1.57 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.00 # Average read queue length over time +system.physmem.avgWrQLen 9.06 # Average write queue length over time +system.physmem.readRowHits 179831 # Number of row buffer hits during reads +system.physmem.writeRowHits 78085 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.63 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 61.47 # Row buffer hit rate for writes +system.physmem.avgGap 15946355.55 # Average gap between requests +system.iocache.replacements 47506 # number of replacements +system.iocache.tagsinuse 0.117830 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47519 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47522 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 5044925516000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.106662 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.006666 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.006666 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 838 # number of ReadReq misses -system.iocache.ReadReq_misses::total 838 # number of ReadReq misses +system.iocache.warmup_cycle 5044498925000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.117830 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.007364 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.007364 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 841 # number of ReadReq misses +system.iocache.ReadReq_misses::total 841 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47558 # number of demand (read+write) misses -system.iocache.demand_misses::total 47558 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47558 # number of overall misses -system.iocache.overall_misses::total 47558 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 130086932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 130086932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10696163160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10696163160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10826250092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10826250092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10826250092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10826250092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 838 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 838 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47561 # number of demand (read+write) misses +system.iocache.demand_misses::total 47561 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47561 # number of overall misses +system.iocache.overall_misses::total 47561 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 133668932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 133668932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9598301160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 9598301160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 9731970092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9731970092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 9731970092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9731970092 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 841 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 841 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47558 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47558 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47558 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47558 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47561 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47561 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47561 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47561 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -83,40 +241,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 155235.002387 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 155235.002387 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 228941.848459 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 228941.848459 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227643.090374 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 227643.090374 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227643.090374 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 227643.090374 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 90078 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158940.466112 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 158940.466112 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 205443.089897 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 205443.089897 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 204620.804693 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 204620.804693 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 204620.804693 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 204620.804693 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 78425 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11025 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10368 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.170340 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.564140 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 838 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 838 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 841 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 841 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47558 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47558 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47558 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47558 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86510932 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 86510932 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8266723160 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8266723160 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8353234092 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8353234092 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8353234092 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8353234092 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47561 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47561 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47561 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47561 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 89906992 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 89906992 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7166703132 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7166703132 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7256610124 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7256610124 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7256610124 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7256610124 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -125,14 +283,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 103235.002387 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 103235.002387 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 176941.848459 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 176941.848459 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175643.090374 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 175643.090374 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175643.090374 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 175643.090374 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 106904.865636 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 106904.865636 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 153396.899229 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 153396.899229 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 152574.801287 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 152574.801287 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 152574.801287 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 152574.801287 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -146,75 +304,75 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 10375792820 # number of cpu cycles simulated +system.cpu.numCycles 10382225728 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128269216 # Number of instructions committed -system.cpu.committedOps 247270559 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 232005526 # Number of integer alu accesses +system.cpu.committedInsts 128244614 # Number of instructions committed +system.cpu.committedOps 247214605 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 231949866 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23152914 # number of instructions that are conditional controls -system.cpu.num_int_insts 232005526 # number of integer instructions +system.cpu.num_conditional_control_insts 23149724 # number of instructions that are conditional controls +system.cpu.num_int_insts 231949866 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 567048885 # number of times the integer registers were read -system.cpu.num_int_register_writes 293217624 # number of times the integer registers were written +system.cpu.num_int_register_reads 566905537 # number of times the integer registers were read +system.cpu.num_int_register_writes 293156479 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 22238817 # number of memory refs -system.cpu.num_load_insts 13875768 # Number of load instructions -system.cpu.num_store_insts 8363049 # Number of store instructions -system.cpu.num_idle_cycles 9774979498.742117 # Number of idle cycles -system.cpu.num_busy_cycles 600813321.257884 # Number of busy cycles -system.cpu.not_idle_fraction 0.057905 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.942095 # Percentage of idle cycles +system.cpu.num_mem_refs 22227093 # number of memory refs +system.cpu.num_load_insts 13866667 # Number of load instructions +system.cpu.num_store_insts 8360426 # Number of store instructions +system.cpu.num_idle_cycles 9781583042.374115 # Number of idle cycles +system.cpu.num_busy_cycles 600642685.625884 # Number of busy cycles +system.cpu.not_idle_fraction 0.057853 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.942147 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 793131 # number of replacements -system.cpu.icache.tagsinuse 510.350730 # Cycle average of tags in use -system.cpu.icache.total_refs 144484487 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 793643 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 182.052241 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 160314386000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.350730 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996779 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996779 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 144484487 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144484487 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144484487 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144484487 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144484487 # number of overall hits -system.cpu.icache.overall_hits::total 144484487 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 793650 # 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number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145278137 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145278137 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145278137 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145278137 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145278137 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005463 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005463 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005463 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005463 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005463 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005463 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13684.447804 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13684.447804 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13684.447804 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13684.447804 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13684.447804 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13684.447804 # average overall miss latency +system.cpu.icache.replacements 790930 # number of replacements +system.cpu.icache.tagsinuse 510.376048 # Cycle average of tags in use +system.cpu.icache.total_refs 144455336 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 791442 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 182.521696 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 159759301000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.376048 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996828 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996828 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 144455336 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144455336 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144455336 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144455336 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144455336 # number of overall hits +system.cpu.icache.overall_hits::total 144455336 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 791449 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 791449 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 791449 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 791449 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 791449 # number of overall misses +system.cpu.icache.overall_misses::total 791449 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 10871283000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 10871283000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 10871283000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 10871283000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 10871283000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 10871283000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145246785 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145246785 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145246785 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145246785 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145246785 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145246785 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005449 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005449 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005449 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005449 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005449 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005449 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13735.923603 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13735.923603 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13735.923603 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13735.923603 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13735.923603 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13735.923603 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -223,80 +381,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 793650 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 793650 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 793650 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 793650 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 793650 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 793650 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9273362000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9273362000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9273362000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9273362000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9273362000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9273362000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005463 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005463 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005463 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005463 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005463 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005463 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11684.447804 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11684.447804 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11684.447804 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11684.447804 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11684.447804 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11684.447804 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791449 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 791449 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 791449 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 791449 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 791449 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 791449 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9288385000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9288385000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9288385000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9288385000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9288385000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9288385000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005449 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005449 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005449 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11735.923603 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11735.923603 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11735.923603 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11735.923603 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11735.923603 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11735.923603 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 3599 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 3.063919 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 7874 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 3610 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.181163 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5162043257000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.063919 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191495 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.191495 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7876 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7876 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 3663 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 3.069768 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 7696 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 3675 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.094150 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5164936292000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.069768 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191861 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.191861 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7696 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7696 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7878 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7878 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7878 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7878 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4455 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4455 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4455 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4455 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4455 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4455 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 43455000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 43455000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 43455000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 43455000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 43455000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 43455000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12331 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12331 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7698 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7698 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7698 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7698 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4528 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4528 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4528 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4528 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4528 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4528 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 46136000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 46136000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 46136000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 46136000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 46136000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 46136000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12224 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12224 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12333 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12333 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12333 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12333 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.361285 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.361285 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.361226 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.361226 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.361226 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.361226 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9754.208754 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9754.208754 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9754.208754 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9754.208754 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9754.208754 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9754.208754 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12226 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12226 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12226 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12226 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.370419 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.370419 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.370358 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.370358 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.370358 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.370358 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10189.045936 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10189.045936 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10189.045936 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10189.045936 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10189.045936 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10189.045936 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -305,78 +463,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 700 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 700 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4455 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4455 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4455 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4455 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4455 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4455 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 34545000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 34545000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 34545000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 34545000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 34545000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 34545000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.361285 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.361285 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.361226 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.361226 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.361226 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.361226 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7754.208754 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7754.208754 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7754.208754 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7754.208754 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7754.208754 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7754.208754 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 884 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 884 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4528 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4528 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4528 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4528 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4528 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4528 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 37080000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 37080000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 37080000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 37080000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 37080000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 37080000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.370419 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.370419 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.370358 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.370358 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.370358 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.370358 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8189.045936 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8189.045936 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8189.045936 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8189.045936 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8189.045936 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8189.045936 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 7423 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 5.046109 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 13594 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 7438 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.827642 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5159593477000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.046109 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315382 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.315382 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13598 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13598 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13598 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13598 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13598 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13598 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8635 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8635 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8635 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8635 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8635 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8635 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 91582000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 91582000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 91582000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 91582000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 91582000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 91582000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22233 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 22233 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22233 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 22233 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22233 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 22233 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.388387 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.388387 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.388387 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.388387 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.388387 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.388387 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10605.906196 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10605.906196 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10605.906196 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10605.906196 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10605.906196 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10605.906196 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 8012 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 5.053256 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 13052 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 8025 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.626417 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5162707625000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.053256 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315829 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.315829 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13068 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13068 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13068 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13068 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13068 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13068 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9194 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 9194 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9194 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 9194 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9194 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 9194 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 98984000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 98984000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 98984000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 98984000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 98984000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 98984000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22262 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 22262 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22262 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 22262 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22262 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 22262 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.412991 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.412991 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.412991 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.412991 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.412991 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.412991 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10766.151838 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10766.151838 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10766.151838 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10766.151838 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10766.151838 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10766.151838 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -385,90 +543,90 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2904 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2904 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8635 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8635 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8635 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 8635 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8635 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 8635 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 74312000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 74312000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74312000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 74312000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74312000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74312000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.388387 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.388387 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.388387 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.388387 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.388387 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.388387 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8605.906196 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8605.906196 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8605.906196 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8605.906196 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8605.906196 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8605.906196 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 3347 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 3347 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9194 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9194 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9194 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 9194 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9194 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 9194 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 80596000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 80596000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 80596000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 80596000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 80596000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 80596000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.412991 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.412991 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.412991 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.412991 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.412991 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.412991 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8766.151838 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8766.151838 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8766.151838 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8766.151838 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8766.151838 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8766.151838 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1618325 # number of replacements -system.cpu.dcache.tagsinuse 511.997377 # Cycle average of tags in use -system.cpu.dcache.total_refs 20032981 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1618837 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.374922 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 43788000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997377 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11992560 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11992560 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8038236 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8038236 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20030796 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20030796 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20030796 # number of overall hits -system.cpu.dcache.overall_hits::total 20030796 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1306270 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1306270 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 314797 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 314797 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1621067 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1621067 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1621067 # number of overall misses -system.cpu.dcache.overall_misses::total 1621067 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18175237000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18175237000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8903442500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8903442500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 27078679500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 27078679500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 27078679500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 27078679500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13298830 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13298830 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8353033 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8353033 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21651863 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21651863 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21651863 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21651863 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098224 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098224 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037687 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037687 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.074870 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.074870 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074870 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074870 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13913.843999 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13913.843999 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28283.123727 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28283.123727 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16704.232151 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16704.232151 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16704.232151 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16704.232151 # average overall miss latency +system.cpu.dcache.replacements 1620900 # number of replacements +system.cpu.dcache.tagsinuse 511.997778 # Cycle average of tags in use +system.cpu.dcache.total_refs 20018689 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1621412 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.346454 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 38749000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.997778 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 11981581 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11981581 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8034926 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8034926 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20016507 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20016507 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20016507 # number of overall hits +system.cpu.dcache.overall_hits::total 20016507 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1308144 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1308144 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 315486 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 315486 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1623630 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1623630 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1623630 # number of overall misses +system.cpu.dcache.overall_misses::total 1623630 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18313652000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18313652000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8702722500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8702722500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 27016374500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 27016374500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 27016374500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 27016374500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13289725 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13289725 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8350412 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8350412 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21640137 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21640137 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21640137 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21640137 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098433 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098433 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037781 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037781 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.075029 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.075029 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.075029 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.075029 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13999.721743 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13999.721743 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27585.130560 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27585.130560 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16639.489600 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16639.489600 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16639.489600 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16639.489600 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -477,46 +635,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1535863 # number of writebacks -system.cpu.dcache.writebacks::total 1535863 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1306270 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1306270 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 314797 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 314797 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1621067 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1621067 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1621067 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1621067 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15562697000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 15562697000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8273848500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8273848500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23836545500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23836545500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23836545500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23836545500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94146954000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94146954000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2469434500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2469434500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96616388500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96616388500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098224 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098224 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037687 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037687 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074870 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.074870 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074870 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074870 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11913.843999 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11913.843999 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26283.123727 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26283.123727 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14704.232151 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14704.232151 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14704.232151 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14704.232151 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1538027 # number of writebacks +system.cpu.dcache.writebacks::total 1538027 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308144 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1308144 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315486 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 315486 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1623630 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1623630 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1623630 # 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average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 55910.061676 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12405.223881 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12405.223881 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50416.176341 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50416.176341 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 55135.430387 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51586.483802 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51882.808717 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 55135.430387 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51586.483802 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51882.808717 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -653,78 +811,78 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 80008 # number of writebacks -system.cpu.l2cache.writebacks::total 80008 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 80353 # number of writebacks +system.cpu.l2cache.writebacks::total 80353 # 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number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2305699000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2305699000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88893260000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88893260000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001770 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016282 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021630 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019525 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.811218 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.811218 # 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mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40034.785637 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40516.325519 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40365.103850 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40287.360595 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40287.360595 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40023.225322 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40023.225322 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40034.785637 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40121.630694 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40114.359722 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40034.785637 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40121.630694 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40114.359722 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12907 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 141963 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 154875 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 280010 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 544175395 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1231005255 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1775460660 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14316322 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14316322 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4249338352 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4249338352 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 280010 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 544175395 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5480343607 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6024799012 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 280010 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 544175395 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5480343607 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6024799012 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86587770000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86587770000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2305910000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2305910000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88893680000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88893680000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001623 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016308 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021749 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019607 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.805288 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.805288 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362368 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362368 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001623 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016308 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087599 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063944 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001623 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016308 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087599 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063944 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56002 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42161.260944 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43294.947948 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42942.572500 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10683.822388 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10683.822388 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37429.211239 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37429.211239 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56002 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42161.260944 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38604.027859 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38901.042854 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56002 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42161.260944 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38604.027859 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38901.042854 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt index 02670c143..812930542 100644 --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt @@ -2,44 +2,202 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.200392 # Number of seconds simulated sim_ticks 200392337000 # Number of ticks simulated -final_tick 4320161594000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +final_tick 4320161528000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 246693534 # Simulator instruction rate (inst/s) -host_op_rate 246690485 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 182041258854 # Simulator tick rate (ticks/s) -host_mem_usage 459700 # Number of bytes of host memory used -host_seconds 1.10 # Real time elapsed on the host -sim_insts 271555592 # Number of instructions simulated -sim_ops 271555592 # Number of ops (including micro ops) simulated -testsys.physmem.bytes_read::cpu.inst 13229896 # Number of bytes read from this memory -testsys.physmem.bytes_read::cpu.data 4514804 # Number of bytes read from this memory +host_inst_rate 90899186 # Simulator instruction rate (inst/s) +host_op_rate 90898450 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67078334403 # Simulator tick rate (ticks/s) +host_mem_usage 463260 # Number of bytes of host memory used +host_seconds 2.99 # Real time elapsed on the host +sim_insts 271551386 # Number of instructions simulated +sim_ops 271551386 # Number of ops (including micro ops) simulated +testsys.physmem.bytes_read::cpu.inst 13230208 # Number of bytes read from this memory +testsys.physmem.bytes_read::cpu.data 4514888 # Number of bytes read from this memory testsys.physmem.bytes_read::tsunami.ethernet 1464 # Number of bytes read from this memory -testsys.physmem.bytes_read::total 17746164 # Number of bytes read from this memory -testsys.physmem.bytes_inst_read::cpu.inst 13229896 # Number of instructions bytes read from this memory -testsys.physmem.bytes_inst_read::total 13229896 # Number of instructions bytes read from this memory -testsys.physmem.bytes_written::cpu.data 3697636 # Number of bytes written to this memory +testsys.physmem.bytes_read::total 17746560 # Number of bytes read from this memory +testsys.physmem.bytes_inst_read::cpu.inst 13230208 # Number of instructions bytes read from this memory +testsys.physmem.bytes_inst_read::total 13230208 # Number of instructions bytes read from this memory +testsys.physmem.bytes_written::cpu.data 3697656 # Number of bytes written to this memory testsys.physmem.bytes_written::tsunami.ethernet 902 # Number of bytes written to this memory -testsys.physmem.bytes_written::total 3698538 # Number of bytes written to this memory -testsys.physmem.num_reads::cpu.inst 3307474 # Number of read requests responded to by this memory -testsys.physmem.num_reads::cpu.data 615757 # Number of read requests responded to by this memory +testsys.physmem.bytes_written::total 3698558 # Number of bytes written to this memory +testsys.physmem.num_reads::cpu.inst 3307552 # Number of read requests responded to by this memory +testsys.physmem.num_reads::cpu.data 615769 # Number of read requests responded to by this memory testsys.physmem.num_reads::tsunami.ethernet 43 # Number of read requests responded to by this memory -testsys.physmem.num_reads::total 3923274 # Number of read requests responded to by this memory -testsys.physmem.num_writes::cpu.data 478509 # Number of write requests responded to by this memory +testsys.physmem.num_reads::total 3923364 # Number of read requests responded to by this memory +testsys.physmem.num_writes::cpu.data 478513 # Number of write requests responded to by this memory testsys.physmem.num_writes::tsunami.ethernet 31 # Number of write requests responded to by this memory -testsys.physmem.num_writes::total 478540 # Number of write requests responded to by this memory -testsys.physmem.bw_read::cpu.inst 66019970 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::cpu.data 22529824 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.num_writes::total 478544 # Number of write requests responded to by this memory +testsys.physmem.bw_read::cpu.inst 66021527 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::cpu.data 22530243 # Total read bandwidth from this memory (bytes/s) testsys.physmem.bw_read::tsunami.ethernet 7306 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::total 88557099 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_inst_read::cpu.inst 66019970 # Instruction read bandwidth from this memory (bytes/s) -testsys.physmem.bw_inst_read::total 66019970 # Instruction read bandwidth from this memory (bytes/s) -testsys.physmem.bw_write::cpu.data 18451983 # Write bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::total 88559075 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_inst_read::cpu.inst 66021527 # Instruction read bandwidth from this memory (bytes/s) +testsys.physmem.bw_inst_read::total 66021527 # Instruction read bandwidth from this memory (bytes/s) +testsys.physmem.bw_write::cpu.data 18452083 # Write bandwidth from this memory (bytes/s) testsys.physmem.bw_write::tsunami.ethernet 4501 # Write bandwidth from this memory (bytes/s) -testsys.physmem.bw_write::total 18456484 # Write bandwidth from this memory (bytes/s) -testsys.physmem.bw_total::cpu.inst 66019970 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::cpu.data 40981807 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_write::total 18456584 # Write bandwidth from this memory (bytes/s) +testsys.physmem.bw_total::cpu.inst 66021527 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::cpu.data 40982326 # Total bandwidth to/from this memory (bytes/s) testsys.physmem.bw_total::tsunami.ethernet 11807 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::total 107013583 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::total 107015659 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.readReqs 0 # Total number of read requests seen +testsys.physmem.writeReqs 0 # Total number of write requests seen +testsys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady +testsys.physmem.bytesRead 0 # Total number of bytes read from memory +testsys.physmem.bytesWritten 0 # Total number of bytes written to memory +testsys.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() +testsys.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +testsys.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +testsys.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +testsys.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis +testsys.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis +testsys.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis +testsys.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis +testsys.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis +testsys.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis +testsys.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis +testsys.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis +testsys.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis +testsys.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis +testsys.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis +testsys.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis +testsys.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis +testsys.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis +testsys.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis +testsys.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis +testsys.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +testsys.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +testsys.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +testsys.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +testsys.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +testsys.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +testsys.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +testsys.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +testsys.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +testsys.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +testsys.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +testsys.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +testsys.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +testsys.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +testsys.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +testsys.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +testsys.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +testsys.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +testsys.physmem.totGap 0 # Total gap between requests +testsys.physmem.readPktSize::0 0 # Categorize read packet sizes +testsys.physmem.readPktSize::1 0 # Categorize read packet sizes +testsys.physmem.readPktSize::2 0 # Categorize read packet sizes +testsys.physmem.readPktSize::3 0 # Categorize read packet sizes +testsys.physmem.readPktSize::4 0 # Categorize read packet sizes +testsys.physmem.readPktSize::5 0 # Categorize read packet sizes +testsys.physmem.readPktSize::6 0 # Categorize read packet sizes +testsys.physmem.readPktSize::7 0 # Categorize read packet sizes +testsys.physmem.readPktSize::8 0 # Categorize read packet sizes +testsys.physmem.writePktSize::0 0 # categorize write packet sizes +testsys.physmem.writePktSize::1 0 # categorize write packet sizes +testsys.physmem.writePktSize::2 0 # categorize write packet sizes +testsys.physmem.writePktSize::3 0 # categorize write packet sizes +testsys.physmem.writePktSize::4 0 # categorize write packet sizes +testsys.physmem.writePktSize::5 0 # categorize write packet sizes +testsys.physmem.writePktSize::6 0 # categorize write packet sizes +testsys.physmem.writePktSize::7 0 # categorize write packet sizes +testsys.physmem.writePktSize::8 0 # categorize write packet sizes +testsys.physmem.neitherpktsize::0 0 # categorize neither packet sizes +testsys.physmem.neitherpktsize::1 0 # categorize neither packet sizes +testsys.physmem.neitherpktsize::2 0 # categorize neither packet sizes +testsys.physmem.neitherpktsize::3 0 # categorize neither packet sizes +testsys.physmem.neitherpktsize::4 0 # categorize neither packet sizes +testsys.physmem.neitherpktsize::5 0 # categorize neither packet sizes +testsys.physmem.neitherpktsize::6 0 # categorize neither packet sizes +testsys.physmem.neitherpktsize::7 0 # categorize neither packet sizes +testsys.physmem.neitherpktsize::8 0 # categorize neither packet sizes +testsys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +testsys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +testsys.physmem.totQLat 0 # Total cycles spent in queuing delays +testsys.physmem.totMemAccLat 0 # Sum of mem lat for all requests +testsys.physmem.totBusLat 0 # Total cycles spent in databus access +testsys.physmem.totBankLat 0 # Total cycles spent in bank access +testsys.physmem.avgQLat nan # Average queueing delay per request +testsys.physmem.avgBankLat nan # Average bank access latency per request +testsys.physmem.avgBusLat nan # Average bus latency per request +testsys.physmem.avgMemAccLat nan # Average memory access latency +testsys.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s +testsys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +testsys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s +testsys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +testsys.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +testsys.physmem.busUtil 0.00 # Data bus utilization in percentage +testsys.physmem.avgRdQLen 0.00 # Average read queue length over time +testsys.physmem.avgWrQLen 0.00 # Average write queue length over time +testsys.physmem.readRowHits 0 # Number of row buffer hits during reads +testsys.physmem.writeRowHits 0 # Number of row buffer hits during writes +testsys.physmem.readRowHitRate nan # Row buffer hit rate for reads +testsys.physmem.writeRowHitRate nan # Row buffer hit rate for writes +testsys.physmem.avgGap nan # Average gap between requests testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -56,22 +214,22 @@ testsys.cpu.dtb.fetch_hits 0 # IT testsys.cpu.dtb.fetch_misses 0 # ITB misses testsys.cpu.dtb.fetch_acv 0 # ITB acv testsys.cpu.dtb.fetch_accesses 0 # ITB accesses -testsys.cpu.dtb.read_hits 611875 # DTB read hits +testsys.cpu.dtb.read_hits 611887 # DTB read hits testsys.cpu.dtb.read_misses 3287 # DTB read misses testsys.cpu.dtb.read_acv 80 # DTB read access violations testsys.cpu.dtb.read_accesses 225414 # DTB read accesses -testsys.cpu.dtb.write_hits 478325 # DTB write hits +testsys.cpu.dtb.write_hits 478329 # DTB write hits testsys.cpu.dtb.write_misses 528 # DTB write misses testsys.cpu.dtb.write_acv 81 # DTB write access violations testsys.cpu.dtb.write_accesses 109988 # DTB write accesses -testsys.cpu.dtb.data_hits 1090200 # DTB hits +testsys.cpu.dtb.data_hits 1090216 # DTB hits testsys.cpu.dtb.data_misses 3815 # DTB misses testsys.cpu.dtb.data_acv 161 # DTB access violations testsys.cpu.dtb.data_accesses 335402 # DTB accesses -testsys.cpu.itb.fetch_hits 1215641 # ITB hits +testsys.cpu.itb.fetch_hits 1215659 # ITB hits testsys.cpu.itb.fetch_misses 1497 # ITB misses testsys.cpu.itb.fetch_acv 69 # ITB acv -testsys.cpu.itb.fetch_accesses 1217138 # ITB accesses +testsys.cpu.itb.fetch_accesses 1217156 # ITB accesses testsys.cpu.itb.read_hits 0 # DTB read hits testsys.cpu.itb.read_misses 0 # DTB read misses testsys.cpu.itb.read_acv 0 # DTB read access violations @@ -84,51 +242,51 @@ testsys.cpu.itb.data_hits 0 # DT testsys.cpu.itb.data_misses 0 # DTB misses testsys.cpu.itb.data_acv 0 # DTB access violations testsys.cpu.itb.data_accesses 0 # DTB accesses -testsys.cpu.numCycles 399134827 # number of cpu cycles simulated +testsys.cpu.numCycles 399134959 # number of cpu cycles simulated testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -testsys.cpu.committedInsts 3303498 # Number of instructions committed -testsys.cpu.committedOps 3303498 # Number of ops (including micro ops) committed -testsys.cpu.num_int_alu_accesses 3114409 # Number of integer alu accesses +testsys.cpu.committedInsts 3303576 # Number of instructions committed +testsys.cpu.committedOps 3303576 # Number of ops (including micro ops) committed +testsys.cpu.num_int_alu_accesses 3114478 # Number of integer alu accesses testsys.cpu.num_fp_alu_accesses 17380 # Number of float alu accesses -testsys.cpu.num_func_calls 87506 # number of times a function call or return occured -testsys.cpu.num_conditional_control_insts 347031 # number of instructions that are conditional controls -testsys.cpu.num_int_insts 3114409 # number of integer instructions +testsys.cpu.num_func_calls 87508 # number of times a function call or return occured +testsys.cpu.num_conditional_control_insts 347037 # number of instructions that are conditional controls +testsys.cpu.num_int_insts 3114478 # number of integer instructions testsys.cpu.num_fp_insts 17380 # number of float instructions -testsys.cpu.num_int_register_reads 4292439 # number of times the integer registers were read -testsys.cpu.num_int_register_writes 2256595 # number of times the integer registers were written +testsys.cpu.num_int_register_reads 4292532 # number of times the integer registers were read +testsys.cpu.num_int_register_writes 2256656 # number of times the integer registers were written testsys.cpu.num_fp_register_reads 11166 # number of times the floating registers were read testsys.cpu.num_fp_register_writes 10823 # number of times the floating registers were written -testsys.cpu.num_mem_refs 1099884 # number of memory refs -testsys.cpu.num_load_insts 619431 # Number of load instructions -testsys.cpu.num_store_insts 480453 # Number of store instructions -testsys.cpu.num_idle_cycles 395839404.829048 # Number of idle cycles -testsys.cpu.num_busy_cycles 3295422.170952 # Number of busy cycles -testsys.cpu.not_idle_fraction 0.008256 # Percentage of non-idle cycles -testsys.cpu.idle_fraction 0.991744 # Percentage of idle cycles +testsys.cpu.num_mem_refs 1099900 # number of memory refs +testsys.cpu.num_load_insts 619443 # Number of load instructions +testsys.cpu.num_store_insts 480457 # Number of store instructions +testsys.cpu.num_idle_cycles 395839458.060266 # Number of idle cycles +testsys.cpu.num_busy_cycles 3295500.939734 # Number of busy cycles +testsys.cpu.not_idle_fraction 0.008257 # Percentage of non-idle cycles +testsys.cpu.idle_fraction 0.991743 # Percentage of idle cycles testsys.cpu.kern.inst.arm 0 # number of arm instructions executed testsys.cpu.kern.inst.quiesce 213 # number of quiesce instructions executed -testsys.cpu.kern.inst.hwrei 16709 # number of hwrei instructions executed -testsys.cpu.kern.ipl_count::0 4122 40.57% 40.57% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::21 54 0.53% 41.10% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::22 205 2.02% 43.12% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::31 5779 56.88% 100.00% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::total 10160 # number of times we switched to this ipl +testsys.cpu.kern.inst.hwrei 16711 # number of hwrei instructions executed +testsys.cpu.kern.ipl_count::0 4122 40.56% 40.56% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::21 54 0.53% 41.09% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::22 205 2.02% 43.11% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::31 5781 56.89% 100.00% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::total 10162 # number of times we switched to this ipl testsys.cpu.kern.ipl_good::0 4116 48.47% 48.47% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good::21 54 0.64% 49.11% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good::22 205 2.41% 51.53% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good::31 4116 48.47% 100.00% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good::total 8491 # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_ticks::0 199321085500 99.88% 99.88% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::0 199321108000 99.88% 99.88% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_ticks::21 4521000 0.00% 99.88% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_ticks::22 8815000 0.00% 99.88% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::31 233213000 0.12% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::total 199567634500 # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::31 233256500 0.12% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::total 199567700500 # number of cycles we spent at this ipl testsys.cpu.kern.ipl_used::0 0.998544 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used::31 0.712234 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used::total 0.835728 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used::31 0.711988 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used::total 0.835564 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.syscall::2 3 3.61% 3.61% # number of syscalls executed testsys.cpu.kern.syscall::3 7 8.43% 12.05% # number of syscalls executed testsys.cpu.kern.syscall::4 1 1.20% 13.25% # number of syscalls executed @@ -151,16 +309,16 @@ testsys.cpu.kern.syscall::104 1 1.20% 93.98% # nu testsys.cpu.kern.syscall::105 3 3.61% 97.59% # number of syscalls executed testsys.cpu.kern.syscall::118 2 2.41% 100.00% # number of syscalls executed testsys.cpu.kern.syscall::total 83 # number of syscalls executed -testsys.cpu.kern.callpal::swpctx 438 4.02% 4.02% # number of callpals executed +testsys.cpu.kern.callpal::swpctx 438 4.01% 4.01% # number of callpals executed testsys.cpu.kern.callpal::tbi 20 0.18% 4.20% # number of callpals executed -testsys.cpu.kern.callpal::swpipl 8990 82.42% 86.62% # number of callpals executed +testsys.cpu.kern.callpal::swpipl 8992 82.42% 86.62% # number of callpals executed testsys.cpu.kern.callpal::rdps 359 3.29% 89.91% # number of callpals executed -testsys.cpu.kern.callpal::wrusp 3 0.03% 89.93% # number of callpals executed +testsys.cpu.kern.callpal::wrusp 3 0.03% 89.94% # number of callpals executed testsys.cpu.kern.callpal::rdusp 3 0.03% 89.96% # number of callpals executed testsys.cpu.kern.callpal::rti 911 8.35% 98.31% # number of callpals executed testsys.cpu.kern.callpal::callsys 140 1.28% 99.60% # number of callpals executed testsys.cpu.kern.callpal::imb 44 0.40% 100.00% # number of callpals executed -testsys.cpu.kern.callpal::total 10908 # number of callpals executed +testsys.cpu.kern.callpal::total 10910 # number of callpals executed testsys.cpu.kern.mode_switch::kernel 1133 # number of protection mode switches testsys.cpu.kern.mode_switch::user 647 # number of protection mode switches testsys.cpu.kern.mode_switch::idle 217 # number of protection mode switches @@ -171,9 +329,9 @@ testsys.cpu.kern.mode_switch_good::kernel 0.575463 # f testsys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches testsys.cpu.kern.mode_switch_good::idle 0.023041 # fraction of useful protection mode switches testsys.cpu.kern.mode_switch_good::total 0.652979 # fraction of useful protection mode switches -testsys.cpu.kern.mode_ticks::kernel 931595000 57.07% 57.07% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks::user 532793000 32.64% 89.71% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks::idle 168009000 10.29% 100.00% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks::kernel 931596000 57.08% 57.08% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks::user 532793000 32.64% 89.72% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks::idle 167721000 10.28% 100.00% # number of ticks spent at the given mode testsys.cpu.kern.swap_context 438 # number of times the context was actually changed testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted testsys.tsunami.ethernet.rxBytes 798 # Bytes Received @@ -253,6 +411,164 @@ drivesys.physmem.bw_total::cpu.inst 39070237 # To drivesys.physmem.bw_total::cpu.data 21904410 # Total bandwidth to/from this memory (bytes/s) drivesys.physmem.bw_total::tsunami.ethernet 11448 # Total bandwidth to/from this memory (bytes/s) drivesys.physmem.bw_total::total 60986094 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.readReqs 0 # Total number of read requests seen +drivesys.physmem.writeReqs 0 # Total number of write requests seen +drivesys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady +drivesys.physmem.bytesRead 0 # Total number of bytes read from memory +drivesys.physmem.bytesWritten 0 # Total number of bytes written to memory +drivesys.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() +drivesys.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +drivesys.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +drivesys.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +drivesys.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis +drivesys.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis +drivesys.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis +drivesys.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis +drivesys.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis +drivesys.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis +drivesys.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis +drivesys.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis +drivesys.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis +drivesys.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis +drivesys.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis +drivesys.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis +drivesys.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis +drivesys.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis +drivesys.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis +drivesys.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis +drivesys.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +drivesys.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +drivesys.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +drivesys.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +drivesys.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +drivesys.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +drivesys.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +drivesys.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +drivesys.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +drivesys.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +drivesys.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +drivesys.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +drivesys.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +drivesys.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +drivesys.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +drivesys.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +drivesys.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +drivesys.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +drivesys.physmem.totGap 0 # Total gap between requests +drivesys.physmem.readPktSize::0 0 # Categorize read packet sizes +drivesys.physmem.readPktSize::1 0 # Categorize read packet sizes +drivesys.physmem.readPktSize::2 0 # Categorize read packet sizes +drivesys.physmem.readPktSize::3 0 # Categorize read packet sizes +drivesys.physmem.readPktSize::4 0 # Categorize read packet sizes +drivesys.physmem.readPktSize::5 0 # Categorize read packet sizes +drivesys.physmem.readPktSize::6 0 # Categorize read packet sizes +drivesys.physmem.readPktSize::7 0 # Categorize read packet sizes +drivesys.physmem.readPktSize::8 0 # Categorize read packet sizes +drivesys.physmem.writePktSize::0 0 # categorize write packet sizes +drivesys.physmem.writePktSize::1 0 # categorize write packet sizes +drivesys.physmem.writePktSize::2 0 # categorize write packet sizes +drivesys.physmem.writePktSize::3 0 # categorize write packet sizes +drivesys.physmem.writePktSize::4 0 # categorize write packet sizes +drivesys.physmem.writePktSize::5 0 # categorize write packet sizes +drivesys.physmem.writePktSize::6 0 # categorize write packet sizes +drivesys.physmem.writePktSize::7 0 # categorize write packet sizes +drivesys.physmem.writePktSize::8 0 # categorize write packet sizes +drivesys.physmem.neitherpktsize::0 0 # categorize neither packet sizes +drivesys.physmem.neitherpktsize::1 0 # categorize neither packet sizes +drivesys.physmem.neitherpktsize::2 0 # categorize neither packet sizes +drivesys.physmem.neitherpktsize::3 0 # categorize neither packet sizes +drivesys.physmem.neitherpktsize::4 0 # categorize neither packet sizes +drivesys.physmem.neitherpktsize::5 0 # categorize neither packet sizes +drivesys.physmem.neitherpktsize::6 0 # categorize neither packet sizes +drivesys.physmem.neitherpktsize::7 0 # categorize neither packet sizes +drivesys.physmem.neitherpktsize::8 0 # categorize neither packet sizes +drivesys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +drivesys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +drivesys.physmem.totQLat 0 # Total cycles spent in queuing delays +drivesys.physmem.totMemAccLat 0 # Sum of mem lat for all requests +drivesys.physmem.totBusLat 0 # Total cycles spent in databus access +drivesys.physmem.totBankLat 0 # Total cycles spent in bank access +drivesys.physmem.avgQLat nan # Average queueing delay per request +drivesys.physmem.avgBankLat nan # Average bank access latency per request +drivesys.physmem.avgBusLat nan # Average bus latency per request +drivesys.physmem.avgMemAccLat nan # Average memory access latency +drivesys.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s +drivesys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +drivesys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s +drivesys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +drivesys.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +drivesys.physmem.busUtil 0.00 # Data bus utilization in percentage +drivesys.physmem.avgRdQLen 0.00 # Average read queue length over time +drivesys.physmem.avgWrQLen 0.00 # Average write queue length over time +drivesys.physmem.readRowHits 0 # Number of row buffer hits during reads +drivesys.physmem.writeRowHits 0 # Number of row buffer hits during writes +drivesys.physmem.readRowHitRate nan # Row buffer hit rate for reads +drivesys.physmem.writeRowHitRate nan # Row buffer hit rate for writes +drivesys.physmem.avgGap nan # Average gap between requests drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -376,7 +692,7 @@ drivesys.cpu.kern.mode_switch_good::idle 0.018265 # fr drivesys.cpu.kern.mode_switch_good::total 0.441352 # fraction of useful protection mode switches drivesys.cpu.kern.mode_ticks::kernel 66889000 2.31% 2.31% # number of ticks spent at the given mode drivesys.cpu.kern.mode_ticks::user 319585750 11.03% 13.34% # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks::idle 2511439250 86.66% 100.00% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks::idle 2511080250 86.66% 100.00% # number of ticks spent at the given mode drivesys.cpu.kern.swap_context 72 # number of times the context was actually changed drivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted drivesys.tsunami.ethernet.rxBytes 960 # Bytes Received @@ -433,15 +749,15 @@ drivesys.tsunami.ethernet.droppedPackets 0 # nu ---------- Begin Simulation Statistics ---------- sim_seconds 0.000390 # Number of seconds simulated sim_ticks 390393500 # Number of ticks simulated -final_tick 4320551987500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +final_tick 4320551921500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 309018358448 # Simulator instruction rate (inst/s) -host_op_rate 304755215914 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 428792748186 # Simulator tick rate (ticks/s) -host_mem_usage 459700 # Number of bytes of host memory used +host_inst_rate 123937139701 # Simulator instruction rate (inst/s) +host_op_rate 122659857960 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 174562814371 # Simulator tick rate (ticks/s) +host_mem_usage 463260 # Number of bytes of host memory used host_seconds 0.00 # Real time elapsed on the host -sim_insts 271558535 # Number of instructions simulated -sim_ops 271558535 # Number of ops (including micro ops) simulated +sim_insts 271554329 # Number of instructions simulated +sim_ops 271554329 # Number of ops (including micro ops) simulated testsys.physmem.bytes_read::cpu.inst 5888 # Number of bytes read from this memory testsys.physmem.bytes_read::cpu.data 2272 # Number of bytes read from this memory testsys.physmem.bytes_read::total 8160 # Number of bytes read from this memory @@ -464,6 +780,164 @@ testsys.physmem.bw_write::total 3299235 # Wr testsys.physmem.bw_total::cpu.inst 15082218 # Total bandwidth to/from this memory (bytes/s) testsys.physmem.bw_total::cpu.data 9119004 # Total bandwidth to/from this memory (bytes/s) testsys.physmem.bw_total::total 24201223 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.readReqs 0 # Total number of read requests seen +testsys.physmem.writeReqs 0 # Total number of write requests seen +testsys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady +testsys.physmem.bytesRead 0 # Total number of bytes read from memory +testsys.physmem.bytesWritten 0 # Total number of bytes written to memory +testsys.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() +testsys.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +testsys.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +testsys.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +testsys.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis +testsys.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis +testsys.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis +testsys.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis +testsys.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis +testsys.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis +testsys.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis +testsys.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis +testsys.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis +testsys.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis +testsys.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis +testsys.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis +testsys.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis +testsys.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis +testsys.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis +testsys.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis +testsys.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +testsys.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +testsys.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +testsys.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +testsys.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +testsys.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +testsys.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +testsys.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +testsys.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +testsys.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +testsys.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +testsys.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +testsys.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +testsys.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +testsys.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +testsys.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +testsys.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +testsys.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +testsys.physmem.totGap 0 # Total gap between requests +testsys.physmem.readPktSize::0 0 # Categorize read packet sizes +testsys.physmem.readPktSize::1 0 # Categorize read packet sizes +testsys.physmem.readPktSize::2 0 # Categorize read packet sizes +testsys.physmem.readPktSize::3 0 # Categorize read packet sizes +testsys.physmem.readPktSize::4 0 # Categorize read packet sizes +testsys.physmem.readPktSize::5 0 # Categorize read packet sizes +testsys.physmem.readPktSize::6 0 # Categorize read packet sizes +testsys.physmem.readPktSize::7 0 # Categorize read packet sizes +testsys.physmem.readPktSize::8 0 # Categorize read packet sizes +testsys.physmem.writePktSize::0 0 # categorize write packet sizes +testsys.physmem.writePktSize::1 0 # categorize write packet sizes +testsys.physmem.writePktSize::2 0 # categorize write packet sizes +testsys.physmem.writePktSize::3 0 # categorize write packet sizes +testsys.physmem.writePktSize::4 0 # categorize write packet sizes +testsys.physmem.writePktSize::5 0 # categorize write packet sizes +testsys.physmem.writePktSize::6 0 # categorize write packet sizes +testsys.physmem.writePktSize::7 0 # categorize write packet sizes +testsys.physmem.writePktSize::8 0 # categorize write packet sizes +testsys.physmem.neitherpktsize::0 0 # categorize neither packet sizes +testsys.physmem.neitherpktsize::1 0 # categorize neither packet sizes +testsys.physmem.neitherpktsize::2 0 # categorize neither packet sizes +testsys.physmem.neitherpktsize::3 0 # categorize neither packet sizes +testsys.physmem.neitherpktsize::4 0 # categorize neither packet sizes +testsys.physmem.neitherpktsize::5 0 # categorize neither packet sizes +testsys.physmem.neitherpktsize::6 0 # categorize neither packet sizes +testsys.physmem.neitherpktsize::7 0 # categorize neither packet sizes +testsys.physmem.neitherpktsize::8 0 # categorize neither packet sizes +testsys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +testsys.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +testsys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +testsys.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +testsys.physmem.totQLat 0 # Total cycles spent in queuing delays +testsys.physmem.totMemAccLat 0 # Sum of mem lat for all requests +testsys.physmem.totBusLat 0 # Total cycles spent in databus access +testsys.physmem.totBankLat 0 # Total cycles spent in bank access +testsys.physmem.avgQLat nan # Average queueing delay per request +testsys.physmem.avgBankLat nan # Average bank access latency per request +testsys.physmem.avgBusLat nan # Average bus latency per request +testsys.physmem.avgMemAccLat nan # Average memory access latency +testsys.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s +testsys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +testsys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s +testsys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +testsys.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +testsys.physmem.busUtil 0.00 # Data bus utilization in percentage +testsys.physmem.avgRdQLen 0.00 # Average read queue length over time +testsys.physmem.avgWrQLen 0.00 # Average write queue length over time +testsys.physmem.readRowHits 0 # Number of row buffer hits during reads +testsys.physmem.writeRowHits 0 # Number of row buffer hits during writes +testsys.physmem.readRowHitRate nan # Row buffer hit rate for reads +testsys.physmem.writeRowHitRate nan # Row buffer hit rate for writes +testsys.physmem.avgGap nan # Average gap between requests testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -620,6 +1094,164 @@ drivesys.physmem.bw_write::total 3299235 # Wr drivesys.physmem.bw_total::cpu.inst 15071972 # Total bandwidth to/from this memory (bytes/s) drivesys.physmem.bw_total::cpu.data 9119004 # Total bandwidth to/from this memory (bytes/s) drivesys.physmem.bw_total::total 24190977 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.readReqs 0 # Total number of read requests seen +drivesys.physmem.writeReqs 0 # Total number of write requests seen +drivesys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady +drivesys.physmem.bytesRead 0 # Total number of bytes read from memory +drivesys.physmem.bytesWritten 0 # Total number of bytes written to memory +drivesys.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() +drivesys.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +drivesys.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +drivesys.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +drivesys.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis +drivesys.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis +drivesys.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis +drivesys.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis +drivesys.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis +drivesys.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis +drivesys.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis +drivesys.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis +drivesys.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis +drivesys.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis +drivesys.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis +drivesys.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis +drivesys.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis +drivesys.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis +drivesys.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis +drivesys.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis +drivesys.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +drivesys.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +drivesys.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +drivesys.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +drivesys.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +drivesys.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +drivesys.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +drivesys.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +drivesys.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +drivesys.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +drivesys.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +drivesys.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +drivesys.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +drivesys.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +drivesys.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +drivesys.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +drivesys.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +drivesys.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +drivesys.physmem.totGap 0 # Total gap between requests +drivesys.physmem.readPktSize::0 0 # Categorize read packet sizes +drivesys.physmem.readPktSize::1 0 # Categorize read packet sizes +drivesys.physmem.readPktSize::2 0 # Categorize read packet sizes +drivesys.physmem.readPktSize::3 0 # Categorize read packet sizes +drivesys.physmem.readPktSize::4 0 # Categorize read packet sizes +drivesys.physmem.readPktSize::5 0 # Categorize read packet sizes +drivesys.physmem.readPktSize::6 0 # Categorize read packet sizes +drivesys.physmem.readPktSize::7 0 # Categorize read packet sizes +drivesys.physmem.readPktSize::8 0 # Categorize read packet sizes +drivesys.physmem.writePktSize::0 0 # categorize write packet sizes +drivesys.physmem.writePktSize::1 0 # categorize write packet sizes +drivesys.physmem.writePktSize::2 0 # categorize write packet sizes +drivesys.physmem.writePktSize::3 0 # categorize write packet sizes +drivesys.physmem.writePktSize::4 0 # categorize write packet sizes +drivesys.physmem.writePktSize::5 0 # categorize write packet sizes +drivesys.physmem.writePktSize::6 0 # categorize write packet sizes +drivesys.physmem.writePktSize::7 0 # categorize write packet sizes +drivesys.physmem.writePktSize::8 0 # categorize write packet sizes +drivesys.physmem.neitherpktsize::0 0 # categorize neither packet sizes +drivesys.physmem.neitherpktsize::1 0 # categorize neither packet sizes +drivesys.physmem.neitherpktsize::2 0 # categorize neither packet sizes +drivesys.physmem.neitherpktsize::3 0 # categorize neither packet sizes +drivesys.physmem.neitherpktsize::4 0 # categorize neither packet sizes +drivesys.physmem.neitherpktsize::5 0 # categorize neither packet sizes +drivesys.physmem.neitherpktsize::6 0 # categorize neither packet sizes +drivesys.physmem.neitherpktsize::7 0 # categorize neither packet sizes +drivesys.physmem.neitherpktsize::8 0 # categorize neither packet sizes +drivesys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +drivesys.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +drivesys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +drivesys.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +drivesys.physmem.totQLat 0 # Total cycles spent in queuing delays +drivesys.physmem.totMemAccLat 0 # Sum of mem lat for all requests +drivesys.physmem.totBusLat 0 # Total cycles spent in databus access +drivesys.physmem.totBankLat 0 # Total cycles spent in bank access +drivesys.physmem.avgQLat nan # Average queueing delay per request +drivesys.physmem.avgBankLat nan # Average bank access latency per request +drivesys.physmem.avgBusLat nan # Average bus latency per request +drivesys.physmem.avgMemAccLat nan # Average memory access latency +drivesys.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s +drivesys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +drivesys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s +drivesys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +drivesys.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +drivesys.physmem.busUtil 0.00 # Data bus utilization in percentage +drivesys.physmem.avgRdQLen 0.00 # Average read queue length over time +drivesys.physmem.avgWrQLen 0.00 # Average write queue length over time +drivesys.physmem.readRowHits 0 # Number of row buffer hits during reads +drivesys.physmem.writeRowHits 0 # Number of row buffer hits during writes +drivesys.physmem.readRowHitRate nan # Row buffer hit rate for reads +drivesys.physmem.writeRowHitRate nan # Row buffer hit rate for writes +drivesys.physmem.avgGap nan # Average gap between requests drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index 062194e2a..ecf052997 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,32 +1,190 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 21628500 # Number of ticks simulated -final_tick 21628500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000020 # Number of seconds simulated +sim_ticks 19841500 # Number of ticks simulated +final_tick 19841500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 34038 # Simulator instruction rate (inst/s) -host_op_rate 34033 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 115179622 # Simulator tick rate (ticks/s) -host_mem_usage 212112 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 31060 # Simulator instruction rate (inst/s) +host_op_rate 31057 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 96425663 # Simulator tick rate (ticks/s) +host_mem_usage 216044 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory -system.physmem.bytes_read::total 30016 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 19264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 19264 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 29952 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19200 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 300 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory -system.physmem.num_reads::total 469 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 890676653 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 497121853 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1387798507 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 890676653 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 890676653 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 890676653 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 497121853 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1387798507 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 468 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 967668775 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 541894514 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1509563289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 967668775 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 967668775 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 967668775 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 541894514 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1509563289 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 469 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 469 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 29952 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 29952 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 50 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 4 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 25 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 21 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 3 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 69 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 23 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 33 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 72 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 66 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 45 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 2 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 7 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 19827000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 469 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 334 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 1719468 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11463468 # Sum of mem lat for all requests +system.physmem.totBusLat 1876000 # Total cycles spent in databus access +system.physmem.totBankLat 7868000 # Total cycles spent in bank access +system.physmem.avgQLat 3666.24 # Average queueing delay per request +system.physmem.avgBankLat 16776.12 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 24442.36 # Average memory access latency +system.physmem.avgRdBW 1509.56 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 1509.56 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 9.43 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.58 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 401 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.50 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 42275.05 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -60,7 +218,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 43258 # number of cpu cycles simulated +system.cpu.numCycles 39684 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.lookups 1606 # Number of BP lookups @@ -90,12 +248,12 @@ system.cpu.execution_unit.executions 4463 # Nu system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 11927 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 11913 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 526 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35855 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 7403 # Number of cycles cpu stages are processed. -system.cpu.activity 17.113597 # Percentage of cycles cpu is active +system.cpu.timesIdled 522 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 32282 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 7402 # Number of cycles cpu stages are processed. +system.cpu.activity 18.652354 # Percentage of cycles cpu is active system.cpu.comLoads 1183 # Number of Load instructions committed system.cpu.comStores 865 # Number of Store instructions committed system.cpu.comBranches 1050 # Number of Branches instructions committed @@ -107,72 +265,72 @@ system.cpu.committedInsts 6390 # Nu system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total) -system.cpu.cpi 6.769640 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.210329 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.769640 # CPI: Total CPI of All Threads -system.cpu.ipc 0.147718 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.210329 # CPI: Total CPI of All Threads +system.cpu.ipc 0.161022 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.147718 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 38346 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.161022 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 34772 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 4912 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 11.355125 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 39380 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 12.377784 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 35806 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 3878 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 8.964816 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 39087 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 4171 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 9.642147 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 41918 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 9.772200 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 35512 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 4172 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 10.513053 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 38344 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1340 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.097693 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 38800 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 3.376676 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 35226 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 4458 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 10.305608 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 11.233747 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 138.677886 # Cycle average of tags in use -system.cpu.icache.total_refs 557 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 142.150123 # Cycle average of tags in use +system.cpu.icache.total_refs 558 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.850498 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1.853821 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 138.677886 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.067714 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.067714 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 557 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 557 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 557 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 557 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 557 # number of overall hits -system.cpu.icache.overall_hits::total 557 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 351 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 351 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 351 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 351 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 351 # number of overall misses -system.cpu.icache.overall_misses::total 351 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19444500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19444500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19444500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19444500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19444500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19444500 # number of overall miss cycles +system.cpu.icache.occ_blocks::cpu.inst 142.150123 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.069409 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.069409 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 558 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 558 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 558 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 558 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 558 # number of overall hits +system.cpu.icache.overall_hits::total 558 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 350 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses +system.cpu.icache.overall_misses::total 350 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17305000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17305000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17305000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17305000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17305000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17305000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 908 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 908 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 908 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 908 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 908 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.386564 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.386564 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.386564 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.386564 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.386564 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.386564 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55397.435897 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55397.435897 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55397.435897 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55397.435897 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55397.435897 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55397.435897 # average overall miss latency +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.385463 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.385463 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.385463 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.385463 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.385463 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.385463 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49442.857143 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49442.857143 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49442.857143 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49442.857143 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49442.857143 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49442.857143 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -181,46 +339,46 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 49 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 49 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 49 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 49 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 49 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 48 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 48 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 48 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 48 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16495000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16495000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16495000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16495000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16495000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16495000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14791500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14791500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14791500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14791500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14791500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14791500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.332599 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.332599 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.332599 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54619.205298 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54619.205298 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54619.205298 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54619.205298 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54619.205298 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54619.205298 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48978.476821 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48978.476821 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48978.476821 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 48978.476821 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48978.476821 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 48978.476821 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 102.512660 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 104.047429 # Cycle average of tags in use system.cpu.dcache.total_refs 1700 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 10.119048 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 102.512660 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025028 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025028 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 104.047429 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025402 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025402 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 614 # number of WriteReq hits @@ -237,14 +395,14 @@ system.cpu.dcache.demand_misses::cpu.data 348 # n system.cpu.dcache.demand_misses::total 348 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 348 # number of overall misses system.cpu.dcache.overall_misses::total 348 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5810500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5810500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 13883000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 13883000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19693500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19693500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19693500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19693500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5354000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5354000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11296500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11296500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16650500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16650500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16650500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16650500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -261,20 +419,20 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.169922 system.cpu.dcache.demand_miss_rate::total 0.169922 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.169922 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.169922 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59902.061856 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59902.061856 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55310.756972 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55310.756972 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56590.517241 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56590.517241 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56590.517241 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56590.517241 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55195.876289 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55195.876289 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45005.976096 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45005.976096 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47846.264368 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47846.264368 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47846.264368 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47846.264368 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3380 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2586 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 37 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 91.351351 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 69.891892 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits @@ -293,14 +451,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5512000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5512000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4096500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4096500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9608500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9608500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9608500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9608500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5078500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5078500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3447000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3447000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8525500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8525500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8525500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8525500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -309,26 +467,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58021.052632 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58021.052632 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56116.438356 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56116.438356 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57193.452381 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 57193.452381 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57193.452381 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 57193.452381 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53457.894737 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53457.894737 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47219.178082 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47219.178082 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50747.023810 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 50747.023810 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50747.023810 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 50747.023810 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 194.915514 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 199.193487 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 138.751655 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.163860 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004234 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001714 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005948 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 142.245680 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.947807 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004341 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001738 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006079 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -346,17 +504,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16176500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5410500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21587000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4019000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4019000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16176500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9429500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 25606000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16176500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9429500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 25606000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14473000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4977000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19450000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3369500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3369500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14473000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8346500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22819500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14473000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8346500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22819500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -379,17 +537,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53742.524917 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56952.631579 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 54512.626263 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55054.794521 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55054.794521 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53742.524917 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56127.976190 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 54597.014925 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53742.524917 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56127.976190 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 54597.014925 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48083.056478 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52389.473684 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 49116.161616 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46157.534247 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46157.534247 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48083.056478 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 49681.547619 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 48655.650320 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48083.056478 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 49681.547619 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 48655.650320 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -409,17 +567,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469 system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12511500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4259000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16770500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3141000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3141000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12511500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7400000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19911500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12511500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7400000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19911500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10688499 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3791620 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14480119 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2447596 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2447596 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10688499 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6239216 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16927715 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10688499 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6239216 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16927715 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses @@ -431,17 +589,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41566.445183 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44831.578947 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42349.747475 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43027.397260 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43027.397260 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41566.445183 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44047.619048 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42455.223881 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41566.445183 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44047.619048 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42455.223881 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35509.963455 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39911.789474 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36565.957071 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33528.712329 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33528.712329 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35509.963455 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37138.190476 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36093.208955 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35509.963455 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37138.190476 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36093.208955 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 1c9a49b18..d5736f11f 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,52 +1,210 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12394500 # Number of ticks simulated -final_tick 12394500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 11568000 # Number of ticks simulated +final_tick 11568000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 52290 # Simulator instruction rate (inst/s) -host_op_rate 52282 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 101684511 # Simulator tick rate (ticks/s) -host_mem_usage 219660 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 27765 # Simulator instruction rate (inst/s) +host_op_rate 27764 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50400871 # Simulator tick rate (ticks/s) +host_mem_usage 217072 # Number of bytes of host memory used +host_seconds 0.23 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 11328 # Number of bytes read from this memory -system.physmem.bytes_read::total 31296 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 177 # Number of read requests responded to by this memory -system.physmem.num_reads::total 489 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1611037154 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 913953770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2524990923 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1611037154 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1611037154 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1611037154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 913953770 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2524990923 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory +system.physmem.bytes_read::total 31104 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory +system.physmem.num_reads::total 486 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1731673582 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 957123098 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2688796680 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1731673582 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1731673582 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1731673582 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 957123098 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2688796680 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 486 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 486 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 31104 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 31104 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 51 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 19 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 4 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 30 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 31 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 25 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 4 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 67 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 33 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 72 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 67 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 44 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 2 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 7 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 11441000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 486 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 243 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 145 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 70 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 3089486 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12593486 # Sum of mem lat for all requests +system.physmem.totBusLat 1944000 # Total cycles spent in databus access +system.physmem.totBankLat 7560000 # Total cycles spent in bank access +system.physmem.avgQLat 6356.97 # Average queueing delay per request +system.physmem.avgBankLat 15555.56 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 25912.52 # Average memory access latency +system.physmem.avgRdBW 2688.80 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 2688.80 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 16.80 # Data bus utilization in percentage +system.physmem.avgRdQLen 1.09 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 416 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.60 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 23541.15 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1990 # DTB read hits -system.cpu.dtb.read_misses 56 # DTB read misses +system.cpu.dtb.read_hits 1960 # DTB read hits +system.cpu.dtb.read_misses 58 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2046 # DTB read accesses -system.cpu.dtb.write_hits 1084 # DTB write hits -system.cpu.dtb.write_misses 30 # DTB write misses +system.cpu.dtb.read_accesses 2018 # DTB read accesses +system.cpu.dtb.write_hits 1076 # DTB write hits +system.cpu.dtb.write_misses 32 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1114 # DTB write accesses -system.cpu.dtb.data_hits 3074 # DTB hits -system.cpu.dtb.data_misses 86 # DTB misses +system.cpu.dtb.write_accesses 1108 # DTB write accesses +system.cpu.dtb.data_hits 3036 # DTB hits +system.cpu.dtb.data_misses 90 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3160 # DTB accesses -system.cpu.itb.fetch_hits 2336 # ITB hits +system.cpu.dtb.data_accesses 3126 # DTB accesses +system.cpu.itb.fetch_hits 2261 # ITB hits system.cpu.itb.fetch_misses 38 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2374 # ITB accesses +system.cpu.itb.fetch_accesses 2299 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,244 +218,244 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 24790 # number of cpu cycles simulated +system.cpu.numCycles 23137 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2873 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1665 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 545 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2164 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 779 # Number of BTB hits +system.cpu.BPredUnit.lookups 2774 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1638 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 514 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2124 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 769 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 421 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 78 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 8141 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16442 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2873 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1200 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2939 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1838 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 885 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 405 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 66 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 7948 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 15915 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2774 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1174 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2854 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1765 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 730 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 739 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2336 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 367 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13982 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.175940 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.562615 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 746 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2261 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 327 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13513 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.177755 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.562670 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11043 78.98% 78.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 296 2.12% 81.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 231 1.65% 82.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 234 1.67% 84.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 276 1.97% 86.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 200 1.43% 87.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 274 1.96% 89.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 190 1.36% 91.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1238 8.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10659 78.88% 78.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 293 2.17% 81.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 218 1.61% 82.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 238 1.76% 84.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 276 2.04% 86.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 191 1.41% 87.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 258 1.91% 89.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 175 1.30% 91.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1205 8.92% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13982 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.115894 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.663251 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9096 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 904 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2739 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 72 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1171 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 257 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 89 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 15180 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 236 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1171 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9315 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 259 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 364 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2589 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 284 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14415 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 8 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 250 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10802 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18056 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18039 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 13513 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.119895 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.687859 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8886 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 751 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2667 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 80 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1129 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 236 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 88 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 14776 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 230 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1129 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9097 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 177 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 345 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2538 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 227 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14039 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 174 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 10509 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 17564 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 17547 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6232 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 33 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 728 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2652 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1357 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 6 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 5939 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 34 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 671 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2611 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1355 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 12813 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10578 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 47 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6130 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3561 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13982 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.756544 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.394074 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 12555 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 31 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 10392 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 59 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5880 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3411 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13513 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.769037 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.410550 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9591 68.60% 68.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1568 11.21% 79.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1143 8.17% 87.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 728 5.21% 93.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 479 3.43% 96.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 273 1.95% 98.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 154 1.10% 99.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 33 0.24% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 13 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9295 68.79% 68.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1391 10.29% 79.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1141 8.44% 87.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 752 5.57% 93.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 466 3.45% 96.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 269 1.99% 98.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 153 1.13% 99.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 32 0.24% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13982 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13513 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 10 8.70% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 65 56.52% 65.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 40 34.78% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11 9.57% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 65 56.52% 66.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 39 33.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7162 67.71% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2248 21.25% 89.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1163 10.99% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7044 67.78% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2192 21.09% 88.92% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1151 11.08% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10578 # Type of FU issued -system.cpu.iq.rate 0.426704 # Inst issue rate +system.cpu.iq.FU_type_0::total 10392 # Type of FU issued +system.cpu.iq.rate 0.449151 # Inst issue rate system.cpu.iq.fu_busy_cnt 115 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010872 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 35279 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 18978 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9581 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.011066 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 34450 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 18472 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9469 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10680 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10494 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1469 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1428 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 492 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 490 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1171 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 12931 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 181 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2652 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1357 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1129 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 12672 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 152 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2611 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1355 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 151 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 403 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 554 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 9992 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2057 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 586 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 18 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 142 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 377 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 519 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 9865 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2029 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 527 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 88 # number of nop insts executed -system.cpu.iew.exec_refs 3174 # number of memory reference insts executed -system.cpu.iew.exec_branches 1621 # Number of branches executed -system.cpu.iew.exec_stores 1117 # Number of stores executed -system.cpu.iew.exec_rate 0.403066 # Inst execution rate -system.cpu.iew.wb_sent 9749 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9591 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5054 # num instructions producing a value -system.cpu.iew.wb_consumers 6863 # num instructions consuming a value +system.cpu.iew.exec_nop 86 # number of nop insts executed +system.cpu.iew.exec_refs 3139 # number of memory reference insts executed +system.cpu.iew.exec_branches 1600 # Number of branches executed +system.cpu.iew.exec_stores 1110 # Number of stores executed +system.cpu.iew.exec_rate 0.426373 # Inst execution rate +system.cpu.iew.wb_sent 9638 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9479 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5022 # num instructions producing a value +system.cpu.iew.wb_consumers 6814 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.386890 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.736413 # average fanout of values written-back +system.cpu.iew.wb_rate 0.409690 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.737012 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6541 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6282 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 462 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12811 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.498712 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.314684 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 432 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12384 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.515908 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.366435 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10031 78.30% 78.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1473 11.50% 89.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 525 4.10% 93.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 241 1.88% 95.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 164 1.28% 97.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 92 0.72% 97.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 108 0.84% 98.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 37 0.29% 98.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 140 1.09% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9732 78.59% 78.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1344 10.85% 89.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 509 4.11% 93.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 223 1.80% 95.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 188 1.52% 96.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 75 0.61% 97.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 105 0.85% 98.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 63 0.51% 98.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 145 1.17% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12811 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12384 # Number of insts commited each cycle system.cpu.commit.committedInsts 6389 # Number of instructions committed system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -308,70 +466,70 @@ system.cpu.commit.branches 1050 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6307 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. -system.cpu.commit.bw_lim_events 140 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 145 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 25250 # The number of ROB reads -system.cpu.rob.rob_writes 27045 # The number of ROB writes -system.cpu.timesIdled 255 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 10808 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 24559 # The number of ROB reads +system.cpu.rob.rob_writes 26483 # The number of ROB writes +system.cpu.timesIdled 248 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 9624 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6372 # Number of Instructions Simulated -system.cpu.cpi 3.890458 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.890458 # CPI: Total CPI of All Threads -system.cpu.ipc 0.257039 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.257039 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12699 # number of integer regfile reads -system.cpu.int_regfile_writes 7211 # number of integer regfile writes +system.cpu.cpi 3.631042 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.631042 # CPI: Total CPI of All Threads +system.cpu.ipc 0.275403 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.275403 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12554 # number of integer regfile reads +system.cpu.int_regfile_writes 7112 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 158.537993 # Cycle average of tags in use -system.cpu.icache.total_refs 1881 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 313 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6.009585 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 160.502909 # Cycle average of tags in use +system.cpu.icache.total_refs 1827 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.818471 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 158.537993 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.077411 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.077411 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1881 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1881 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1881 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1881 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1881 # number of overall hits -system.cpu.icache.overall_hits::total 1881 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 455 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 455 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 455 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 455 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 455 # number of overall misses -system.cpu.icache.overall_misses::total 455 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15830500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15830500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15830500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15830500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15830500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15830500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2336 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2336 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2336 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2336 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2336 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2336 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.194777 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.194777 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.194777 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.194777 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.194777 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.194777 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34792.307692 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34792.307692 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34792.307692 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34792.307692 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34792.307692 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34792.307692 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 160.502909 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.078371 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.078371 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1827 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1827 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1827 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1827 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1827 # number of overall hits +system.cpu.icache.overall_hits::total 1827 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 434 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 434 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 434 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 434 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 434 # number of overall misses +system.cpu.icache.overall_misses::total 434 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13420000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13420000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13420000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13420000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13420000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13420000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2261 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2261 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2261 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2261 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2261 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2261 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.191950 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.191950 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.191950 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.191950 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10333000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10333000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10333000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138877 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138877 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138877 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.138877 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138877 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.138877 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32907.643312 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32907.643312 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32907.643312 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 32907.643312 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32907.643312 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 32907.643312 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 107.969871 # Cycle average of tags in use -system.cpu.dcache.total_refs 2254 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 177 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.734463 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 107.685258 # Cycle average of tags in use +system.cpu.dcache.total_refs 2236 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 173 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.924855 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 107.969871 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.026360 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.026360 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1748 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1748 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2254 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2254 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2254 # number of overall hits -system.cpu.dcache.overall_hits::total 2254 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 168 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 168 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 527 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 527 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 527 # number of overall misses -system.cpu.dcache.overall_misses::total 527 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6365000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6365000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12897000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12897000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19262000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19262000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19262000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19262000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1916 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1916 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 107.685258 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.026290 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.026290 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1732 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1732 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 504 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 504 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2236 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2236 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2236 # number of overall hits +system.cpu.dcache.overall_hits::total 2236 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 158 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 158 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 361 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 361 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 519 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 519 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 519 # 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number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2781 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2781 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2781 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2781 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087683 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.087683 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.189500 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.189500 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.189500 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.189500 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37886.904762 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 37886.904762 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35924.791086 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35924.791086 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36550.284630 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36550.284630 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36550.284630 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36550.284630 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 2755 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2755 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2755 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2755 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083598 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.083598 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.417341 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.417341 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.188385 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.188385 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.188385 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.188385 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38069.620253 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 38069.620253 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26717.451524 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26717.451524 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30173.410405 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30173.410405 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30173.410405 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30173.410405 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -476,119 +634,119 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 286 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 286 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 177 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 177 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 177 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 177 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4341000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4341000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2884500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2884500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7225500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7225500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7225500 # 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average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39513.698630 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39513.698630 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 40822.033898 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 40822.033898 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 40822.033898 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 40822.033898 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 289 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 289 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 346 # 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mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997959 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997947 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997959 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32733.974359 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37548.076923 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33937.500000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35301.369863 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35301.369863 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32733.974359 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36621.468927 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34141.104294 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32733.974359 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36621.468927 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34141.104294 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997947 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28448.753994 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38015.800000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 30765.230024 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 27493.589041 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 27493.589041 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28448.753994 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33575.791908 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 30273.810700 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28448.753994 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33575.791908 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30273.810700 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 7f4e477cc..d5e0f20d7 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000007 # Number of seconds simulated -sim_ticks 7079000 # Number of ticks simulated -final_tick 7079000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000006 # Number of seconds simulated +sim_ticks 6408000 # Number of ticks simulated +final_tick 6408000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 8209 # Simulator instruction rate (inst/s) -host_op_rate 8209 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24342914 # Simulator tick rate (ticks/s) -host_mem_usage 218360 # Number of bytes of host memory used -host_seconds 0.29 # Real time elapsed on the host +host_inst_rate 494 # Simulator instruction rate (inst/s) +host_op_rate 494 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1327192 # Simulator tick rate (ticks/s) +host_mem_usage 215760 # Number of bytes of host memory used +host_seconds 4.83 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 12032 # Number of bytes read from this memory @@ -19,34 +19,192 @@ system.physmem.bytes_inst_read::total 12032 # Nu system.physmem.num_reads::cpu.inst 188 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 273 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1699675095 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 768470123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2468145218 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1699675095 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1699675095 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1699675095 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 768470123 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2468145218 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1877652934 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 848938826 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2726591760 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1877652934 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1877652934 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1877652934 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 848938826 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2726591760 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 273 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 273 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 17472 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 17472 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 2 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 6 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 10 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 23 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 9 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 27 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 25 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 36 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 21 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 16 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 6357500 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 273 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 137 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 90 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 1341773 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 7053773 # Sum of mem lat for all requests +system.physmem.totBusLat 1092000 # Total cycles spent in databus access +system.physmem.totBankLat 4620000 # Total cycles spent in bank access +system.physmem.avgQLat 4914.92 # Average queueing delay per request +system.physmem.avgBankLat 16923.08 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 25838.00 # Average memory access latency +system.physmem.avgRdBW 2726.59 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 2726.59 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 17.04 # Data bus utilization in percentage +system.physmem.avgRdQLen 1.10 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 229 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.88 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 23287.55 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 712 # DTB read hits -system.cpu.dtb.read_misses 34 # DTB read misses +system.cpu.dtb.read_hits 718 # DTB read hits +system.cpu.dtb.read_misses 36 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 746 # DTB read accesses -system.cpu.dtb.write_hits 367 # DTB write hits -system.cpu.dtb.write_misses 20 # DTB write misses +system.cpu.dtb.read_accesses 754 # DTB read accesses +system.cpu.dtb.write_hits 382 # DTB write hits +system.cpu.dtb.write_misses 24 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 387 # DTB write accesses -system.cpu.dtb.data_hits 1079 # DTB hits -system.cpu.dtb.data_misses 54 # DTB misses +system.cpu.dtb.write_accesses 406 # DTB write accesses +system.cpu.dtb.data_hits 1100 # DTB hits +system.cpu.dtb.data_misses 60 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1133 # DTB accesses -system.cpu.itb.fetch_hits 1015 # ITB hits +system.cpu.dtb.data_accesses 1160 # DTB accesses +system.cpu.itb.fetch_hits 1042 # ITB hits system.cpu.itb.fetch_misses 30 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1045 # ITB accesses +system.cpu.itb.fetch_accesses 1072 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,244 +218,244 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 14159 # number of cpu cycles simulated +system.cpu.numCycles 12817 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 1131 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 569 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 255 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 792 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 219 # Number of BTB hits +system.cpu.BPredUnit.lookups 1162 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 576 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 259 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 820 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 228 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 213 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 37 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 4177 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6936 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1131 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 432 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1190 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 862 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 243 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 224 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 39 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 4082 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 7077 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1162 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 452 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1223 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 886 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 261 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 902 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1015 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 171 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7112 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.975253 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.397370 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 857 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1042 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 173 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 7043 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.004827 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.418564 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 5922 83.27% 83.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 52 0.73% 84.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 129 1.81% 85.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 100 1.41% 87.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 139 1.95% 89.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 63 0.89% 90.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 67 0.94% 91.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 67 0.94% 91.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 573 8.06% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 5820 82.64% 82.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 52 0.74% 83.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 133 1.89% 85.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 101 1.43% 86.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 157 2.23% 88.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 70 0.99% 89.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 69 0.98% 90.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 64 0.91% 91.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 577 8.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7112 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.079879 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.489865 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5180 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 271 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1148 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 503 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 169 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 83 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 6175 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 293 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 503 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5278 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 59 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 172 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1058 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 42 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5909 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 16 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 15 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 4299 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6685 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6673 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 7043 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.090661 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.552157 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5035 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 297 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1173 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 15 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 523 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 176 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 84 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 6290 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 301 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 523 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5140 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 24 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 214 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1083 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 59 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 6004 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 29 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 4336 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6797 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6785 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2531 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2568 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 136 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 960 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 476 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 5031 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 172 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 984 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 506 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 5173 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 4054 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 79 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2424 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1475 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 4204 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 57 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2615 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1486 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7112 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.570022 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.279366 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7043 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.596905 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.307061 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5467 76.87% 76.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 597 8.39% 85.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 392 5.51% 90.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 263 3.70% 94.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 194 2.73% 97.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 122 1.72% 98.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 53 0.75% 99.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12 0.17% 99.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 12 0.17% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5344 75.88% 75.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 621 8.82% 84.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 394 5.59% 90.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 268 3.81% 94.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 205 2.91% 97.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 132 1.87% 98.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 55 0.78% 99.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11 0.16% 99.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 13 0.18% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7112 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7043 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2 4.65% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18 41.86% 46.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23 53.49% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2 4.26% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 22 46.81% 51.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 23 48.94% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2869 70.77% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 786 19.39% 90.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 398 9.82% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2977 70.81% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 808 19.22% 90.06% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 418 9.94% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 4054 # Type of FU issued -system.cpu.iq.rate 0.286320 # Inst issue rate -system.cpu.iq.fu_busy_cnt 43 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010607 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15329 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 7459 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3702 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 4204 # Type of FU issued +system.cpu.iq.rate 0.328002 # Inst issue rate +system.cpu.iq.fu_busy_cnt 47 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011180 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 15542 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 7792 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3821 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 4090 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 4244 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 31 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 34 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 545 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 569 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 182 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 212 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 503 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 46 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5379 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 98 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 960 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 476 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 523 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 12 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5532 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 63 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 984 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 506 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 57 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 154 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 211 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3894 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 747 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 160 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 61 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 160 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 221 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 4011 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 755 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 193 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 342 # number of nop insts executed -system.cpu.iew.exec_refs 1134 # number of memory reference insts executed -system.cpu.iew.exec_branches 652 # Number of branches executed -system.cpu.iew.exec_stores 387 # Number of stores executed -system.cpu.iew.exec_rate 0.275019 # Inst execution rate -system.cpu.iew.wb_sent 3793 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3708 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1740 # num instructions producing a value -system.cpu.iew.wb_consumers 2258 # num instructions consuming a value +system.cpu.iew.exec_nop 353 # number of nop insts executed +system.cpu.iew.exec_refs 1161 # number of memory reference insts executed +system.cpu.iew.exec_branches 678 # Number of branches executed +system.cpu.iew.exec_stores 406 # Number of stores executed +system.cpu.iew.exec_rate 0.312944 # Inst execution rate +system.cpu.iew.wb_sent 3922 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3827 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1795 # num instructions producing a value +system.cpu.iew.wb_consumers 2353 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.261883 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.770593 # average fanout of values written-back +system.cpu.iew.wb_rate 0.298588 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.762856 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2798 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2928 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 175 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6609 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.389772 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.242894 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 179 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 6520 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.395092 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.243251 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5727 86.65% 86.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 217 3.28% 89.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 312 4.72% 94.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 115 1.74% 96.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 67 1.01% 97.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 53 0.80% 98.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 34 0.51% 98.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 19 0.29% 99.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 65 0.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5631 86.37% 86.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 221 3.39% 89.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 313 4.80% 94.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 120 1.84% 96.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 64 0.98% 97.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 55 0.84% 98.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 34 0.52% 98.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22 0.34% 99.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 60 0.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6609 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6520 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -308,69 +466,69 @@ system.cpu.commit.branches 396 # Nu system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. system.cpu.commit.int_insts 2367 # Number of committed integer instructions. system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.bw_lim_events 65 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 60 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 11671 # The number of ROB reads -system.cpu.rob.rob_writes 11260 # The number of ROB writes -system.cpu.timesIdled 165 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7047 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 11717 # The number of ROB reads +system.cpu.rob.rob_writes 11541 # The number of ROB writes +system.cpu.timesIdled 158 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5774 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 5.931713 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.931713 # CPI: Total CPI of All Threads -system.cpu.ipc 0.168585 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.168585 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4712 # number of integer regfile reads -system.cpu.int_regfile_writes 2874 # number of integer regfile writes +system.cpu.cpi 5.369501 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.369501 # CPI: Total CPI of All Threads +system.cpu.ipc 0.186237 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.186237 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4858 # number of integer regfile reads +system.cpu.int_regfile_writes 2964 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 93.783034 # Cycle average of tags in use -system.cpu.icache.total_refs 767 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 92.000483 # Cycle average of tags in use +system.cpu.icache.total_refs 799 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 188 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.079787 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.250000 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 93.783034 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.045792 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.045792 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 767 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 767 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 767 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 767 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 767 # number of overall hits -system.cpu.icache.overall_hits::total 767 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 248 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 248 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 248 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 248 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 248 # number of overall misses -system.cpu.icache.overall_misses::total 248 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 9016000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 9016000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 9016000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 9016000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 9016000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 9016000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1015 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1015 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1015 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1015 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1015 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1015 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.244335 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.244335 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.244335 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.244335 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.244335 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.244335 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36354.838710 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36354.838710 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36354.838710 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36354.838710 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36354.838710 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36354.838710 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 92.000483 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.044922 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.044922 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 799 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 799 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 799 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 799 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 799 # number of overall hits +system.cpu.icache.overall_hits::total 799 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 243 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 243 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 243 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 243 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 243 # number of overall misses +system.cpu.icache.overall_misses::total 243 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 7449000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 7449000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 7449000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 7449000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 7449000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 7449000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1042 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1042 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1042 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1042 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1042 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1042 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.233205 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.233205 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.233205 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.233205 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.233205 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.233205 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30654.320988 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 30654.320988 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 30654.320988 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 30654.320988 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 30654.320988 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 30654.320988 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -379,94 +537,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 60 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 60 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 60 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 60 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 55 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 55 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 55 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 55 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 188 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 188 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 188 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6948500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 6948500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6948500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 6948500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6948500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 6948500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.185222 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.185222 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.185222 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.185222 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.185222 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.185222 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36960.106383 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36960.106383 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36960.106383 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36960.106383 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36960.106383 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36960.106383 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5938000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 5938000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5938000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 5938000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5938000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 5938000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.180422 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.180422 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.180422 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.180422 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.180422 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.180422 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 31585.106383 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 31585.106383 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 31585.106383 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 31585.106383 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 31585.106383 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 31585.106383 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 45.970482 # Cycle average of tags in use -system.cpu.dcache.total_refs 773 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 44.834744 # Cycle average of tags in use +system.cpu.dcache.total_refs 777 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 9.094118 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 9.141176 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 45.970482 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.011223 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.011223 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 560 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 560 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 44.834744 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.010946 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.010946 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 564 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 564 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 773 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 773 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 773 # number of overall hits -system.cpu.dcache.overall_hits::total 773 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 121 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 121 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 777 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 777 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 777 # number of overall hits +system.cpu.dcache.overall_hits::total 777 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 120 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 120 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 202 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 202 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 202 # number of overall misses -system.cpu.dcache.overall_misses::total 202 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4078500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4078500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3119500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3119500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7198000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7198000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7198000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7198000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 681 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 681 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 201 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 201 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 201 # number of overall misses +system.cpu.dcache.overall_misses::total 201 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3706500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3706500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2874500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2874500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6581000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6581000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6581000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6581000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 684 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 684 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 975 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 975 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 975 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 975 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.177680 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.177680 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 978 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 978 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 978 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 978 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.175439 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.175439 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.207179 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.207179 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.207179 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.207179 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33706.611570 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33706.611570 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38512.345679 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38512.345679 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35633.663366 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 35633.663366 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35633.663366 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35633.663366 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.205521 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.205521 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.205521 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.205521 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30887.500000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30887.500000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35487.654321 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35487.654321 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32741.293532 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32741.293532 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32741.293532 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32741.293532 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -475,14 +633,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 60 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 117 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 117 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 117 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 117 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 116 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 116 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 116 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 116 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses @@ -491,42 +649,42 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2530500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2530500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 981500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 981500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3512000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 3512000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3512000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 3512000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.089574 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.089574 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2417000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2417000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 953500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 953500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3370500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3370500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3370500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3370500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.089181 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.089181 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.087179 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.087179 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.087179 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.087179 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 41483.606557 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 41483.606557 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40895.833333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40895.833333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 41317.647059 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 41317.647059 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 41317.647059 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 41317.647059 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.086912 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.086912 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.086912 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.086912 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39622.950820 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39622.950820 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39729.166667 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39729.166667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 39652.941176 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 39652.941176 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 39652.941176 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 39652.941176 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 122.770960 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 120.198004 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 249 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 93.868144 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28.902816 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.002865 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000882 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.003747 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 92.103751 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 28.094254 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.002811 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000857 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.003668 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_misses::cpu.inst 188 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 249 # number of ReadReq misses @@ -538,17 +696,17 @@ system.cpu.l2cache.demand_misses::total 273 # nu system.cpu.l2cache.overall_misses::cpu.inst 188 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 273 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6760000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2469500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 9229500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 956000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 956000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 6760000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 3425500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10185500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 6760000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 3425500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10185500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 5749500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2356000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 8105500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 928000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 928000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 5749500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 3284000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 9033500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 5749500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 3284000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 9033500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 188 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) @@ -571,17 +729,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35957.446809 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40483.606557 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 37066.265060 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39833.333333 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39833.333333 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35957.446809 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40300 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 37309.523810 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35957.446809 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40300 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 37309.523810 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 30582.446809 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38622.950820 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 32552.208835 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38666.666667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38666.666667 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 30582.446809 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38635.294118 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 33089.743590 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 30582.446809 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38635.294118 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 33089.743590 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -601,17 +759,17 @@ system.cpu.l2cache.demand_mshr_misses::total 273 system.cpu.l2cache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 273 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6157500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2280500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8438000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 881500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 881500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6157500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3162000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9319500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6157500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3162000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9319500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5087760 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2153056 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7240816 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 847024 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 847024 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5087760 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3000080 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8087840 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5087760 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3000080 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8087840 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -623,17 +781,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32752.659574 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37385.245902 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33887.550201 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36729.166667 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36729.166667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32752.659574 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37200 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34137.362637 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32752.659574 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37200 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34137.362637 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 27062.553191 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35296 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 29079.582329 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35292.666667 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35292.666667 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 27062.553191 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35295.058824 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 29625.787546 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 27062.553191 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35295.058824 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 29625.787546 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index cbe28c826..122d34e0f 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,32 +1,190 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000010 # Number of seconds simulated -sim_ticks 10412000 # Number of ticks simulated -final_tick 10412000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 10062000 # Number of ticks simulated +final_tick 10062000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 32172 # Simulator instruction rate (inst/s) -host_op_rate 40134 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 72868464 # Simulator tick rate (ticks/s) -host_mem_usage 233868 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 57856 # Simulator instruction rate (inst/s) +host_op_rate 72170 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 126623534 # Simulator tick rate (ticks/s) +host_mem_usage 231188 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 4596 # Number of instructions simulated sim_ops 5734 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7872 # Number of bytes read from this memory -system.physmem.bytes_read::total 25600 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17728 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 277 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 123 # Number of read requests responded to by this memory -system.physmem.num_reads::total 400 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1702650788 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 756050711 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2458701498 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1702650788 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1702650788 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1702650788 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 756050711 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2458701498 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory +system.physmem.bytes_read::total 25472 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory +system.physmem.num_reads::total 398 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1755515802 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 775988869 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2531504671 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1755515802 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1755515802 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1755515802 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 775988869 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2531504671 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 398 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 398 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 25472 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 25472 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 48 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 43 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 44 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 12 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 25 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 62 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 10 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 34 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 10004500 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 398 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 129 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 2567898 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 10711898 # Sum of mem lat for all requests +system.physmem.totBusLat 1592000 # Total cycles spent in databus access +system.physmem.totBankLat 6552000 # Total cycles spent in bank access +system.physmem.avgQLat 6452.01 # Average queueing delay per request +system.physmem.avgBankLat 16462.31 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 26914.32 # Average memory access latency +system.physmem.avgRdBW 2531.50 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 2531.50 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 15.82 # Data bus utilization in percentage +system.physmem.avgRdQLen 1.06 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 323 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.16 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 25136.93 # Average gap between requests system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits @@ -115,243 +273,243 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 20825 # number of cpu cycles simulated +system.cpu.numCycles 20125 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2492 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1785 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 490 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1982 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 699 # Number of BTB hits +system.cpu.BPredUnit.lookups 2519 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1814 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 492 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1994 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 720 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 261 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6546 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12176 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2492 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 960 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2644 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1597 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2014 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 266 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6589 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12264 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2519 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 986 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2669 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1615 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1986 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1932 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 294 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12289 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.242575 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.647072 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1950 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12344 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.244977 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.643916 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9645 78.48% 78.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 219 1.78% 80.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 197 1.60% 81.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 227 1.85% 83.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 211 1.72% 85.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 285 2.32% 87.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 100 0.81% 88.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 133 1.08% 89.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1272 10.35% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9675 78.38% 78.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 218 1.77% 80.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 198 1.60% 81.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 234 1.90% 83.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 218 1.77% 85.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 293 2.37% 87.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 104 0.84% 88.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 141 1.14% 89.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1263 10.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12289 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.119664 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.584682 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6694 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2170 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2432 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 67 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 926 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 377 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13288 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 560 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 926 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6959 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 392 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1561 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2229 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 222 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12442 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 182 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12452 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 56629 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56357 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 12344 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.125168 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.609391 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6607 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2275 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2441 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 79 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 942 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 382 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 166 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 13351 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 557 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 942 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6879 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 421 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1584 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2242 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 276 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12528 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 23 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 224 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 12573 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 56963 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 56691 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 272 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6771 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 47 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 45 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 672 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2727 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1576 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 42 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 25 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11136 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 55 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8838 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5149 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14358 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12289 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.719180 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.401668 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 6892 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 46 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 44 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 786 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2771 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1566 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 43 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 22 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11233 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 56 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8888 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 106 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5186 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14443 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 18 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 12344 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.720026 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.398788 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8691 70.72% 70.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1369 11.14% 81.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 785 6.39% 88.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 562 4.57% 92.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 445 3.62% 96.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 257 2.09% 98.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 123 1.00% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 46 0.37% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 11 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8706 70.53% 70.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1401 11.35% 81.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 791 6.41% 88.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 558 4.52% 92.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 454 3.68% 96.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 254 2.06% 98.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 127 1.03% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 41 0.33% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 12 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12289 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12344 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4 1.81% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 143 64.71% 66.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 74 33.48% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5 2.24% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 144 64.57% 66.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 74 33.18% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5335 60.36% 60.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 8 0.09% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2273 25.72% 86.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1219 13.79% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5378 60.51% 60.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2274 25.59% 86.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1226 13.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8838 # Type of FU issued -system.cpu.iq.rate 0.424394 # Inst issue rate -system.cpu.iq.fu_busy_cnt 221 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.025006 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30263 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16340 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7981 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8888 # Type of FU issued +system.cpu.iq.rate 0.441640 # Inst issue rate +system.cpu.iq.fu_busy_cnt 223 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.025090 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30413 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16476 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8046 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9039 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9091 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1526 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 637 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1570 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 627 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 926 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 243 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 23 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11191 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 120 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2727 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1576 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 942 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 240 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 19 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11289 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2771 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1566 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 43 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 98 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 282 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 380 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8434 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2079 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 99 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 285 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8485 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2088 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 403 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3246 # number of memory reference insts executed -system.cpu.iew.exec_branches 1415 # Number of branches executed -system.cpu.iew.exec_stores 1167 # Number of stores executed -system.cpu.iew.exec_rate 0.404994 # Inst execution rate -system.cpu.iew.wb_sent 8148 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7997 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3850 # num instructions producing a value -system.cpu.iew.wb_consumers 7766 # num instructions consuming a value +system.cpu.iew.exec_refs 3261 # number of memory reference insts executed +system.cpu.iew.exec_branches 1428 # Number of branches executed +system.cpu.iew.exec_stores 1173 # Number of stores executed +system.cpu.iew.exec_rate 0.421615 # Inst execution rate +system.cpu.iew.wb_sent 8213 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8062 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3862 # num instructions producing a value +system.cpu.iew.wb_consumers 7771 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.384010 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.495751 # average fanout of values written-back +system.cpu.iew.wb_rate 0.400596 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.496976 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5462 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5560 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 38 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 332 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11364 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.504576 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.339059 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 335 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 11403 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.502850 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.330846 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9062 79.74% 79.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1091 9.60% 89.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 395 3.48% 92.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 263 2.31% 95.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 177 1.56% 96.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 168 1.48% 98.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 53 0.47% 98.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 42 0.37% 99.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 113 0.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9072 79.56% 79.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1121 9.83% 89.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 403 3.53% 92.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 263 2.31% 95.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 172 1.51% 96.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 166 1.46% 98.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 56 0.49% 98.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 36 0.32% 99.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 114 1.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11364 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11403 # Number of insts commited each cycle system.cpu.commit.committedInsts 4596 # Number of instructions committed system.cpu.commit.committedOps 5734 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -362,69 +520,69 @@ system.cpu.commit.branches 1008 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4980 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 113 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 114 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22290 # The number of ROB reads -system.cpu.rob.rob_writes 23328 # The number of ROB writes -system.cpu.timesIdled 196 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8536 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22426 # The number of ROB reads +system.cpu.rob.rob_writes 23541 # The number of ROB writes +system.cpu.timesIdled 200 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7781 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4596 # Number of Instructions Simulated system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4596 # Number of Instructions Simulated -system.cpu.cpi 4.531114 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.531114 # CPI: Total CPI of All Threads -system.cpu.ipc 0.220696 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.220696 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 38756 # number of integer regfile reads -system.cpu.int_regfile_writes 7886 # number of integer regfile writes +system.cpu.cpi 4.378808 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.378808 # CPI: Total CPI of All Threads +system.cpu.ipc 0.228373 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.228373 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39006 # number of integer regfile reads +system.cpu.int_regfile_writes 7962 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 15116 # number of misc regfile reads +system.cpu.misc_regfile_reads 15230 # number of misc regfile reads system.cpu.misc_regfile_writes 26 # number of misc regfile writes -system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 150.292417 # Cycle average of tags in use -system.cpu.icache.total_refs 1564 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.283784 # Average number of references to valid blocks. +system.cpu.icache.replacements 4 # number of replacements +system.cpu.icache.tagsinuse 152.520984 # Cycle average of tags in use +system.cpu.icache.total_refs 1592 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 295 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.396610 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 150.292417 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.073385 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.073385 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1564 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1564 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1564 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1564 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1564 # number of overall hits -system.cpu.icache.overall_hits::total 1564 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses -system.cpu.icache.overall_misses::total 368 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12876500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12876500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12876500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12876500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12876500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12876500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1932 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1932 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1932 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1932 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1932 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1932 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.190476 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.190476 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.190476 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.190476 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.190476 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.190476 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34990.489130 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34990.489130 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34990.489130 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34990.489130 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34990.489130 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34990.489130 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 152.520984 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.074473 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.074473 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1592 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1592 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1592 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1592 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1592 # number of overall hits +system.cpu.icache.overall_hits::total 1592 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 358 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 358 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 358 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 358 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 358 # number of overall misses +system.cpu.icache.overall_misses::total 358 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11241000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11241000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11241000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11241000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11241000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11241000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1950 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1950 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1950 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1950 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1950 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183590 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.183590 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.183590 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.183590 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.183590 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.183590 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31399.441341 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 31399.441341 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 31399.441341 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 31399.441341 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 31399.441341 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 31399.441341 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -433,110 +591,110 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 72 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 72 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 72 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 72 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10420500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10420500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10420500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10420500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10420500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10420500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153209 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153209 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153209 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.153209 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153209 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.153209 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35204.391892 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35204.391892 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35204.391892 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35204.391892 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35204.391892 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35204.391892 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 295 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 295 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 295 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 295 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 295 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 295 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9141000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9141000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9141000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9141000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9141000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9141000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.151282 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.151282 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.151282 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.151282 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.151282 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.151282 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 30986.440678 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 30986.440678 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 30986.440678 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 30986.440678 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 30986.440678 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 30986.440678 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 86.816564 # Cycle average of tags in use -system.cpu.dcache.total_refs 2331 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 15.857143 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 87.982117 # Cycle average of tags in use +system.cpu.dcache.total_refs 2334 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 15.986301 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 86.816564 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021195 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021195 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1709 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1709 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits +system.cpu.dcache.occ_blocks::cpu.data 87.982117 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021480 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021480 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1717 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1717 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 12 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 12 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2306 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2306 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2306 # number of overall hits -system.cpu.dcache.overall_hits::total 2306 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 186 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 186 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 2309 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2309 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2309 # number of overall hits +system.cpu.dcache.overall_hits::total 2309 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 185 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 185 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 321 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 321 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses -system.cpu.dcache.overall_misses::total 502 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6202500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6202500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11056500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11056500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 75000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 75000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17259000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17259000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17259000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17259000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1895 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1895 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 506 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 506 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 506 # number of overall misses +system.cpu.dcache.overall_misses::total 506 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5690000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5690000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10922000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10922000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 53000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 53000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16612000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16612000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16612000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16612000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1902 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1902 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 12 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 12 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2808 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2808 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2808 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2808 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098153 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098153 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2815 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2815 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2815 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2815 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097266 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.097266 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.351588 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.351588 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.133333 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.133333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.178775 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.178775 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.178775 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.178775 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33346.774194 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33346.774194 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34988.924051 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34988.924051 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34380.478088 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34380.478088 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34380.478088 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34380.478088 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.179751 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.179751 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.179751 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.179751 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30756.756757 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30756.756757 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34024.922118 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34024.922118 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 26500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 26500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32830.039526 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32830.039526 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32830.039526 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32830.039526 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -547,58 +705,58 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 81 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 274 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 279 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 279 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # 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average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40152.941176 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 37115.384615 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39452.380952 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39452.380952 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36189.964158 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39921.259843 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 37357.142857 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36189.964158 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39921.259843 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 37357.142857 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.942373 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4564000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 13771000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.935811 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.771429 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.892768 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 398 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 398 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7843874 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2768060 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10611934 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1736536 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1736536 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7843874 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4504596 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12348470 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7843874 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4504596 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12348470 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.935593 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.769231 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.892231 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935811 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.902935 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935811 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.902935 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33238.267148 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37487.654321 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34199.720670 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36369.047619 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36369.047619 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33238.267148 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37105.691057 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34427.500000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33238.267148 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37105.691057 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34427.500000 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935593 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.835616 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.902494 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935593 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.835616 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.902494 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28419.833333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34600.750000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 29808.803371 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41346.095238 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41346.095238 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28419.833333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36922.918033 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31026.306533 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28419.833333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36922.918033 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31026.306533 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 4110b4ea0..f60a54b23 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,32 +1,190 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000010 # Number of seconds simulated -sim_ticks 10412000 # Number of ticks simulated -final_tick 10412000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 10062000 # Number of ticks simulated +final_tick 10062000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 40558 # Simulator instruction rate (inst/s) -host_op_rate 50593 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 91854675 # Simulator tick rate (ticks/s) -host_mem_usage 232720 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 70596 # Simulator instruction rate (inst/s) +host_op_rate 88057 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 154493805 # Simulator tick rate (ticks/s) +host_mem_usage 230168 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 4596 # Number of instructions simulated sim_ops 5734 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7872 # Number of bytes read from this memory -system.physmem.bytes_read::total 25600 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17728 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 277 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 123 # Number of read requests responded to by this memory -system.physmem.num_reads::total 400 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1702650788 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 756050711 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2458701498 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1702650788 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1702650788 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1702650788 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 756050711 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2458701498 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory +system.physmem.bytes_read::total 25472 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory +system.physmem.num_reads::total 398 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1755515802 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 775988869 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2531504671 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1755515802 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1755515802 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1755515802 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 775988869 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2531504671 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 398 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 398 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 25472 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 25472 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 48 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 43 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 44 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 12 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 25 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 62 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 10 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 34 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 10004500 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 398 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 129 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 2567898 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 10711898 # Sum of mem lat for all requests +system.physmem.totBusLat 1592000 # Total cycles spent in databus access +system.physmem.totBankLat 6552000 # Total cycles spent in bank access +system.physmem.avgQLat 6452.01 # Average queueing delay per request +system.physmem.avgBankLat 16462.31 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 26914.32 # Average memory access latency +system.physmem.avgRdBW 2531.50 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 2531.50 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 15.82 # Data bus utilization in percentage +system.physmem.avgRdQLen 1.06 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 323 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.16 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 25136.93 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,243 +228,243 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 20825 # number of cpu cycles simulated +system.cpu.numCycles 20125 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2492 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1785 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 490 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1982 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 699 # Number of BTB hits +system.cpu.BPredUnit.lookups 2519 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1814 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 492 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1994 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 720 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 261 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6546 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12176 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2492 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 960 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2644 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1597 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2014 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 266 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6589 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12264 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2519 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 986 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2669 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1615 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1986 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1932 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 294 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12289 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.242575 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.647072 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1950 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12344 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.244977 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.643916 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9645 78.48% 78.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 219 1.78% 80.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 197 1.60% 81.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 227 1.85% 83.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 211 1.72% 85.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 285 2.32% 87.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 100 0.81% 88.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 133 1.08% 89.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1272 10.35% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9675 78.38% 78.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 218 1.77% 80.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 198 1.60% 81.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 234 1.90% 83.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 218 1.77% 85.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 293 2.37% 87.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 104 0.84% 88.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 141 1.14% 89.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1263 10.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12289 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.119664 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.584682 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6694 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2170 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2432 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 67 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 926 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 377 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13288 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 560 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 926 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6959 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 392 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1561 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2229 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 222 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12442 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 182 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12452 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 56629 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56357 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 12344 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.125168 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.609391 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6607 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2275 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2441 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 79 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 942 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 382 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 166 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 13351 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 557 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 942 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6879 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 421 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1584 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2242 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 276 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12528 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 23 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 224 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 12573 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 56963 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 56691 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 272 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6771 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 47 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 45 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 672 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2727 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1576 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 42 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 25 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11136 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 55 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8838 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5149 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14358 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12289 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.719180 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.401668 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 6892 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 46 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 44 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 786 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2771 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1566 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 43 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 22 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11233 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 56 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8888 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 106 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5186 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14443 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 18 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 12344 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.720026 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.398788 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8691 70.72% 70.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1369 11.14% 81.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 785 6.39% 88.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 562 4.57% 92.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 445 3.62% 96.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 257 2.09% 98.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 123 1.00% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 46 0.37% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 11 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8706 70.53% 70.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1401 11.35% 81.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 791 6.41% 88.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 558 4.52% 92.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 454 3.68% 96.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 254 2.06% 98.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 127 1.03% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 41 0.33% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 12 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12289 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12344 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4 1.81% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 143 64.71% 66.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 74 33.48% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5 2.24% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 144 64.57% 66.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 74 33.18% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5335 60.36% 60.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 8 0.09% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2273 25.72% 86.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1219 13.79% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5378 60.51% 60.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2274 25.59% 86.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1226 13.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8838 # Type of FU issued -system.cpu.iq.rate 0.424394 # Inst issue rate -system.cpu.iq.fu_busy_cnt 221 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.025006 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30263 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16340 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7981 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8888 # Type of FU issued +system.cpu.iq.rate 0.441640 # Inst issue rate +system.cpu.iq.fu_busy_cnt 223 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.025090 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30413 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16476 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8046 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9039 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9091 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1526 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 637 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1570 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 627 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 926 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 243 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 23 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11191 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 120 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2727 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1576 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 942 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 240 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 19 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11289 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2771 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1566 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 43 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 98 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 282 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 380 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8434 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2079 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 99 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 285 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8485 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2088 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 403 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3246 # number of memory reference insts executed -system.cpu.iew.exec_branches 1415 # Number of branches executed -system.cpu.iew.exec_stores 1167 # Number of stores executed -system.cpu.iew.exec_rate 0.404994 # Inst execution rate -system.cpu.iew.wb_sent 8148 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7997 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3850 # num instructions producing a value -system.cpu.iew.wb_consumers 7766 # num instructions consuming a value +system.cpu.iew.exec_refs 3261 # number of memory reference insts executed +system.cpu.iew.exec_branches 1428 # Number of branches executed +system.cpu.iew.exec_stores 1173 # Number of stores executed +system.cpu.iew.exec_rate 0.421615 # Inst execution rate +system.cpu.iew.wb_sent 8213 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8062 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3862 # num instructions producing a value +system.cpu.iew.wb_consumers 7771 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.384010 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.495751 # average fanout of values written-back +system.cpu.iew.wb_rate 0.400596 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.496976 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5462 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5560 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 38 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 332 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11364 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.504576 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.339059 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 335 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 11403 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.502850 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.330846 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9062 79.74% 79.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1091 9.60% 89.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 395 3.48% 92.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 263 2.31% 95.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 177 1.56% 96.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 168 1.48% 98.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 53 0.47% 98.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 42 0.37% 99.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 113 0.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9072 79.56% 79.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1121 9.83% 89.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 403 3.53% 92.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 263 2.31% 95.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 172 1.51% 96.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 166 1.46% 98.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 56 0.49% 98.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 36 0.32% 99.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 114 1.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11364 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11403 # Number of insts commited each cycle system.cpu.commit.committedInsts 4596 # Number of instructions committed system.cpu.commit.committedOps 5734 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -317,69 +475,69 @@ system.cpu.commit.branches 1008 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4980 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 113 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 114 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22290 # The number of ROB reads -system.cpu.rob.rob_writes 23328 # The number of ROB writes -system.cpu.timesIdled 196 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8536 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22426 # The number of ROB reads +system.cpu.rob.rob_writes 23541 # The number of ROB writes +system.cpu.timesIdled 200 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7781 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4596 # Number of Instructions Simulated system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4596 # Number of Instructions Simulated -system.cpu.cpi 4.531114 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.531114 # CPI: Total CPI of All Threads -system.cpu.ipc 0.220696 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.220696 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 38756 # number of integer regfile reads -system.cpu.int_regfile_writes 7886 # number of integer regfile writes +system.cpu.cpi 4.378808 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.378808 # CPI: Total CPI of All Threads +system.cpu.ipc 0.228373 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.228373 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39006 # number of integer regfile reads +system.cpu.int_regfile_writes 7962 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 15116 # number of misc regfile reads +system.cpu.misc_regfile_reads 15230 # number of misc regfile reads system.cpu.misc_regfile_writes 26 # number of misc regfile writes -system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 150.292417 # Cycle average of tags in use -system.cpu.icache.total_refs 1564 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.283784 # Average number of references to valid blocks. +system.cpu.icache.replacements 4 # number of replacements +system.cpu.icache.tagsinuse 152.520984 # Cycle average of tags in use +system.cpu.icache.total_refs 1592 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 295 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.396610 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 150.292417 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.073385 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.073385 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1564 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1564 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1564 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1564 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1564 # number of overall hits -system.cpu.icache.overall_hits::total 1564 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses -system.cpu.icache.overall_misses::total 368 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12876500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12876500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12876500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12876500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12876500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12876500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1932 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1932 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1932 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1932 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1932 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1932 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.190476 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.190476 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.190476 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.190476 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.190476 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.190476 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34990.489130 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34990.489130 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34990.489130 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34990.489130 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34990.489130 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34990.489130 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 152.520984 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.074473 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.074473 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1592 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1592 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1592 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1592 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1592 # number of overall hits +system.cpu.icache.overall_hits::total 1592 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 358 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 358 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 358 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 358 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 358 # number of overall misses +system.cpu.icache.overall_misses::total 358 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11241000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11241000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11241000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11241000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11241000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11241000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1950 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1950 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1950 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1950 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1950 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183590 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.183590 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.183590 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.183590 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.183590 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.183590 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31399.441341 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 31399.441341 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 31399.441341 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 31399.441341 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 31399.441341 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 31399.441341 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -388,110 +546,110 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 72 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 72 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 72 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 72 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10420500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10420500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10420500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10420500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10420500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10420500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153209 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153209 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153209 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.153209 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9141000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9141000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9141000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.151282 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.151282 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.151282 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.151282 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.151282 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.151282 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 30986.440678 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 30986.440678 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 30986.440678 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 30986.440678 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 30986.440678 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 30986.440678 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 86.816564 # Cycle average of tags in use -system.cpu.dcache.total_refs 2331 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 15.857143 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 87.982117 # Cycle average of tags in use +system.cpu.dcache.total_refs 2334 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 15.986301 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 86.816564 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021195 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021195 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1709 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1709 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits +system.cpu.dcache.occ_blocks::cpu.data 87.982117 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021480 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021480 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1717 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1717 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 12 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 12 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2306 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2306 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2306 # number of overall hits -system.cpu.dcache.overall_hits::total 2306 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 186 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 186 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 2309 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2309 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2309 # number of overall hits +system.cpu.dcache.overall_hits::total 2309 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 185 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 185 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 321 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 321 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses -system.cpu.dcache.overall_misses::total 502 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6202500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6202500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11056500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11056500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 75000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 75000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17259000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17259000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17259000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17259000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1895 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1895 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 506 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 506 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 506 # number of overall misses +system.cpu.dcache.overall_misses::total 506 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5690000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5690000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10922000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10922000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 53000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 53000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16612000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16612000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16612000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16612000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1902 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1902 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 12 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 12 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2808 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2808 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2808 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2808 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098153 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098153 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2815 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2815 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2815 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2815 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097266 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.097266 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.351588 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.351588 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.133333 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.133333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.178775 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.178775 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.178775 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.178775 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33346.774194 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33346.774194 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34988.924051 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34988.924051 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34380.478088 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34380.478088 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34380.478088 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34380.478088 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.179751 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.179751 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.179751 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.179751 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30756.756757 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30756.756757 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34024.922118 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34024.922118 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 26500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 26500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32830.039526 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32830.039526 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32830.039526 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32830.039526 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -502,58 +660,58 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 81 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 274 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 279 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 279 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 355 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 355 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 355 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 355 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 360 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 360 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 360 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 360 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3549000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3549000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1700000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1700000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5249000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5249000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5249000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5249000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055409 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055409 # 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average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36369.047619 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36369.047619 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33238.267148 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37105.691057 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34427.500000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33238.267148 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37105.691057 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34427.500000 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935593 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.835616 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.902494 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935593 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.835616 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.902494 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28419.833333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34600.750000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 29808.803371 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41346.095238 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41346.095238 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28419.833333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36922.918033 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31026.306533 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28419.833333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36922.918033 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31026.306533 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 04aaa0ff5..8aae2e3f0 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 20184000 # Number of ticks simulated -final_tick 20184000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000019 # Number of seconds simulated +sim_ticks 19373000 # Number of ticks simulated +final_tick 19373000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91753 # Simulator instruction rate (inst/s) -host_op_rate 91718 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 318298211 # Simulator tick rate (ticks/s) -host_mem_usage 212944 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 54522 # Simulator instruction rate (inst/s) +host_op_rate 54510 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 181593348 # Simulator tick rate (ticks/s) +host_mem_usage 216696 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory @@ -19,14 +19,172 @@ system.physmem.bytes_inst_read::total 20288 # Nu system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 455 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1005152596 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 437574316 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1442726912 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1005152596 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1005152596 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1005152596 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 437574316 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1442726912 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1047230682 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 455892221 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1503122903 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1047230682 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1047230682 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1047230682 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 455892221 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1503122903 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 455 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 455 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 29120 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 29120 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 60 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 27 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 53 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 5 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 31 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 19 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 40 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 20 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 50 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 30 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 28 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 19298000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 455 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 2404453 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12694453 # Sum of mem lat for all requests +system.physmem.totBusLat 1820000 # Total cycles spent in databus access +system.physmem.totBankLat 8470000 # Total cycles spent in bank access +system.physmem.avgQLat 5284.51 # Average queueing delay per request +system.physmem.avgBankLat 18615.38 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 27899.90 # Average memory access latency +system.physmem.avgRdBW 1503.12 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 1503.12 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 9.39 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.66 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 357 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 78.46 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 42413.19 # Average gap between requests system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -46,7 +204,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 40369 # number of cpu cycles simulated +system.cpu.numCycles 38747 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.lookups 1146 # Number of BP lookups @@ -79,9 +237,9 @@ system.cpu.contextSwitches 1 # Nu system.cpu.threadCycles 9675 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 483 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34984 # Number of cycles cpu's stages were not processed +system.cpu.idleCycles 33362 # Number of cycles cpu's stages were not processed system.cpu.runCycles 5385 # Number of cycles cpu stages are processed. -system.cpu.activity 13.339444 # Percentage of cycles cpu is active +system.cpu.activity 13.897850 # Percentage of cycles cpu is active system.cpu.comLoads 1163 # Number of Load instructions committed system.cpu.comStores 925 # Number of Store instructions committed system.cpu.comBranches 915 # Number of Branches instructions committed @@ -93,36 +251,36 @@ system.cpu.committedInsts 5814 # Nu system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total) -system.cpu.cpi 6.943412 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.664431 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.943412 # CPI: Total CPI of All Threads -system.cpu.ipc 0.144021 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.664431 # CPI: Total CPI of All Threads +system.cpu.ipc 0.150050 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.144021 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 36744 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.150050 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 35122 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 3625 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 8.979663 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 37547 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 9.355563 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 35925 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 2822 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 6.990513 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 37585 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 7.283145 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 35963 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 2784 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 6.896381 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 39127 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 7.185072 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 37505 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1242 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.076618 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 37465 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 3.205409 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 35843 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 2904 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.193639 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 7.494774 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.tagsinuse 147.108411 # Cycle average of tags in use +system.cpu.icache.tagsinuse 148.105671 # Cycle average of tags in use system.cpu.icache.total_refs 410 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1.285266 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 147.108411 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.071830 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.071830 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 148.105671 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.072317 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.072317 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 410 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 410 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 410 # number of demand (read+write) hits @@ -135,12 +293,12 @@ system.cpu.icache.demand_misses::cpu.inst 344 # n system.cpu.icache.demand_misses::total 344 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 344 # number of overall misses system.cpu.icache.overall_misses::total 344 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19298000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19298000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19298000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19298000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19298000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19298000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18000000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18000000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18000000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18000000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18000000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18000000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 754 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 754 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 754 # number of demand (read+write) accesses @@ -153,18 +311,18 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.456233 system.cpu.icache.demand_miss_rate::total 0.456233 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.456233 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.456233 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56098.837209 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56098.837209 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56098.837209 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56098.837209 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56098.837209 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56098.837209 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52325.581395 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52325.581395 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52325.581395 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52325.581395 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52325.581395 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52325.581395 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 58 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 34 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 58 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 34 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 25 # number of ReadReq MSHR hits @@ -179,34 +337,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 319 system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17456000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17456000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17456000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17456000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17456000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17456000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16448000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16448000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16448000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16448000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16448000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16448000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.423077 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.423077 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.423077 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54721.003135 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54721.003135 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54721.003135 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54721.003135 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54721.003135 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54721.003135 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51561.128527 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51561.128527 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51561.128527 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51561.128527 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51561.128527 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51561.128527 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 89.235833 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 89.430963 # Cycle average of tags in use system.cpu.dcache.total_refs 1834 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 13.289855 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 89.235833 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021786 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021786 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 89.430963 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021834 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021834 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1072 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1072 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 762 # number of WriteReq hits @@ -223,14 +381,14 @@ system.cpu.dcache.demand_misses::cpu.data 254 # n system.cpu.dcache.demand_misses::total 254 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 254 # number of overall misses system.cpu.dcache.overall_misses::total 254 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5402500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5402500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9244000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9244000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14646500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14646500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14646500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14646500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5497500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5497500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8188000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8188000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13685500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13685500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13685500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13685500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -247,20 +405,20 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.121648 system.cpu.dcache.demand_miss_rate::total 0.121648 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.121648 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.121648 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59368.131868 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59368.131868 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56711.656442 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56711.656442 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 57663.385827 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 57663.385827 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 57663.385827 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 57663.385827 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60412.087912 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60412.087912 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 50233.128834 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 50233.128834 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53879.921260 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53879.921260 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53879.921260 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53879.921260 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2389 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2069 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 103.869565 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 89.956522 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits @@ -279,14 +437,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5111000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5111000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2905000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2905000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8016000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8016000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8016000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8016000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5201000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5201000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2605000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2605000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7806000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7806000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7806000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7806000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -295,26 +453,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58747.126437 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58747.126437 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56960.784314 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56960.784314 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58086.956522 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 58086.956522 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58086.956522 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 58086.956522 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59781.609195 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59781.609195 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51078.431373 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51078.431373 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56565.217391 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 56565.217391 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56565.217391 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 56565.217391 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 204.139180 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 205.347343 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 148.719836 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 55.419344 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004539 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001691 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006230 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 149.740781 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 55.606562 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004570 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001697 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006267 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -332,17 +490,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 455 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 17110500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5017500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 22128000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2851000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2851000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 17110500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7868500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 24979000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 17110500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7868500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 24979000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16102500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5107500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 21210000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2551000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2551000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16102500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7658500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23761000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16102500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7658500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23761000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -365,17 +523,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995624 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53976.340694 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57672.413793 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 54772.277228 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55901.960784 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55901.960784 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53976.340694 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 57018.115942 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 54898.901099 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53976.340694 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57018.115942 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 54898.901099 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50796.529968 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58706.896552 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50019.607843 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50019.607843 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50796.529968 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55496.376812 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52221.978022 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50796.529968 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55496.376812 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52221.978022 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -395,17 +553,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455 system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13248500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3962500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17211000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2227500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2227500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13248500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6190000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19438500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13248500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6190000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19438500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12097521 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4026597 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16124118 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1915572 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1915572 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12097521 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5942169 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18039690 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12097521 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5942169 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18039690 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses @@ -417,17 +575,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41793.375394 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45545.977011 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42601.485149 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43676.470588 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43676.470588 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41793.375394 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44855.072464 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42721.978022 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41793.375394 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44855.072464 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42721.978022 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38162.526814 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46282.724138 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39911.183168 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37560.235294 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37560.235294 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38162.526814 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43059.195652 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39647.670330 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38162.526814 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43059.195652 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39647.670330 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 1fd33095f..85090bc10 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 12603500 # Number of ticks simulated -final_tick 12603500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000012 # Number of seconds simulated +sim_ticks 12097500 # Number of ticks simulated +final_tick 12097500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 49943 # Simulator instruction rate (inst/s) -host_op_rate 49935 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 122043566 # Simulator tick rate (ticks/s) -host_mem_usage 220512 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 46391 # Simulator instruction rate (inst/s) +host_op_rate 46381 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 108798708 # Simulator tick rate (ticks/s) +host_mem_usage 217720 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21696 # Number of bytes read from this memory @@ -19,14 +19,172 @@ system.physmem.bytes_inst_read::total 21696 # Nu system.physmem.num_reads::cpu.inst 339 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory system.physmem.num_reads::total 480 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1721426588 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 715991590 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2437418177 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1721426588 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1721426588 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1721426588 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 715991590 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2437418177 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1793428394 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 745939244 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2539367638 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1793428394 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1793428394 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1793428394 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 745939244 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2539367638 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 480 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 480 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30720 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 30720 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 64 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 30 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 23 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 54 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 6 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 20 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 40 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 18 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 17 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 40 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 52 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 30 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 12035000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 480 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 3039980 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13667980 # Sum of mem lat for all requests +system.physmem.totBusLat 1920000 # Total cycles spent in databus access +system.physmem.totBankLat 8708000 # Total cycles spent in bank access +system.physmem.avgQLat 6333.29 # Average queueing delay per request +system.physmem.avgBankLat 18141.67 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 28474.96 # Average memory access latency +system.physmem.avgRdBW 2539.37 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 2539.37 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 15.87 # Data bus utilization in percentage +system.physmem.avgRdQLen 1.13 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 380 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.17 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 25072.92 # Average gap between requests system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -46,243 +204,243 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 25208 # number of cpu cycles simulated +system.cpu.numCycles 24196 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2076 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1377 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1640 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 471 # Number of BTB hits +system.cpu.BPredUnit.lookups 2174 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1443 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 447 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1705 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 494 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 262 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 8496 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12782 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2076 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 733 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3147 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1298 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 705 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 283 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 8516 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13177 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2174 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 777 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3260 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1345 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 699 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1923 # Number of cache lines fetched +system.cpu.fetch.PendingTrapStallCycles 157 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1979 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 260 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13341 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.958099 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.266693 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 13523 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.974414 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.279455 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10194 76.41% 76.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1306 9.79% 86.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 106 0.79% 86.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 141 1.06% 88.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 294 2.20% 90.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 100 0.75% 91.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 154 1.15% 92.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 127 0.95% 93.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 919 6.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10263 75.89% 75.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1359 10.05% 85.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 113 0.84% 86.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 150 1.11% 87.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 301 2.23% 90.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 101 0.75% 90.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 159 1.18% 92.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 137 1.01% 93.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 940 6.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13341 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.082355 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.507061 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8622 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 899 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2969 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 47 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 804 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 145 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 46 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11860 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 13523 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.089850 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.544594 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8657 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 898 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3079 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 45 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 844 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 154 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 47 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12246 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 178 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 804 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8807 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 246 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 544 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2833 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 107 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11360 # Number of instructions processed by rename -system.cpu.rename.LSQFullEvents 96 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 6940 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 13521 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13517 # Number of integer rename lookups +system.cpu.rename.SquashCycles 844 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8855 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 196 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 599 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2928 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 101 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11668 # Number of instructions processed by rename +system.cpu.rename.LSQFullEvents 92 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 7112 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 13873 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13869 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3542 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 17 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 277 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2388 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1175 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 3714 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 12 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 271 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2456 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1189 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8869 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8060 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 44 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3246 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1840 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13341 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.604153 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.265993 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 9092 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 14 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8231 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 55 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3471 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1958 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13523 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.608667 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.271089 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9853 73.86% 73.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1401 10.50% 84.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 847 6.35% 90.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 533 4.00% 94.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 353 2.65% 97.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 227 1.70% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 84 0.63% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 29 0.22% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9982 73.81% 73.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1399 10.35% 84.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 867 6.41% 90.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 551 4.07% 94.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 358 2.65% 97.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 239 1.77% 99.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 85 0.63% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 28 0.21% 99.90% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13341 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13523 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3 1.97% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 97 63.82% 65.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 52 34.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3 2.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 95 63.33% 65.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 52 34.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4766 59.13% 59.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2195 27.23% 86.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1090 13.52% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4866 59.12% 59.12% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2254 27.38% 86.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1102 13.39% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8060 # Type of FU issued -system.cpu.iq.rate 0.319740 # Inst issue rate -system.cpu.iq.fu_busy_cnt 152 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018859 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29653 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12136 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7261 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8231 # Type of FU issued +system.cpu.iq.rate 0.340180 # Inst issue rate +system.cpu.iq.fu_busy_cnt 150 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.018224 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30186 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12584 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7378 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8210 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8379 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1225 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 250 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1293 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 9 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 264 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 804 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 170 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 844 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 139 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10299 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2388 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1175 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispatchedInsts 10561 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 111 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2456 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1189 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 14 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 105 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 360 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 465 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7692 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2065 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 368 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 9 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 110 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 364 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 474 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7823 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2103 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 408 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1417 # number of nop insts executed -system.cpu.iew.exec_refs 3127 # number of memory reference insts executed -system.cpu.iew.exec_branches 1305 # Number of branches executed -system.cpu.iew.exec_stores 1062 # Number of stores executed -system.cpu.iew.exec_rate 0.305141 # Inst execution rate -system.cpu.iew.wb_sent 7351 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7263 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2827 # num instructions producing a value -system.cpu.iew.wb_consumers 4035 # num instructions consuming a value +system.cpu.iew.exec_nop 1455 # number of nop insts executed +system.cpu.iew.exec_refs 3177 # number of memory reference insts executed +system.cpu.iew.exec_branches 1335 # Number of branches executed +system.cpu.iew.exec_stores 1074 # Number of stores executed +system.cpu.iew.exec_rate 0.323318 # Inst execution rate +system.cpu.iew.wb_sent 7479 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7380 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2890 # num instructions producing a value +system.cpu.iew.wb_consumers 4129 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.288123 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.700620 # average fanout of values written-back +system.cpu.iew.wb_rate 0.305009 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.699927 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4478 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4740 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 395 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12537 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.463668 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.253066 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 401 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12679 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.458475 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.250836 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10143 80.90% 80.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 988 7.88% 88.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 634 5.06% 93.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 313 2.50% 96.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 148 1.18% 97.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 91 0.73% 98.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 75 0.60% 98.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 39 0.31% 99.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106 0.85% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10300 81.24% 81.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 973 7.67% 88.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 629 4.96% 93.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 317 2.50% 96.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 148 1.17% 97.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 88 0.69% 98.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 75 0.59% 98.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 43 0.34% 99.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106 0.84% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12537 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12679 # Number of insts commited each cycle system.cpu.commit.committedInsts 5813 # Number of instructions committed system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -295,67 +453,67 @@ system.cpu.commit.int_insts 5111 # Nu system.cpu.commit.function_calls 87 # Number of function calls committed. system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22709 # The number of ROB reads -system.cpu.rob.rob_writes 21393 # The number of ROB writes -system.cpu.timesIdled 269 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11867 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23113 # The number of ROB reads +system.cpu.rob.rob_writes 21959 # The number of ROB writes +system.cpu.timesIdled 270 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 10673 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5156 # Number of Instructions Simulated system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5156 # Number of Instructions Simulated -system.cpu.cpi 4.889061 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.889061 # CPI: Total CPI of All Threads -system.cpu.ipc 0.204538 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.204538 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10482 # number of integer regfile reads -system.cpu.int_regfile_writes 5097 # number of integer regfile writes +system.cpu.cpi 4.692785 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.692785 # CPI: Total CPI of All Threads +system.cpu.ipc 0.213093 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.213093 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10646 # number of integer regfile reads +system.cpu.int_regfile_writes 5184 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 151 # number of misc regfile reads +system.cpu.misc_regfile_reads 155 # number of misc regfile reads system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 161.691170 # Cycle average of tags in use -system.cpu.icache.total_refs 1486 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 162.253661 # Cycle average of tags in use +system.cpu.icache.total_refs 1552 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 342 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.345029 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.538012 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 161.691170 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.078951 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.078951 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1486 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1486 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1486 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1486 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1486 # number of overall hits -system.cpu.icache.overall_hits::total 1486 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses -system.cpu.icache.overall_misses::total 437 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15633000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15633000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15633000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15633000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15633000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15633000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1923 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1923 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1923 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1923 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1923 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1923 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.227249 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.227249 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.227249 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.227249 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.227249 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.227249 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35773.455378 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35773.455378 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35773.455378 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35773.455378 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35773.455378 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35773.455378 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 162.253661 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.079225 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.079225 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1552 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1552 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1552 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1552 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1552 # number of overall hits +system.cpu.icache.overall_hits::total 1552 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 427 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 427 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 427 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 427 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 427 # number of overall misses +system.cpu.icache.overall_misses::total 427 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14343000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14343000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14343000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14343000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14343000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14343000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1979 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1979 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1979 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1979 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1979 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1979 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.215766 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.215766 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.215766 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.215766 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.215766 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.215766 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33590.163934 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 33590.163934 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 33590.163934 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 33590.163934 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 33590.163934 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 33590.163934 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -364,94 +522,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 85 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 342 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 342 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 342 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 342 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 342 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 342 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12431000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12431000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12431000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12431000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12431000 # 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average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36347.953216 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36347.953216 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36347.953216 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11802500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11802500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11802500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11802500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11802500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11802500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.172815 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.172815 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.172815 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.172815 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.172815 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.172815 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34510.233918 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34510.233918 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34510.233918 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 34510.233918 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34510.233918 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 34510.233918 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 90.751581 # Cycle average of tags in use -system.cpu.dcache.total_refs 2409 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 91.817694 # Cycle average of tags in use +system.cpu.dcache.total_refs 2445 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 17.085106 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 17.340426 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 90.751581 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.022156 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.022156 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1833 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1833 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 576 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 576 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2409 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2409 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2409 # number of overall hits -system.cpu.dcache.overall_hits::total 2409 # number of overall hits +system.cpu.dcache.occ_blocks::cpu.data 91.817694 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.022416 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.022416 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1868 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1868 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 577 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 577 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2445 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2445 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2445 # number of overall hits +system.cpu.dcache.overall_hits::total 2445 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 149 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 149 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 349 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 349 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses -system.cpu.dcache.overall_misses::total 498 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5432500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5432500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11660000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11660000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17092500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17092500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17092500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17092500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1982 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1982 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 348 # 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number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15425000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2017 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2017 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2907 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2907 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2907 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2907 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075177 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.075177 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.377297 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.377297 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.171311 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.171311 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.171311 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.171311 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36459.731544 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36459.731544 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33409.742120 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33409.742120 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34322.289157 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34322.289157 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34322.289157 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34322.289157 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 2942 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2942 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2942 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2942 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.073872 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.073872 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.376216 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.376216 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.168933 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.168933 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.168933 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.168933 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39704.697987 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 39704.697987 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27324.712644 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27324.712644 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31036.217304 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31036.217304 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31036.217304 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31036.217304 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -462,12 +620,12 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 298 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 298 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 357 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 357 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 357 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 357 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 297 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 297 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 356 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 356 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 356 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 356 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses @@ -476,42 +634,42 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141 system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3834500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3834500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2072000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2072000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5906500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5906500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5906500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5906500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045409 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045409 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3832000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3832000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1859000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1859000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5691000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5691000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5691000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5691000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044621 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044621 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048504 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.048504 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048504 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.048504 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 42605.555556 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 42605.555556 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40627.450980 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40627.450980 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 41890.070922 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 41890.070922 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 41890.070922 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 41890.070922 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.047927 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.047927 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.047927 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.047927 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 42577.777778 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 42577.777778 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36450.980392 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36450.980392 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 40361.702128 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 40361.702128 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 40361.702128 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 40361.702128 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 220.970580 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 222.617700 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 429 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.006993 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 163.825301 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 57.145280 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001744 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006743 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 164.369429 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 58.248271 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005016 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001778 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006794 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits @@ -529,17 +687,17 @@ system.cpu.l2cache.demand_misses::total 480 # nu system.cpu.l2cache.overall_misses::cpu.inst 339 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses system.cpu.l2cache.overall_misses::total 480 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12084000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3740000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 15824000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2020500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2020500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 12084000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 5760500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 17844500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 12084000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 5760500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 17844500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11455500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3737500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 15193000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1807500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1807500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11455500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 5545000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 17000500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11455500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 5545000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 17000500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 342 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 90 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 432 # number of ReadReq accesses(hits+misses) @@ -562,17 +720,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.993789 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991228 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.993789 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35646.017699 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 41555.555556 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 36885.780886 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39617.647059 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39617.647059 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35646.017699 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40854.609929 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 37176.041667 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35646.017699 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40854.609929 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 37176.041667 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 33792.035398 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 41527.777778 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 35414.918415 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 35441.176471 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 35441.176471 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 33792.035398 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39326.241135 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 35417.708333 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 33792.035398 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39326.241135 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 35417.708333 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -592,17 +750,17 @@ system.cpu.l2cache.demand_mshr_misses::total 480 system.cpu.l2cache.overall_mshr_misses::cpu.inst 339 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 480 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11000500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3465500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14466000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1861500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1861500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11000500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5327000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16327500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11000500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5327000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16327500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10252004 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3439074 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13691078 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1635054 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1635054 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10252004 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5074128 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15326132 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10252004 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5074128 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15326132 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993056 # mshr miss rate for ReadReq accesses @@ -614,17 +772,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993789 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.993789 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32449.852507 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38505.555556 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33720.279720 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32449.852507 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37780.141844 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34015.625000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32449.852507 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37780.141844 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34015.625000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 30241.899705 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38211.933333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31913.934732 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32059.882353 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 32059.882353 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 30241.899705 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35986.723404 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31929.441667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 30241.899705 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35986.723404 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31929.441667 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 233f5f73b..3c312e713 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,32 +1,190 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000011 # Number of seconds simulated -sim_ticks 11490500 # Number of ticks simulated -final_tick 11490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000010 # Number of seconds simulated +sim_ticks 10184500 # Number of ticks simulated +final_tick 10184500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 46998 # Simulator instruction rate (inst/s) -host_op_rate 46991 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 93211132 # Simulator tick rate (ticks/s) -host_mem_usage 217464 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 98086 # Simulator instruction rate (inst/s) +host_op_rate 98064 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 172399568 # Simulator tick rate (ticks/s) +host_mem_usage 213936 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 22464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 22528 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 6528 # Number of bytes read from this memory -system.physmem.bytes_read::total 28992 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 22464 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 22464 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 351 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 29056 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 22528 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 22528 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 352 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 102 # Number of read requests responded to by this memory -system.physmem.num_reads::total 453 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1955006310 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 568121492 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2523127801 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1955006310 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1955006310 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1955006310 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 568121492 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2523127801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 454 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2211988807 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 640974029 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2852962836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2211988807 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2211988807 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2211988807 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 640974029 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2852962836 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 454 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 454 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 29056 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 29056 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 64 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 14 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 49 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 21 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 40 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 14 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 21 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 30 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 23 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 31 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 11 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 10067000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 454 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 224 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 49 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 2091454 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11313454 # Sum of mem lat for all requests +system.physmem.totBusLat 1816000 # Total cycles spent in databus access +system.physmem.totBankLat 7406000 # Total cycles spent in bank access +system.physmem.avgQLat 4606.73 # Average queueing delay per request +system.physmem.avgBankLat 16312.78 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 24919.50 # Average memory access latency +system.physmem.avgRdBW 2852.96 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 2852.96 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 17.83 # Data bus utilization in percentage +system.physmem.avgRdQLen 1.11 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 377 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.04 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 22174.01 # Average gap between requests system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -46,243 +204,243 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 22982 # number of cpu cycles simulated +system.cpu.numCycles 20370 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2481 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 2031 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 452 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2060 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 620 # Number of BTB hits +system.cpu.BPredUnit.lookups 2504 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 2048 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 453 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2080 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 624 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 160 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 162 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 30 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7156 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14473 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2481 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 780 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2399 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1409 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 837 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 7226 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14617 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2504 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 786 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2424 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1424 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 732 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1870 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 316 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11344 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.275829 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.704070 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1887 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 318 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11348 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.288068 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.714156 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8945 78.85% 78.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 173 1.53% 80.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 163 1.44% 81.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 136 1.20% 83.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 199 1.75% 84.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 148 1.30% 86.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 251 2.21% 88.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 108 0.95% 89.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1221 10.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8924 78.64% 78.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 176 1.55% 80.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 165 1.45% 81.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 138 1.22% 82.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 200 1.76% 84.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 150 1.32% 85.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 252 2.22% 88.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 109 0.96% 89.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1234 10.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11344 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.107954 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.629754 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7303 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 957 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2216 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 11348 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.122926 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.717575 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7362 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 868 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2237 # Number of cycles decode is running system.cpu.decode.UnblockCycles 77 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 791 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 355 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12764 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 460 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 791 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7518 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 384 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2068 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 254 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12054 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 208 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10357 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 19653 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 19598 # Number of integer rename lookups +system.cpu.decode.SquashCycles 804 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 358 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 166 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12862 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 473 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 804 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7582 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 226 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 416 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2090 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 230 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12157 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 192 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 10431 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 19827 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 19772 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5359 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 5433 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 28 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 528 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2068 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1915 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 56 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 30 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10860 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 524 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2089 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1950 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 55 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 35 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 10962 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 64 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9235 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 164 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4823 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4140 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 9314 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 176 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4943 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4190 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 48 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11344 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.814087 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.547249 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 11348 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.820761 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.558908 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 7932 69.92% 69.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1090 9.61% 79.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 771 6.80% 86.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 520 4.58% 90.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 472 4.16% 95.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 326 2.87% 97.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 145 1.28% 99.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 49 0.43% 99.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 39 0.34% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 7942 69.99% 69.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1067 9.40% 79.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 770 6.79% 86.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 514 4.53% 90.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 477 4.20% 94.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 338 2.98% 97.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 150 1.32% 99.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 53 0.47% 99.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 37 0.33% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11344 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11348 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4 2.29% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.29% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 76 43.43% 45.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 95 54.29% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4 2.22% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 78 43.33% 45.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 98 54.44% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5682 61.53% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1849 20.02% 81.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1702 18.43% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5730 61.52% 61.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.54% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1859 19.96% 81.50% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1723 18.50% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9235 # Type of FU issued -system.cpu.iq.rate 0.401836 # Inst issue rate -system.cpu.iq.fu_busy_cnt 175 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018950 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30091 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 15718 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8353 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9314 # Type of FU issued +system.cpu.iq.rate 0.457241 # Inst issue rate +system.cpu.iq.fu_busy_cnt 180 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019326 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30270 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 15941 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8417 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9376 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9460 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 77 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1107 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1128 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 869 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 8 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 904 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 791 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 138 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10924 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 109 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2068 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1915 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 804 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 103 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11026 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2089 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1950 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations +system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 8 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 78 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 303 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 381 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8741 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1709 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 494 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 302 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 380 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8807 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1716 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 507 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3273 # number of memory reference insts executed -system.cpu.iew.exec_branches 1381 # Number of branches executed -system.cpu.iew.exec_stores 1564 # Number of stores executed -system.cpu.iew.exec_rate 0.380341 # Inst execution rate -system.cpu.iew.wb_sent 8540 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8380 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4334 # num instructions producing a value -system.cpu.iew.wb_consumers 6987 # num instructions consuming a value +system.cpu.iew.exec_refs 3293 # number of memory reference insts executed +system.cpu.iew.exec_branches 1392 # Number of branches executed +system.cpu.iew.exec_stores 1577 # Number of stores executed +system.cpu.iew.exec_rate 0.432351 # Inst execution rate +system.cpu.iew.wb_sent 8605 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8444 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4397 # num instructions producing a value +system.cpu.iew.wb_consumers 7138 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.364633 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.620295 # average fanout of values written-back +system.cpu.iew.wb_rate 0.414531 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.615999 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5141 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5240 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 292 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10553 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.548849 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.335888 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 10544 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.549317 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.355880 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8133 77.07% 77.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1033 9.79% 86.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 640 6.06% 92.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 254 2.41% 95.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 184 1.74% 97.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 109 1.03% 98.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 61 0.58% 98.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 42 0.40% 99.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 97 0.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8175 77.53% 77.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 992 9.41% 86.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 623 5.91% 92.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 255 2.42% 95.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 176 1.67% 96.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 108 1.02% 97.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 67 0.64% 98.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 41 0.39% 98.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 107 1.01% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10553 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 10544 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -293,68 +451,68 @@ system.cpu.commit.branches 1037 # Nu system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. system.cpu.commit.int_insts 5698 # Number of committed integer instructions. system.cpu.commit.function_calls 103 # Number of function calls committed. -system.cpu.commit.bw_lim_events 97 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 107 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21389 # The number of ROB reads -system.cpu.rob.rob_writes 22658 # The number of ROB writes -system.cpu.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11638 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 21469 # The number of ROB reads +system.cpu.rob.rob_writes 22869 # The number of ROB writes +system.cpu.timesIdled 234 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 9022 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5792 # Number of Instructions Simulated -system.cpu.cpi 3.967887 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.967887 # CPI: Total CPI of All Threads -system.cpu.ipc 0.252023 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.252023 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13882 # number of integer regfile reads -system.cpu.int_regfile_writes 7254 # number of integer regfile writes +system.cpu.cpi 3.516920 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.516920 # CPI: Total CPI of All Threads +system.cpu.ipc 0.284340 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.284340 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13990 # number of integer regfile reads +system.cpu.int_regfile_writes 7309 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 173.017509 # Cycle average of tags in use -system.cpu.icache.total_refs 1435 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 356 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.030899 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 172.348292 # Cycle average of tags in use +system.cpu.icache.total_refs 1461 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 357 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4.092437 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 173.017509 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.084481 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.084481 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1435 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1435 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1435 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1435 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1435 # number of overall hits -system.cpu.icache.overall_hits::total 1435 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 435 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 435 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 435 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 435 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 435 # number of overall misses -system.cpu.icache.overall_misses::total 435 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15962500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15962500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15962500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15962500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15962500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15962500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1870 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1870 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1870 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1870 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1870 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1870 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.232620 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.232620 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.232620 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.232620 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.232620 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.232620 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36695.402299 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36695.402299 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36695.402299 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36695.402299 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36695.402299 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36695.402299 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 172.348292 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.084154 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.084154 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1461 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1461 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1461 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1461 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1461 # number of overall hits +system.cpu.icache.overall_hits::total 1461 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 426 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 426 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 426 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 426 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 426 # number of overall misses +system.cpu.icache.overall_misses::total 426 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13125000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13125000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13125000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13125000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13125000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13125000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1887 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1887 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1887 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1887 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1887 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1887 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.225755 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.225755 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.225755 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.225755 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.225755 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.225755 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30809.859155 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 30809.859155 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 30809.859155 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 30809.859155 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 30809.859155 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 30809.859155 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -363,94 +521,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 356 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 356 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 356 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 356 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 356 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 356 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13118500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13118500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13118500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13118500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13118500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13118500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.190374 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.190374 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.190374 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.190374 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.190374 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.190374 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36849.719101 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36849.719101 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36849.719101 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36849.719101 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36849.719101 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36849.719101 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 357 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 357 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 357 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 357 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 357 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 357 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10853500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10853500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10853500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10853500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10853500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10853500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.189189 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.189189 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.189189 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.189189 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.189189 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.189189 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 30401.960784 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 30401.960784 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 30401.960784 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 30401.960784 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 30401.960784 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 30401.960784 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 63.294290 # Cycle average of tags in use -system.cpu.dcache.total_refs 2199 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 63.058180 # Cycle average of tags in use +system.cpu.dcache.total_refs 2201 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 102 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 21.558824 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 21.578431 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 63.294290 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.015453 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.015453 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1487 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1487 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 712 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 712 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2199 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2199 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2199 # number of overall hits -system.cpu.dcache.overall_hits::total 2199 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 94 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 94 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 334 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 334 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 428 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 428 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 428 # number of overall misses -system.cpu.dcache.overall_misses::total 428 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3573500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3573500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11341500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11341500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14915000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14915000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14915000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14915000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1581 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1581 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 63.058180 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.015395 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.015395 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1483 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1483 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 718 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 718 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2201 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2201 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2201 # number of overall hits +system.cpu.dcache.overall_hits::total 2201 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 92 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 92 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 328 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 328 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 420 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 420 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 420 # number of overall misses +system.cpu.dcache.overall_misses::total 420 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3276500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3276500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9157000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9157000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12433500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12433500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12433500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12433500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1575 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1575 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2627 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2627 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2627 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2627 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.059456 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.059456 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.319312 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.319312 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.162923 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.162923 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.162923 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.162923 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38015.957447 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 38015.957447 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33956.586826 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33956.586826 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34848.130841 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34848.130841 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34848.130841 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34848.130841 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 2621 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2621 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2621 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2621 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.058413 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.058413 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.313576 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.313576 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.160244 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.160244 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.160244 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.160244 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35614.130435 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 35614.130435 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27917.682927 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27917.682927 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29603.571429 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29603.571429 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 29603.571429 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29603.571429 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -459,14 +617,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11632000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3833500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15465500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11632000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3833500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15465500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 454 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9262482 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1897546 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11160028 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1863544 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1863544 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9262482 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3761090 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13023572 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9262482 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3761090 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13023572 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985994 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987835 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987864 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985994 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.989083 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.989107 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985994 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.989083 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33139.601140 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 36009.090909 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33528.325123 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39425.531915 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39425.531915 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33139.601140 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37583.333333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34140.176600 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33139.601140 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37583.333333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34140.176600 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.989107 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 26313.869318 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34500.836364 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 27420.216216 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39649.872340 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39649.872340 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 26313.869318 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36873.431373 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 28686.281938 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 26313.869318 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36873.431373 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 28686.281938 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index a6445a723..8df237734 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 18570500 # Number of ticks simulated -final_tick 18570500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000018 # Number of seconds simulated +sim_ticks 17991500 # Number of ticks simulated +final_tick 17991500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 78205 # Simulator instruction rate (inst/s) -host_op_rate 78177 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 272440141 # Simulator tick rate (ticks/s) -host_mem_usage 214124 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 44971 # Simulator instruction rate (inst/s) +host_op_rate 44961 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 151823718 # Simulator tick rate (ticks/s) +host_mem_usage 222708 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory @@ -19,28 +19,186 @@ system.physmem.bytes_inst_read::total 18496 # Nu system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 423 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 995988261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 461807706 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1457795967 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 995988261 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 995988261 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 995988261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 461807706 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1457795967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1028041019 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 476669538 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1504710558 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1028041019 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1028041019 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1028041019 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 476669538 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1504710558 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 423 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 423 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 27072 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 27072 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 35 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 24 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 2 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 9 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 7 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 5 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 40 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 59 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 62 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 25 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 54 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 17940000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 423 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 281 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 1964422 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11356422 # Sum of mem lat for all requests +system.physmem.totBusLat 1692000 # Total cycles spent in databus access +system.physmem.totBankLat 7700000 # Total cycles spent in bank access +system.physmem.avgQLat 4644.02 # Average queueing delay per request +system.physmem.avgBankLat 18203.31 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 26847.33 # Average memory access latency +system.physmem.avgRdBW 1504.71 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 1504.71 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 9.40 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.63 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 336 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.43 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 42411.35 # Average gap between requests system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 37142 # number of cpu cycles simulated +system.cpu.numCycles 35984 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 1632 # Number of BP lookups +system.cpu.branch_predictor.lookups 1634 # Number of BP lookups system.cpu.branch_predictor.condPredicted 1036 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 901 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 1167 # Number of BTB lookups +system.cpu.branch_predictor.BTBLookups 1169 # Number of BTB lookups system.cpu.branch_predictor.BTBHits 438 # Number of BTB hits system.cpu.branch_predictor.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 4 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 37.532134 # BTB Hit Percentage +system.cpu.branch_predictor.BTBHitPct 37.467921 # BTB Hit Percentage system.cpu.branch_predictor.predictedTaken 505 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 1127 # Number of Branches Predicted As Not Taken (False). +system.cpu.branch_predictor.predictedNotTaken 1129 # Number of Branches Predicted As Not Taken (False). system.cpu.regfile_manager.intRegFileReads 5626 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 3988 # Number of Writes to Int. Register File system.cpu.regfile_manager.intRegFileAccesses 9614 # Total Accesses (Read+Write) to the Int. Register File @@ -58,12 +216,12 @@ system.cpu.execution_unit.executions 3966 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9963 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9941 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 471 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30915 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 6227 # Number of cycles cpu stages are processed. -system.cpu.activity 16.765387 # Percentage of cycles cpu is active +system.cpu.timesIdled 470 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 29760 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 6224 # Number of cycles cpu stages are processed. +system.cpu.activity 17.296576 # Percentage of cycles cpu is active system.cpu.comLoads 715 # Number of Load instructions committed system.cpu.comStores 673 # Number of Store instructions committed system.cpu.comBranches 1115 # Number of Branches instructions committed @@ -75,120 +233,120 @@ system.cpu.committedInsts 5327 # Nu system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total) -system.cpu.cpi 6.972405 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.755022 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.972405 # CPI: Total CPI of All Threads -system.cpu.ipc 0.143423 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.755022 # CPI: Total CPI of All Threads +system.cpu.ipc 0.148038 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.143423 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 32576 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 4566 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 12.293361 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 33943 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3199 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 8.612891 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 34098 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.148038 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 31416 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 4568 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 12.694531 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 32782 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3202 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 8.898399 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 32940 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 3044 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 8.195574 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 36160 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 8.459315 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 35002 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 982 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.643907 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 33973 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 2.728991 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 32815 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 3169 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 8.532120 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 8.806692 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 136.328432 # Cycle average of tags in use -system.cpu.icache.total_refs 828 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 138.057869 # Cycle average of tags in use +system.cpu.icache.total_refs 829 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2.845361 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 2.848797 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 136.328432 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.066567 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.066567 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 828 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 828 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 828 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 828 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 828 # number of overall hits -system.cpu.icache.overall_hits::total 828 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 350 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses -system.cpu.icache.overall_misses::total 350 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19327000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19327000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19327000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19327000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19327000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19327000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1178 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1178 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1178 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1178 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1178 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1178 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.297114 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.297114 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.297114 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.297114 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.297114 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.297114 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55220 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55220 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55220 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55220 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55220 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55220 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 138.057869 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.067411 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.067411 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 829 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 829 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 829 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 829 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 829 # number of overall hits +system.cpu.icache.overall_hits::total 829 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 348 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 348 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 348 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 348 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 348 # number of overall misses +system.cpu.icache.overall_misses::total 348 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18017500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18017500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18017500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18017500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18017500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18017500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1177 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1177 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1177 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1177 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1177 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1177 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.295667 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.295667 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.295667 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.295667 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.295667 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.295667 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51774.425287 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 51774.425287 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 51774.425287 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 51774.425287 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 51774.425287 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 51774.425287 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 218 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 148 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 72.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 49.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 59 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 59 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 59 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 59 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 59 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 57 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 57 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 57 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 57 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 57 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15994000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15994000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15994000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15994000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15994000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15994000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.247029 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.247029 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.247029 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54962.199313 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54962.199313 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54962.199313 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54962.199313 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54962.199313 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54962.199313 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15219500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15219500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15219500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15219500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15219500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15219500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.247239 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.247239 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.247239 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.247239 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.247239 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.247239 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52300.687285 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52300.687285 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52300.687285 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52300.687285 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52300.687285 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52300.687285 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 82.607202 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 83.298060 # Cycle average of tags in use system.cpu.dcache.total_refs 1045 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 7.740741 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 82.607202 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020168 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020168 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 83.298060 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020336 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020336 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 391 # number of WriteReq hits @@ -205,14 +363,14 @@ system.cpu.dcache.demand_misses::cpu.data 343 # n system.cpu.dcache.demand_misses::total 343 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 343 # number of overall misses system.cpu.dcache.overall_misses::total 343 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3485500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3485500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 15720000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15720000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19205500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19205500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19205500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19205500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3323500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3323500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 13337500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 13337500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16661000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16661000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16661000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16661000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -229,20 +387,20 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.247118 system.cpu.dcache.demand_miss_rate::total 0.247118 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.247118 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.247118 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 57139.344262 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 57139.344262 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55744.680851 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55744.680851 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55992.711370 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55992.711370 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55992.711370 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55992.711370 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54483.606557 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54483.606557 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47296.099291 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47296.099291 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 48574.344023 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 48574.344023 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 48574.344023 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 48574.344023 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 4614 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3752 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 102.533333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 83.377778 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits @@ -261,14 +419,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3073000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3073000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4525000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4525000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7598000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7598000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7598000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7598000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3959500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3959500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6874500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6874500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6874500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6874500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -277,26 +435,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56907.407407 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56907.407407 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55864.197531 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55864.197531 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56281.481481 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 56281.481481 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56281.481481 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 56281.481481 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53981.481481 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53981.481481 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48882.716049 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48882.716049 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50922.222222 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 50922.222222 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50922.222222 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 50922.222222 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 161.896728 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 163.809669 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 135.841585 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 26.055143 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004146 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000795 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.004941 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 137.551022 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 26.258647 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004198 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000801 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.004999 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits @@ -317,17 +475,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15675500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3006500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18682000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4441500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4441500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15675500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7448000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23123500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15675500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7448000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23123500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14901000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2848500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 17749500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3876000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3876000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14901000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6724500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21625500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14901000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6724500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21625500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses) @@ -350,17 +508,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54240.484429 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56726.415094 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 54625.730994 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54833.333333 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54833.333333 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54240.484429 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55582.089552 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 54665.484634 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54240.484429 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55582.089552 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 54665.484634 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51560.553633 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53745.283019 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 51899.122807 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 47851.851852 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 47851.851852 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51560.553633 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50182.835821 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51124.113475 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51560.553633 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50182.835821 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51124.113475 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -380,17 +538,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423 system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12160000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2365000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14525000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3462500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3462500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12160000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5827500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17987500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12160000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5827500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17987500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11259441 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2182574 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13442015 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2846130 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2846130 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11259441 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5028704 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16288145 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11259441 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5028704 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16288145 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses @@ -402,17 +560,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42076.124567 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44622.641509 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42470.760234 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42746.913580 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42746.913580 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42076.124567 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43488.805970 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42523.640662 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42076.124567 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43488.805970 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42523.640662 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38960.003460 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41180.641509 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39304.137427 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35137.407407 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35137.407407 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38960.003460 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37527.641791 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38506.252955 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38960.003460 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37527.641791 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38506.252955 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 36ed22f0b..91efbc873 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,269 +1,427 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12215000 # Number of ticks simulated -final_tick 12215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 12009000 # Number of ticks simulated +final_tick 12009000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 33465 # Simulator instruction rate (inst/s) -host_op_rate 60609 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 75963972 # Simulator tick rate (ticks/s) -host_mem_usage 227744 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 10920 # Simulator instruction rate (inst/s) +host_op_rate 19780 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24373770 # Simulator tick rate (ticks/s) +host_mem_usage 225464 # Number of bytes of host memory used +host_seconds 0.49 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9745 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory -system.physmem.bytes_read::total 28928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9280 # Number of bytes read from this memory +system.physmem.bytes_read::total 28800 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory -system.physmem.num_reads::total 452 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1598035203 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 770200573 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2368235776 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1598035203 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1598035203 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1598035203 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 770200573 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2368235776 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 145 # Number of read requests responded to by this memory +system.physmem.num_reads::total 450 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1625447581 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 772753768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2398201349 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1625447581 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1625447581 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1625447581 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 772753768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2398201349 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 451 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 451 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28800 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28800 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 40 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 20 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 55 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 23 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 52 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 23 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 14 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 35 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 30 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 40 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 13 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 17 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 34 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 17 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 11990500 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 451 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 221 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 3096951 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13440951 # Sum of mem lat for all requests +system.physmem.totBusLat 1804000 # Total cycles spent in databus access +system.physmem.totBankLat 8540000 # Total cycles spent in bank access +system.physmem.avgQLat 6866.85 # Average queueing delay per request +system.physmem.avgBankLat 18935.70 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 29802.55 # Average memory access latency +system.physmem.avgRdBW 2398.20 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 2398.20 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 14.99 # Data bus utilization in percentage +system.physmem.avgRdQLen 1.12 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 353 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 78.27 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 26586.47 # Average gap between requests system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 24431 # number of cpu cycles simulated +system.cpu.numCycles 24019 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 3187 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 3187 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 588 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2597 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 772 # Number of BTB hits +system.cpu.BPredUnit.lookups 3185 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3185 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 589 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2591 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 779 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7858 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 15336 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3187 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 772 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4160 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2551 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 3088 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 59 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1994 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 303 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 17124 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.595013 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.047737 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 8560 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 15317 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3185 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 779 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4169 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2596 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 2320 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 142 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1999 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 297 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 17196 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.587346 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.039622 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 13067 76.31% 76.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 184 1.07% 77.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 158 0.92% 78.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 198 1.16% 79.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 177 1.03% 80.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 181 1.06% 81.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 237 1.38% 82.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 192 1.12% 84.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2730 15.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 13133 76.37% 76.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 180 1.05% 77.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 163 0.95% 78.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 205 1.19% 79.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 179 1.04% 80.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 184 1.07% 81.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 242 1.41% 83.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 193 1.12% 84.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2717 15.80% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 17124 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.130449 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.627727 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8263 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3049 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3749 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 116 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1947 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 26028 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1947 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8634 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1940 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 422 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3487 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 694 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 24257 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 601 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 26511 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 58176 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 58160 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 17196 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.132603 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.637703 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9044 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2277 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3768 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 126 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1981 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 26083 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1981 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9405 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1279 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 293 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3524 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 714 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 24459 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 19 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 613 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 26793 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 58583 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 58567 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11060 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 15451 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 33 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 33 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1918 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2379 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1816 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 8 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 21504 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 37 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 18146 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 221 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10979 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14783 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 17124 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.059682 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.899800 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 15733 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 29 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 29 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2012 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2439 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1809 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 10 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 21719 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 18260 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 229 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11155 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15144 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 21 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 17196 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.061875 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.899452 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11674 68.17% 68.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1321 7.71% 75.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 996 5.82% 81.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 705 4.12% 85.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 752 4.39% 90.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 712 4.16% 94.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 641 3.74% 98.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 280 1.64% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 43 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11700 68.04% 68.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1330 7.73% 75.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1020 5.93% 81.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 704 4.09% 85.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 773 4.50% 90.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 702 4.08% 94.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 638 3.71% 98.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 284 1.65% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 45 0.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 17124 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 17196 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166 80.19% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 80.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 21 10.14% 90.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 20 9.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 154 78.97% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 78.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 22 11.28% 90.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19 9.74% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 14557 80.22% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2050 11.30% 91.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1535 8.46% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 5 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 14636 80.15% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2090 11.45% 91.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1529 8.37% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 18146 # Type of FU issued -system.cpu.iq.rate 0.742745 # Inst issue rate -system.cpu.iq.fu_busy_cnt 207 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011407 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 53836 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 32525 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 16639 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 18260 # Type of FU issued +system.cpu.iq.rate 0.760231 # Inst issue rate +system.cpu.iq.fu_busy_cnt 195 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010679 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 54132 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 32913 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 16722 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 18345 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 18446 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 130 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 141 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1327 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 21 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1387 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 23 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 9 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 882 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 875 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1947 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1327 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 1981 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 687 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 21541 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 44 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2379 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1816 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispatchedInsts 21753 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 45 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2439 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1809 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 9 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 70 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 643 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 713 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 17109 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1898 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1037 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 71 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 652 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 723 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 17199 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1930 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1061 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3313 # number of memory reference insts executed -system.cpu.iew.exec_branches 1690 # Number of branches executed -system.cpu.iew.exec_stores 1415 # Number of stores executed -system.cpu.iew.exec_rate 0.700299 # Inst execution rate -system.cpu.iew.wb_sent 16835 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 16643 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10619 # num instructions producing a value -system.cpu.iew.wb_consumers 16444 # num instructions consuming a value +system.cpu.iew.exec_refs 3340 # number of memory reference insts executed +system.cpu.iew.exec_branches 1687 # Number of branches executed +system.cpu.iew.exec_stores 1410 # Number of stores executed +system.cpu.iew.exec_rate 0.716058 # Inst execution rate +system.cpu.iew.wb_sent 16930 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 16726 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10734 # num instructions producing a value +system.cpu.iew.wb_consumers 16630 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.681225 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.645767 # average fanout of values written-back +system.cpu.iew.wb_rate 0.696365 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.645460 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 11795 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 12007 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 595 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 15177 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.642090 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.514380 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 606 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 15215 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.640486 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.512697 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11633 76.65% 76.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1329 8.76% 85.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 606 3.99% 89.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 700 4.61% 94.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 357 2.35% 96.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 136 0.90% 97.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 126 0.83% 98.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 80 0.53% 98.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 210 1.38% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11677 76.75% 76.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1319 8.67% 85.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 603 3.96% 89.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 704 4.63% 94.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 365 2.40% 96.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 135 0.89% 97.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 125 0.82% 98.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 73 0.48% 98.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 214 1.41% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 15177 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 15215 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9745 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -274,68 +432,68 @@ system.cpu.commit.branches 1208 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 9650 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 210 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 214 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 36507 # The number of ROB reads -system.cpu.rob.rob_writes 45058 # The number of ROB writes -system.cpu.timesIdled 145 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7307 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 36753 # The number of ROB reads +system.cpu.rob.rob_writes 45519 # The number of ROB writes +system.cpu.timesIdled 141 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6823 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9745 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5380 # Number of Instructions Simulated -system.cpu.cpi 4.541078 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.541078 # CPI: Total CPI of All Threads -system.cpu.ipc 0.220212 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.220212 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 30201 # number of integer regfile reads -system.cpu.int_regfile_writes 17927 # number of integer regfile writes +system.cpu.cpi 4.464498 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.464498 # CPI: Total CPI of All Threads +system.cpu.ipc 0.223989 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.223989 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 30259 # number of integer regfile reads +system.cpu.int_regfile_writes 18088 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.misc_regfile_reads 7454 # number of misc regfile reads +system.cpu.misc_regfile_reads 7500 # number of misc regfile reads system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 147.121871 # Cycle average of tags in use -system.cpu.icache.total_refs 1595 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 307 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.195440 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 149.891095 # Cycle average of tags in use +system.cpu.icache.total_refs 1605 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 305 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.262295 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 147.121871 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.071837 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.071837 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1595 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1595 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1595 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1595 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1595 # number of overall hits -system.cpu.icache.overall_hits::total 1595 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 399 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 399 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 399 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 399 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 399 # number of overall misses -system.cpu.icache.overall_misses::total 399 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14232000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14232000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14232000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14232000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14232000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14232000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1994 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1994 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1994 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1994 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1994 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1994 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.200100 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.200100 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.200100 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.200100 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.200100 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.200100 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35669.172932 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35669.172932 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35669.172932 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35669.172932 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35669.172932 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35669.172932 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 149.891095 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.073189 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.073189 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1605 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1605 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1605 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1605 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1605 # number of overall hits +system.cpu.icache.overall_hits::total 1605 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 394 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 394 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 394 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 394 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 394 # number of overall misses +system.cpu.icache.overall_misses::total 394 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13338000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13338000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13338000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13338000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13338000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13338000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1999 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1999 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1999 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1999 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1999 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1999 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.197099 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.197099 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.197099 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.197099 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.197099 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.197099 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33852.791878 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 33852.791878 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 33852.791878 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 33852.791878 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 33852.791878 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 33852.791878 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -344,94 +502,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 92 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 92 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 92 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 92 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 92 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 307 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 307 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 307 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 307 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 307 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 307 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11314000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11314000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11314000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11314000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11314000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11314000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153962 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153962 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153962 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.153962 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153962 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.153962 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36853.420195 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36853.420195 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36853.420195 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36853.420195 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36853.420195 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36853.420195 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 88 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 88 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 88 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 88 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 88 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 88 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 306 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 306 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 306 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 306 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 306 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 306 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10626000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10626000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10626000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10626000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10626000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10626000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153077 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153077 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153077 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.153077 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153077 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.153077 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34725.490196 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34725.490196 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34725.490196 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 34725.490196 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34725.490196 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 34725.490196 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 85.059195 # Cycle average of tags in use -system.cpu.dcache.total_refs 2428 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.630137 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 84.879845 # Cycle average of tags in use +system.cpu.dcache.total_refs 2447 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 145 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 16.875862 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 85.059195 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020766 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020766 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1570 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1570 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 84.879845 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020723 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020723 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1589 # 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number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 132 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 209 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 209 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 209 # number of overall misses -system.cpu.dcache.overall_misses::total 209 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4790000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4790000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3017000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3017000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7807000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7807000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7807000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7807000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1703 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1703 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 208 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 208 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 208 # number of overall misses +system.cpu.dcache.overall_misses::total 208 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5132000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5132000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3133000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3133000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 8265000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8265000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 8265000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8265000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1721 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1721 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2637 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2637 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2637 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2637 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078097 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.078097 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2655 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2655 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2655 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2655 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076700 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.076700 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.081370 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.079257 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.079257 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.079257 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.079257 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36015.037594 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36015.037594 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39697.368421 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39697.368421 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37354.066986 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37354.066986 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37354.066986 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37354.066986 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.078343 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.078343 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.078343 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.078343 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38878.787879 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 38878.787879 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41223.684211 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41223.684211 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39735.576923 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39735.576923 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39735.576923 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39735.576923 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -446,111 +604,111 @@ system.cpu.dcache.demand_mshr_hits::cpu.data 62 system.cpu.dcache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 62 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 71 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 71 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 70 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2826000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2826000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2865000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2865000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5691000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5691000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5691000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5691000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041691 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041691 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3278500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3278500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2981000 # 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mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.055745 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055745 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.055745 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39802.816901 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39802.816901 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37697.368421 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37697.368421 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38714.285714 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 38714.285714 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38714.285714 # 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average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 36611.725664 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36078.688525 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37717.687075 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 36611.725664 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997788 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 33832.786885 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 45850 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 36076 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38223.684211 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38223.684211 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 33832.786885 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41880.136986 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 36437.915743 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 33832.786885 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41880.136986 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 36437.915743 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -560,49 +718,49 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 305 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 71 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 376 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 70 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 375 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 452 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 451 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 452 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10035000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2539500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12574500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2558000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2558000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10035000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5097500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15132500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10035000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5097500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15132500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993485 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 451 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9239430 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2977566 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12216996 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2628106 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2628106 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9239430 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5605672 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14845102 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9239430 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5605672 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14845102 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996732 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994709 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997340 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993485 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996732 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.995595 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993485 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997788 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996732 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.995595 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32901.639344 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35767.605634 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33442.819149 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33657.894737 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33657.894737 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32901.639344 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34676.870748 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33478.982301 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32901.639344 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34676.870748 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33478.982301 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997788 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 30293.213115 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42536.657143 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32578.656000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 34580.342105 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 34580.342105 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 30293.213115 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38395.013699 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32915.968958 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 30293.213115 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38395.013699 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32915.968958 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index c19d33801..9ebeed2de 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,52 +1,210 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000015 # Number of seconds simulated -sim_ticks 14818500 # Number of ticks simulated -final_tick 14818500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000017 # Number of seconds simulated +sim_ticks 16578000 # Number of ticks simulated +final_tick 16578000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95139 # Simulator instruction rate (inst/s) -host_op_rate 95123 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 110579898 # Simulator tick rate (ticks/s) -host_mem_usage 213740 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 76899 # Simulator instruction rate (inst/s) +host_op_rate 76894 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 100012302 # Simulator tick rate (ticks/s) +host_mem_usage 217664 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 12745 # Number of instructions simulated sim_ops 12745 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 40000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 22720 # Number of bytes read from this memory -system.physmem.bytes_read::total 62720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 22400 # Number of bytes read from this memory +system.physmem.bytes_read::total 62400 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 40000 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 40000 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 625 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 355 # Number of read requests responded to by this memory -system.physmem.num_reads::total 980 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2699328542 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1533218612 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4232547154 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2699328542 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2699328542 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2699328542 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1533218612 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4232547154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 350 # Number of read requests responded to by this memory +system.physmem.num_reads::total 975 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2412836289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1351188322 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3764024611 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2412836289 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2412836289 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2412836289 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1351188322 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3764024611 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 975 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 975 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 62400 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 62400 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 73 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 52 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 71 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 123 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 80 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 17 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 75 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 74 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 71 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 98 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 74 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 27 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 11 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 75 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 16446000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 975 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 159 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 326 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 63 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 16512475 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 38892475 # Sum of mem lat for all requests +system.physmem.totBusLat 3900000 # Total cycles spent in databus access +system.physmem.totBankLat 18480000 # Total cycles spent in bank access +system.physmem.avgQLat 16935.87 # Average queueing delay per request +system.physmem.avgBankLat 18953.85 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 39889.72 # Average memory access latency +system.physmem.avgRdBW 3764.02 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 3764.02 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 23.53 # Data bus utilization in percentage +system.physmem.avgRdQLen 2.35 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 738 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.69 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 16867.69 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 4173 # DTB read hits +system.cpu.dtb.read_hits 4074 # DTB read hits system.cpu.dtb.read_misses 101 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 4274 # DTB read accesses -system.cpu.dtb.write_hits 2094 # DTB write hits -system.cpu.dtb.write_misses 67 # DTB write misses +system.cpu.dtb.read_accesses 4175 # DTB read accesses +system.cpu.dtb.write_hits 2120 # DTB write hits +system.cpu.dtb.write_misses 61 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2161 # DTB write accesses -system.cpu.dtb.data_hits 6267 # DTB hits -system.cpu.dtb.data_misses 168 # DTB misses +system.cpu.dtb.write_accesses 2181 # DTB write accesses +system.cpu.dtb.data_hits 6194 # DTB hits +system.cpu.dtb.data_misses 162 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 6435 # DTB accesses -system.cpu.itb.fetch_hits 5272 # ITB hits -system.cpu.itb.fetch_misses 65 # ITB misses +system.cpu.dtb.data_accesses 6356 # DTB accesses +system.cpu.itb.fetch_hits 5134 # ITB hits +system.cpu.itb.fetch_misses 54 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 5337 # ITB accesses +system.cpu.itb.fetch_accesses 5188 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -61,358 +219,359 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload0.num_syscalls 17 # Number of system calls system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.numCycles 29638 # number of cpu cycles simulated +system.cpu.numCycles 33157 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 6610 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 3711 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1792 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 4939 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 751 # Number of BTB hits +system.cpu.BPredUnit.lookups 6335 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3524 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1643 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 4675 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 824 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 944 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 198 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 1602 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 36672 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6610 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1695 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 6124 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1868 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 47 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 5272 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 768 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 24286 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.510006 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.874831 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 962 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 181 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 1485 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 35462 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6335 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1786 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 5973 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1719 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 45 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 5134 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 754 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 24653 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.438446 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.812361 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 18162 74.78% 74.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 487 2.01% 76.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 349 1.44% 78.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 481 1.98% 80.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 433 1.78% 81.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 367 1.51% 83.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 502 2.07% 85.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 575 2.37% 87.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2930 12.06% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 18680 75.77% 75.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 457 1.85% 77.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 358 1.45% 79.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 502 2.04% 81.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 454 1.84% 82.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 361 1.46% 84.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 481 1.95% 86.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 604 2.45% 88.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2756 11.18% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 24286 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.223024 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.237330 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 34845 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5279 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5199 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 530 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2549 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 678 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 456 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 31855 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 699 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2549 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 35545 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2460 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 852 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4962 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2034 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 29496 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full -system.cpu.rename.LSQFullEvents 2078 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 22198 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 36809 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 36775 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 24653 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.191061 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.069518 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 34329 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 6707 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5019 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 579 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2403 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 637 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 388 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 30928 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 701 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2403 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34978 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3976 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 854 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4893 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1933 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 28789 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1945 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 21557 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 36008 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 35974 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 13058 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 56 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 44 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 5621 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2720 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1336 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 10 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 12417 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 55 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 43 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 5160 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2607 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1348 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 2704 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1337 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.insertedLoads 2616 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1346 # Number of stores inserted to the mem dependence unit. system.cpu.memDep1.conflictingLoads 14 # Number of conflicting loads. system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 26000 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 52 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21936 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 118 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 12217 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 6791 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 18 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 24286 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.903236 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.464516 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 25414 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 21500 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 112 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11650 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 6459 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 24653 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.872105 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.460410 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15163 62.44% 62.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3175 13.07% 75.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2422 9.97% 85.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1558 6.42% 91.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1052 4.33% 96.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 575 2.37% 98.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 252 1.04% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 64 0.26% 99.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 25 0.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15812 64.14% 64.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3038 12.32% 76.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2340 9.49% 85.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1493 6.06% 92.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1014 4.11% 96.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 592 2.40% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 274 1.11% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 77 0.31% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 13 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 24286 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 24653 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11 6.15% 6.15% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.15% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.15% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 105 58.66% 64.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 63 35.20% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 26 13.83% 13.83% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 13.83% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 13.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 13.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 13.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 13.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.83% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 101 53.72% 67.55% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 61 32.45% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7498 68.11% 68.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 68.14% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2352 21.36% 89.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1154 10.48% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7329 68.16% 68.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 68.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2278 21.19% 89.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1140 10.60% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 11009 # Type of FU issued +system.cpu.iq.FU_type_0::total 10752 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 7399 67.71% 67.73% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 67.74% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 67.76% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2369 21.68% 89.44% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1154 10.56% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 7287 67.80% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 67.83% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 67.85% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 67.85% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 67.85% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 67.85% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 67.85% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 67.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 67.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 67.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 67.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 67.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 67.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 67.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 67.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 67.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 67.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 67.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 67.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 67.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 67.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 67.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 67.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 67.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 67.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 67.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 67.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 67.85% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2302 21.42% 89.26% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1154 10.74% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 10927 # Type of FU issued +system.cpu.iq.FU_type_1::total 10748 # Type of FU issued system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type::IntAlu 14897 67.91% 67.93% # Type of FU issued -system.cpu.iq.FU_type::IntMult 2 0.01% 67.94% # Type of FU issued -system.cpu.iq.FU_type::IntDiv 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type::FloatAdd 4 0.02% 67.96% # Type of FU issued -system.cpu.iq.FU_type::FloatCmp 0 0.00% 67.96% # Type of FU issued -system.cpu.iq.FU_type::FloatCvt 0 0.00% 67.96% # Type of FU issued -system.cpu.iq.FU_type::FloatMult 0 0.00% 67.96% # Type of FU issued -system.cpu.iq.FU_type::FloatDiv 0 0.00% 67.96% # Type of FU issued -system.cpu.iq.FU_type::FloatSqrt 0 0.00% 67.96% # Type of FU issued -system.cpu.iq.FU_type::SimdAdd 0 0.00% 67.96% # Type of FU issued -system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 67.96% # Type of FU issued -system.cpu.iq.FU_type::SimdAlu 0 0.00% 67.96% # Type of FU issued -system.cpu.iq.FU_type::SimdCmp 0 0.00% 67.96% # Type of FU issued -system.cpu.iq.FU_type::SimdCvt 0 0.00% 67.96% # Type of FU issued -system.cpu.iq.FU_type::SimdMisc 0 0.00% 67.96% # Type of FU issued -system.cpu.iq.FU_type::SimdMult 0 0.00% 67.96% # Type of FU issued -system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 67.96% # Type of FU issued -system.cpu.iq.FU_type::SimdShift 0 0.00% 67.96% # Type of FU issued -system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 67.96% # Type of FU issued -system.cpu.iq.FU_type::SimdSqrt 0 0.00% 67.96% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 67.96% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 67.96% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 67.96% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 67.96% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 67.96% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 67.96% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 67.96% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 67.96% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 67.96% # Type of FU issued -system.cpu.iq.FU_type::MemRead 4721 21.52% 89.48% # Type of FU issued -system.cpu.iq.FU_type::MemWrite 2308 10.52% 100.00% # Type of FU issued +system.cpu.iq.FU_type::IntAlu 14616 67.98% 68.00% # Type of FU issued +system.cpu.iq.FU_type::IntMult 2 0.01% 68.01% # Type of FU issued +system.cpu.iq.FU_type::IntDiv 0 0.00% 68.01% # Type of FU issued +system.cpu.iq.FU_type::FloatAdd 4 0.02% 68.03% # Type of FU issued +system.cpu.iq.FU_type::FloatCmp 0 0.00% 68.03% # Type of FU issued +system.cpu.iq.FU_type::FloatCvt 0 0.00% 68.03% # Type of FU issued +system.cpu.iq.FU_type::FloatMult 0 0.00% 68.03% # Type of FU issued +system.cpu.iq.FU_type::FloatDiv 0 0.00% 68.03% # Type of FU issued +system.cpu.iq.FU_type::FloatSqrt 0 0.00% 68.03% # Type of FU issued +system.cpu.iq.FU_type::SimdAdd 0 0.00% 68.03% # Type of FU issued +system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 68.03% # Type of FU issued +system.cpu.iq.FU_type::SimdAlu 0 0.00% 68.03% # Type of FU issued +system.cpu.iq.FU_type::SimdCmp 0 0.00% 68.03% # Type of FU issued +system.cpu.iq.FU_type::SimdCvt 0 0.00% 68.03% # Type of FU issued +system.cpu.iq.FU_type::SimdMisc 0 0.00% 68.03% # Type of FU issued +system.cpu.iq.FU_type::SimdMult 0 0.00% 68.03% # Type of FU issued +system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 68.03% # Type of FU issued +system.cpu.iq.FU_type::SimdShift 0 0.00% 68.03% # Type of FU issued +system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 68.03% # Type of FU issued +system.cpu.iq.FU_type::SimdSqrt 0 0.00% 68.03% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 68.03% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 68.03% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 68.03% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 68.03% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 68.03% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 68.03% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 68.03% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 68.03% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 68.03% # Type of FU issued +system.cpu.iq.FU_type::MemRead 4580 21.30% 89.33% # Type of FU issued +system.cpu.iq.FU_type::MemWrite 2294 10.67% 100.00% # Type of FU issued system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type::total 21936 # Type of FU issued -system.cpu.iq.rate 0.740131 # Inst issue rate -system.cpu.iq.fu_busy_cnt::0 90 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 89 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 179 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.004103 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.004057 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.008160 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 68413 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 38274 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 19529 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type::total 21500 # Type of FU issued +system.cpu.iq.rate 0.648430 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 92 # FU busy when requested +system.cpu.iq.fu_busy_cnt::1 96 # FU busy when requested +system.cpu.iq.fu_busy_cnt::total 188 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.004279 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.004465 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.008744 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 67911 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 37122 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 19235 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 22089 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21662 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 56 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1537 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 471 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1424 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 15 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 483 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread1.forwLoads 69 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread1.forwLoads 72 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 1521 # Number of loads squashed -system.cpu.iew.lsq.thread1.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread1.memOrderViolation 15 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 472 # Number of stores squashed +system.cpu.iew.lsq.thread1.squashedLoads 1433 # Number of loads squashed +system.cpu.iew.lsq.thread1.ignoredResponses 10 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.memOrderViolation 18 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.squashedStores 481 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2549 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 597 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 26207 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 761 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 5424 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2673 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 52 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 35 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 2403 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2077 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 53 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 25609 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 858 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 5223 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2694 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 51 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 5 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 269 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1293 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1562 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20406 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 2135 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2153 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 4288 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1530 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 33 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 261 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1201 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1462 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20081 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 2080 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2108 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 4188 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1419 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed -system.cpu.iew.exec_nop::0 78 # number of nop insts executed -system.cpu.iew.exec_nop::1 77 # number of nop insts executed -system.cpu.iew.exec_nop::total 155 # number of nop insts executed -system.cpu.iew.exec_refs::0 3247 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 3223 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 6470 # number of memory reference insts executed -system.cpu.iew.exec_branches::0 1671 # Number of branches executed -system.cpu.iew.exec_branches::1 1692 # Number of branches executed -system.cpu.iew.exec_branches::total 3363 # Number of branches executed -system.cpu.iew.exec_stores::0 1112 # Number of stores executed -system.cpu.iew.exec_stores::1 1070 # Number of stores executed -system.cpu.iew.exec_stores::total 2182 # Number of stores executed -system.cpu.iew.exec_rate 0.688508 # Inst execution rate -system.cpu.iew.wb_sent::0 9974 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 9875 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 19849 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 9831 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 9718 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 19549 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 5093 # num instructions producing a value -system.cpu.iew.wb_producers::1 5062 # num instructions producing a value -system.cpu.iew.wb_producers::total 10155 # num instructions producing a value -system.cpu.iew.wb_consumers::0 6638 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 6585 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 13223 # num instructions consuming a value +system.cpu.iew.exec_nop::0 75 # number of nop insts executed +system.cpu.iew.exec_nop::1 69 # number of nop insts executed +system.cpu.iew.exec_nop::total 144 # number of nop insts executed +system.cpu.iew.exec_refs::0 3173 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 3212 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 6385 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1610 # Number of branches executed +system.cpu.iew.exec_branches::1 1659 # Number of branches executed +system.cpu.iew.exec_branches::total 3269 # Number of branches executed +system.cpu.iew.exec_stores::0 1093 # Number of stores executed +system.cpu.iew.exec_stores::1 1104 # Number of stores executed +system.cpu.iew.exec_stores::total 2197 # Number of stores executed +system.cpu.iew.exec_rate 0.605634 # Inst execution rate +system.cpu.iew.wb_sent::0 9747 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 9790 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 19537 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 9617 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 9638 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 19255 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 5071 # num instructions producing a value +system.cpu.iew.wb_producers::1 5050 # num instructions producing a value +system.cpu.iew.wb_producers::total 10121 # num instructions producing a value +system.cpu.iew.wb_consumers::0 6666 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 6567 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 13233 # num instructions consuming a value system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate::0 0.331703 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.327890 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.659592 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.767249 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.768717 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.767980 # average fanout of values written-back +system.cpu.iew.wb_rate::0 0.290044 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.290678 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.580722 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.760726 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.768996 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.764830 # average fanout of values written-back system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 13400 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 12822 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1351 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 24235 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.527295 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.312718 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1273 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 24601 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.519450 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.331680 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 18649 76.95% 76.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 2814 11.61% 88.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1163 4.80% 93.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 521 2.15% 95.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 359 1.48% 96.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 238 0.98% 97.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 198 0.82% 98.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 82 0.34% 99.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 211 0.87% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 19177 77.95% 77.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 2699 10.97% 88.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1115 4.53% 93.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 469 1.91% 95.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 340 1.38% 96.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 279 1.13% 97.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 190 0.77% 98.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 108 0.44% 99.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 224 0.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 24235 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 24601 # Number of insts commited each cycle system.cpu.commit.committedInsts::0 6389 # Number of instructions committed system.cpu.commit.committedInsts::1 6390 # Number of instructions committed system.cpu.commit.committedInsts::total 12779 # Number of instructions committed @@ -443,27 +602,27 @@ system.cpu.commit.int_insts::total 12614 # Nu system.cpu.commit.function_calls::0 127 # Number of function calls committed. system.cpu.commit.function_calls::1 127 # Number of function calls committed. system.cpu.commit.function_calls::total 254 # Number of function calls committed. -system.cpu.commit.bw_lim_events 211 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 224 # number cycles where commit BW limit reached system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 119797 # The number of ROB reads -system.cpu.rob.rob_writes 54926 # The number of ROB writes -system.cpu.timesIdled 290 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5352 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 119315 # The number of ROB reads +system.cpu.rob.rob_writes 53622 # The number of ROB writes +system.cpu.timesIdled 272 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8504 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6372 # Number of Instructions Simulated system.cpu.committedInsts::1 6373 # Number of Instructions Simulated system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::1 6373 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 12745 # Number of Instructions Simulated -system.cpu.cpi::0 4.651287 # CPI: Cycles Per Instruction -system.cpu.cpi::1 4.650557 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.325461 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.214994 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.215028 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.430022 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 25729 # number of integer regfile reads -system.cpu.int_regfile_writes 14801 # number of integer regfile writes +system.cpu.cpi::0 5.203547 # CPI: Cycles Per Instruction +system.cpu.cpi::1 5.202730 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.601569 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.192177 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.192207 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.384383 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 25429 # number of integer regfile reads +system.cpu.int_regfile_writes 14534 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads @@ -471,50 +630,50 @@ system.cpu.misc_regfile_writes 2 # nu system.cpu.icache.replacements::0 6 # number of replacements system.cpu.icache.replacements::1 0 # number of replacements system.cpu.icache.replacements::total 6 # number of replacements -system.cpu.icache.tagsinuse 316.337538 # Cycle average of tags in use -system.cpu.icache.total_refs 4394 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 313.964791 # Cycle average of tags in use +system.cpu.icache.total_refs 4270 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 627 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.007974 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 6.810207 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 316.337538 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.154462 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.154462 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 4394 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4394 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4394 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4394 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4394 # number of overall hits -system.cpu.icache.overall_hits::total 4394 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 878 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 878 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 878 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 878 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 878 # number of overall misses -system.cpu.icache.overall_misses::total 878 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 33797000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 33797000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 33797000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 33797000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 33797000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 33797000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5272 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5272 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5272 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5272 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5272 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5272 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.166540 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.166540 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.166540 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.166540 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.166540 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.166540 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38493.166287 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 38493.166287 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 38493.166287 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 38493.166287 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 38493.166287 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 38493.166287 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 313.964791 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.153303 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.153303 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4270 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4270 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4270 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4270 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4270 # number of overall hits +system.cpu.icache.overall_hits::total 4270 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 864 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 864 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 864 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 864 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 864 # number of overall misses +system.cpu.icache.overall_misses::total 864 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 38406500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 38406500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 38406500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 38406500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 38406500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 38406500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5134 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5134 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5134 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5134 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5134 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5134 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.168290 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.168290 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.168290 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.168290 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.168290 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.168290 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44451.967593 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 44451.967593 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 44451.967593 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 44451.967593 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 44451.967593 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 44451.967593 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -523,96 +682,96 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 251 # 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number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 627 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 627 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 627 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 627 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24965000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24965000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24965000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24965000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24965000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24965000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118930 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118930 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118930 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.118930 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118930 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.118930 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39816.586922 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39816.586922 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39816.586922 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 39816.586922 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39816.586922 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 39816.586922 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29513000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 29513000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29513000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 29513000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29513000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 29513000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.122127 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.122127 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.122127 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.122127 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.122127 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.122127 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47070.175439 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47070.175439 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47070.175439 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 47070.175439 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47070.175439 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 47070.175439 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # 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Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.053075 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 3702 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3702 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1012 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1012 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 4714 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4714 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4714 # number of overall hits -system.cpu.dcache.overall_hits::total 4714 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 344 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 344 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 718 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 718 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1062 # 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number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 4046 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 214.758121 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.052431 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.052431 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 3604 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3604 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1016 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1016 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 4620 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4620 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4620 # number of overall hits +system.cpu.dcache.overall_hits::total 4620 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 337 # 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miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.085022 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.183864 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.183864 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.183864 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.183864 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41382.267442 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41382.267442 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34040.389972 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34040.389972 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36418.549906 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36418.549906 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36418.549906 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36418.549906 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 5671 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5671 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 5671 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5671 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085511 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.085511 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.412717 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.412717 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.185329 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.185329 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.185329 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.185329 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63826.409496 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63826.409496 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32601.540616 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 32601.540616 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 42613.701237 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 42613.701237 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 42613.701237 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 42613.701237 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -621,60 +780,60 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 135 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 135 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 572 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 572 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 707 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 707 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 707 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 707 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 209 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 209 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 133 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 133 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 568 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 568 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 701 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 701 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 701 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 701 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 204 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 355 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 355 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 355 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 355 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9702000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9702000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6308500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6308500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16010500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16010500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16010500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16010500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051656 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051656 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 350 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 350 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 350 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14117500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 14117500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6787000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6787000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20904500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 20904500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20904500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 20904500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051764 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051764 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061461 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.061461 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061461 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.061461 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46421.052632 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46421.052632 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43208.904110 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43208.904110 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45100 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45100 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45100 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 45100 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061718 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.061718 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061718 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.061718 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69203.431373 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69203.431373 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46486.301370 # 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Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 833 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.002401 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 829 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002413 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 316.614928 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 122.141181 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.009662 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.003727 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.013390 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 314.254634 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 120.845997 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.009590 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.003688 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.013278 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -682,112 +841,112 @@ system.cpu.l2cache.demand_hits::total 2 # nu system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits system.cpu.l2cache.overall_hits::total 2 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 625 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 209 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 834 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 204 # 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number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 627 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 355 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 982 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 350 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 977 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996810 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.997608 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.997593 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996810 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997963 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.997953 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996810 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997963 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 38918.400000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 45361.244019 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 40532.973621 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42191.780822 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42191.780822 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 38918.400000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 44057.746479 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 40780.102041 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 38918.400000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 44057.746479 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 40780.102041 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked +system.cpu.l2cache.overall_miss_rate::total 0.997953 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 46196 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68142.156863 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 51596.501809 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 45469.178082 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 45469.178082 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 46196 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 58684.285714 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 50678.974359 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 46196 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 58684.285714 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 50678.974359 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 208 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8.166667 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 16 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 625 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 209 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 834 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 829 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 350 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 975 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 26807484 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13234146 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 40041630 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6160108 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6160108 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26807484 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19394254 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 46201738 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26807484 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19394254 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 46201738 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996810 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997608 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997593 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996810 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997963 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997953 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996810 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997963 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35778.400000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42322.966507 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37418.465228 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39078.767123 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39078.767123 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35778.400000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40988.732394 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37665.816327 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35778.400000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40988.732394 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37665.816327 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997953 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42891.974400 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64873.264706 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 48301.121834 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42192.520548 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42192.520548 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42891.974400 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55412.154286 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 47386.397949 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42891.974400 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55412.154286 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 47386.397949 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index c5840e3c9..9c26db577 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000025 # Number of seconds simulated -sim_ticks 25317500 # Number of ticks simulated -final_tick 25317500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000024 # Number of seconds simulated +sim_ticks 24110500 # Number of ticks simulated +final_tick 24110500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 84248 # Simulator instruction rate (inst/s) -host_op_rate 84237 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 140641450 # Simulator tick rate (ticks/s) -host_mem_usage 214032 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 94813 # Simulator instruction rate (inst/s) +host_op_rate 94805 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 150747979 # Simulator tick rate (ticks/s) +host_mem_usage 222632 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory @@ -19,27 +19,185 @@ system.physmem.bytes_inst_read::total 19072 # Nu system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 436 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 753312926 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 348849610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1102162536 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 753312926 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 753312926 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 753312926 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 348849610 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1102162536 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 791024657 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 366313432 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1157338089 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 791024657 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 791024657 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 791024657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 366313432 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1157338089 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 436 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 436 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 27904 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 27904 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 69 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 25 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 4 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 5 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 34 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 3 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 17 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 37 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 31 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 11 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 76 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 43 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 22 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 24077000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 436 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 305 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 1670434 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11016434 # Sum of mem lat for all requests +system.physmem.totBusLat 1744000 # Total cycles spent in databus access +system.physmem.totBankLat 7602000 # Total cycles spent in bank access +system.physmem.avgQLat 3831.27 # Average queueing delay per request +system.physmem.avgBankLat 17435.78 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 25267.05 # Average memory access latency +system.physmem.avgRdBW 1157.34 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 1157.34 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 7.23 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.46 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 359 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.34 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 55222.48 # Average gap between requests system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 50636 # number of cpu cycles simulated +system.cpu.numCycles 48222 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 5020 # Number of BP lookups +system.cpu.branch_predictor.lookups 5021 # Number of BP lookups system.cpu.branch_predictor.condPredicted 3412 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 2378 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 3517 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 2141 # Number of BTB hits +system.cpu.branch_predictor.BTBLookups 3518 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 2142 # Number of BTB hits system.cpu.branch_predictor.usedRAS 176 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 5 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 60.875746 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 2317 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.BTBHitPct 60.886868 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 2318 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 2703 # Number of Branches Predicted As Not Taken (False). system.cpu.regfile_manager.intRegFileReads 14367 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 11099 # Number of Writes to Int. Register File @@ -58,12 +216,12 @@ system.cpu.execution_unit.executions 11058 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 22132 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 22133 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 497 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 33281 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 17355 # Number of cycles cpu stages are processed. -system.cpu.activity 34.274034 # Percentage of cycles cpu is active +system.cpu.idleCycles 30866 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 17356 # Number of cycles cpu stages are processed. +system.cpu.activity 35.991871 # Percentage of cycles cpu is active system.cpu.comLoads 2225 # Number of Load instructions committed system.cpu.comStores 1448 # Number of Store instructions committed system.cpu.comBranches 3358 # Number of Branches instructions committed @@ -75,36 +233,36 @@ system.cpu.committedInsts 15162 # Nu system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total) -system.cpu.cpi 3.339665 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 3.180451 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 3.339665 # CPI: Total CPI of All Threads -system.cpu.ipc 0.299431 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 3.180451 # CPI: Total CPI of All Threads +system.cpu.ipc 0.314421 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.299431 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 37504 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.314421 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 35090 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 13132 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 25.934118 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 41449 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 9187 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 18.143218 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 41821 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 8815 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 17.408563 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 47752 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 27.232384 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 39034 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 9188 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 19.053544 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 39406 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 8816 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 18.282112 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 45338 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 2884 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 5.695553 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 41318 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 5.980673 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 38904 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 9318 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 18.401927 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 19.323131 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 164.702089 # Cycle average of tags in use +system.cpu.icache.tagsinuse 166.100833 # Cycle average of tags in use system.cpu.icache.total_refs 2586 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 8.648829 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 164.702089 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.080421 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.080421 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 166.100833 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.081104 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.081104 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 2586 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2586 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 2586 # number of demand (read+write) hits @@ -117,12 +275,12 @@ system.cpu.icache.demand_misses::cpu.inst 369 # n system.cpu.icache.demand_misses::total 369 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 369 # number of overall misses system.cpu.icache.overall_misses::total 369 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20235000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20235000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20235000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20235000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20235000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20235000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18278500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18278500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18278500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18278500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18278500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18278500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2955 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2955 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2955 # number of demand (read+write) accesses @@ -135,18 +293,18 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.124873 system.cpu.icache.demand_miss_rate::total 0.124873 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.124873 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.124873 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54837.398374 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54837.398374 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54837.398374 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54837.398374 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54837.398374 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54837.398374 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49535.230352 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49535.230352 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49535.230352 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49535.230352 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49535.230352 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49535.230352 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 131 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 85 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 65.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 42.500000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits @@ -161,34 +319,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 301 system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16329000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16329000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16329000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16329000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16329000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16329000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14783500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14783500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14783500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14783500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14783500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14783500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.101861 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.101861 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.101861 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54249.169435 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54249.169435 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54249.169435 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54249.169435 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54249.169435 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54249.169435 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49114.617940 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49114.617940 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49114.617940 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 49114.617940 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49114.617940 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 49114.617940 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 96.602865 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 97.064476 # Cycle average of tags in use system.cpu.dcache.total_refs 3314 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 24.014493 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 96.602865 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.023585 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.023585 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 97.064476 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.023697 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.023697 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1141 # number of WriteReq hits @@ -207,14 +365,14 @@ system.cpu.dcache.demand_misses::cpu.data 359 # n system.cpu.dcache.demand_misses::total 359 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 359 # number of overall misses system.cpu.dcache.overall_misses::total 359 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3411000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3411000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 16758500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 16758500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20169500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20169500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20169500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20169500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3241000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3241000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14317500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14317500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17558500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17558500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17558500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17558500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -233,20 +391,20 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.097900 system.cpu.dcache.demand_miss_rate::total 0.097900 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.097900 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.097900 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58810.344828 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 58810.344828 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55676.079734 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55676.079734 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56182.451253 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56182.451253 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56182.451253 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56182.451253 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55879.310345 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55879.310345 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47566.445183 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47566.445183 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 48909.470752 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 48909.470752 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 48909.470752 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 48909.470752 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 4519 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3701 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 100.422222 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 82.244444 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits @@ -265,14 +423,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2994500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2994500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4733000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4733000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7727500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7727500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7727500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7727500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2840500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2840500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4329000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4329000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7169500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7169500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7169500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7169500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses @@ -281,26 +439,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55682.352941 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55682.352941 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55996.376812 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 55996.376812 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55996.376812 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 55996.376812 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53594.339623 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53594.339623 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50929.411765 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50929.411765 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51952.898551 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51952.898551 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51952.898551 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51952.898551 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 195.229432 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 196.769171 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 350 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.005714 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 351 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.005698 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 164.095749 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.133683 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005008 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000950 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005958 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 165.497362 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31.271809 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005051 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000954 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006005 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -318,17 +476,17 @@ system.cpu.l2cache.demand_misses::total 437 # nu system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 437 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16005500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2940000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18945500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4645500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4645500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16005500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7585500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23591000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16005500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7585500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23591000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14500500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2786000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 17286500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4241500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4241500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14500500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7027500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21528000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14500500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7027500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21528000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses) @@ -351,17 +509,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995444 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53530.100334 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55471.698113 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 53822.443182 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54652.941176 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54652.941176 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53530.100334 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54967.391304 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 53983.981693 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53530.100334 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54967.391304 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 53983.981693 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48496.655518 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52566.037736 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 49109.375000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49900 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49900 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48496.655518 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50923.913043 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 49263.157895 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48496.655518 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50923.913043 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 49263.157895 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,17 +539,17 @@ system.cpu.l2cache.demand_mshr_misses::total 437 system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12396000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2298500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14694500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3614500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3614500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12396000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5913000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18309000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12396000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5913000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18309000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10728482 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2122568 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12851050 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3166632 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3166632 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10728482 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5289200 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16017682 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10728482 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5289200 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16017682 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses @@ -403,17 +561,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41458.193980 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43367.924528 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41745.738636 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42523.529412 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42523.529412 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41458.193980 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42847.826087 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41897.025172 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41458.193980 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42847.826087 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41897.025172 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35881.210702 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40048.452830 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36508.664773 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37254.494118 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37254.494118 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35881.210702 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38327.536232 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36653.734554 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35881.210702 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38327.536232 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36653.734554 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 5ed8e97b3..a830552cf 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,161 +1,319 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19879000 # Number of ticks simulated -final_tick 19879000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19778500 # Number of ticks simulated +final_tick 19778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 39676 # Simulator instruction rate (inst/s) -host_op_rate 39674 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54630622 # Simulator tick rate (ticks/s) -host_mem_usage 221392 # Number of bytes of host memory used -host_seconds 0.36 # Real time elapsed on the host +host_inst_rate 52882 # Simulator instruction rate (inst/s) +host_op_rate 52877 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 72439157 # Simulator tick rate (ticks/s) +host_mem_usage 223656 # Number of bytes of host memory used +host_seconds 0.27 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 21568 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory -system.physmem.bytes_read::total 30784 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 30912 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 21568 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 21568 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 337 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory -system.physmem.num_reads::total 481 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1078525077 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 470043765 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1548568841 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1078525077 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1078525077 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1078525077 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 470043765 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1548568841 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 483 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1090477033 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 472432186 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1562909220 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1090477033 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1090477033 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1090477033 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 472432186 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1562909220 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 483 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 483 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30912 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 30912 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 70 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 36 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 24 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 6 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 44 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 3 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 21 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 43 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 31 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 13 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 80 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 46 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 26 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 19726000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 483 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 137 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 3361480 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13231480 # Sum of mem lat for all requests +system.physmem.totBusLat 1932000 # Total cycles spent in databus access +system.physmem.totBankLat 7938000 # Total cycles spent in bank access +system.physmem.avgQLat 6959.59 # Average queueing delay per request +system.physmem.avgBankLat 16434.78 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 27394.37 # Average memory access latency +system.physmem.avgRdBW 1562.91 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 1562.91 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 9.77 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.67 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 394 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.57 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 40840.58 # Average gap between requests system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 39759 # number of cpu cycles simulated +system.cpu.numCycles 39558 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 6854 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 4554 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1112 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 4710 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 2490 # Number of BTB hits +system.cpu.BPredUnit.lookups 6961 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 4635 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1124 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 5126 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 2626 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 477 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 443 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 12088 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 31936 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6854 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 2967 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9404 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3148 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7222 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 11957 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 32537 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6961 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 3069 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 9617 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3192 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7429 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 741 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 5545 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 478 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 31399 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.017102 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.199996 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 834 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 5561 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 468 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 31813 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.022758 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.197280 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 21995 70.05% 70.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4682 14.91% 84.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 472 1.50% 86.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 410 1.31% 87.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 687 2.19% 89.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 719 2.29% 92.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 235 0.75% 93.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 265 0.84% 93.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1934 6.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 22196 69.77% 69.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4753 14.94% 84.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 498 1.57% 86.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 475 1.49% 87.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 708 2.23% 89.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 718 2.26% 92.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 247 0.78% 93.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 285 0.90% 93.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1933 6.08% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 31399 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.172389 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.803240 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12738 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 7939 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 8587 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 195 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1940 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 29749 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1940 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13426 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 259 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7130 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 8156 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 488 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 27133 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 140 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 24210 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 50486 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 50486 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 31813 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.175969 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.822514 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12679 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8183 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 8793 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 186 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1972 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 30371 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1972 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13365 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 199 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7520 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 8338 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 419 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 27570 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 112 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 24556 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 51144 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 51144 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10391 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 723 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 723 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2887 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3597 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2432 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 10737 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 696 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 697 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2824 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3648 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2459 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 22935 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 673 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21597 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 91 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8291 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 5610 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 198 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 31399 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.687824 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.304127 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 23227 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 659 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 21740 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8509 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 6060 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 184 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 31813 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.683368 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.298612 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 22002 70.07% 70.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3599 11.46% 81.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2373 7.56% 89.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1680 5.35% 94.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 925 2.95% 97.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 497 1.58% 98.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 251 0.80% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 55 0.18% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 22340 70.22% 70.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3583 11.26% 81.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2473 7.77% 89.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1697 5.33% 94.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 903 2.84% 97.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 492 1.55% 98.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 244 0.77% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 64 0.20% 99.95% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 17 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 31399 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 31813 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 47 27.33% 27.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 27.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 27.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 27.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 27.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 27.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 27.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 27.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 27.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 27.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 27.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 27.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 27.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 27.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 27.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 27.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 27.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 27.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 27.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 27.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 27.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 27.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 27.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 27.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 27.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 27.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 27.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 27.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 27 15.70% 43.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 98 56.98% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 50 28.09% 28.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 28.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 28.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 28.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 26 14.61% 42.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 102 57.30% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 15947 73.84% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 16052 73.84% 73.84% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.84% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.84% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.84% # Type of FU issued @@ -184,84 +342,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.84% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.84% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.84% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 3395 15.72% 89.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 2255 10.44% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 3424 15.75% 89.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 2264 10.41% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 21597 # Type of FU issued -system.cpu.iq.rate 0.543198 # Inst issue rate -system.cpu.iq.fu_busy_cnt 172 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007964 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 74856 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 31925 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 19878 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 21740 # Type of FU issued +system.cpu.iq.rate 0.549573 # Inst issue rate +system.cpu.iq.fu_busy_cnt 178 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008188 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 75584 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 32421 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 19938 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21769 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21918 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 29 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 26 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1372 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1423 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 984 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 1011 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1940 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 112 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 24765 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 456 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 3597 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2432 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 673 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1972 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 103 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 25068 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 512 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 3648 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2459 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 659 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 268 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 979 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1247 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20456 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 3252 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1141 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 296 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 961 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1257 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20524 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 3260 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1216 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1157 # number of nop insts executed -system.cpu.iew.exec_refs 5386 # number of memory reference insts executed -system.cpu.iew.exec_branches 4298 # Number of branches executed -system.cpu.iew.exec_stores 2134 # Number of stores executed -system.cpu.iew.exec_rate 0.514500 # Inst execution rate -system.cpu.iew.wb_sent 20129 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 19878 # cumulative count of insts written-back -system.cpu.iew.wb_producers 9203 # num instructions producing a value -system.cpu.iew.wb_consumers 11321 # num instructions consuming a value +system.cpu.iew.exec_nop 1182 # number of nop insts executed +system.cpu.iew.exec_refs 5396 # number of memory reference insts executed +system.cpu.iew.exec_branches 4297 # Number of branches executed +system.cpu.iew.exec_stores 2136 # Number of stores executed +system.cpu.iew.exec_rate 0.518833 # Inst execution rate +system.cpu.iew.wb_sent 20197 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 19938 # cumulative count of insts written-back +system.cpu.iew.wb_producers 9248 # num instructions producing a value +system.cpu.iew.wb_consumers 11357 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.499962 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.812914 # average fanout of values written-back +system.cpu.iew.wb_rate 0.504019 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.814300 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9531 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9816 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1112 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 29476 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.514385 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.202047 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1124 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 29858 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.507804 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.195478 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 22110 75.01% 75.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 4076 13.83% 88.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1418 4.81% 93.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 772 2.62% 96.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 337 1.14% 97.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 264 0.90% 98.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 327 1.11% 99.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 72 0.24% 99.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 100 0.34% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 22523 75.43% 75.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3989 13.36% 88.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1473 4.93% 93.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 787 2.64% 96.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 343 1.15% 97.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 245 0.82% 98.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 323 1.08% 99.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 69 0.23% 99.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106 0.36% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 29476 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 29858 # Number of insts commited each cycle system.cpu.commit.committedInsts 15162 # Number of instructions committed system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -272,68 +430,68 @@ system.cpu.commit.branches 3358 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 12174 # Number of committed integer instructions. system.cpu.commit.function_calls 187 # Number of function calls committed. -system.cpu.commit.bw_lim_events 100 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 53246 # The number of ROB reads -system.cpu.rob.rob_writes 51332 # The number of ROB writes -system.cpu.timesIdled 190 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8360 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 53907 # The number of ROB reads +system.cpu.rob.rob_writes 51935 # The number of ROB writes +system.cpu.timesIdled 182 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7745 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 14436 # Number of Instructions Simulated -system.cpu.cpi 2.754156 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.754156 # CPI: Total CPI of All Threads -system.cpu.ipc 0.363088 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.363088 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 32578 # number of integer regfile reads -system.cpu.int_regfile_writes 18091 # number of integer regfile writes -system.cpu.misc_regfile_reads 7032 # number of misc regfile reads +system.cpu.cpi 2.740233 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.740233 # CPI: Total CPI of All Threads +system.cpu.ipc 0.364933 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.364933 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 32646 # number of integer regfile reads +system.cpu.int_regfile_writes 18155 # number of integer regfile writes +system.cpu.misc_regfile_reads 7050 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 199.192019 # Cycle average of tags in use -system.cpu.icache.total_refs 5061 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 337 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 15.017804 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 200.987114 # Cycle average of tags in use +system.cpu.icache.total_refs 5096 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 339 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 15.032448 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 199.192019 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.097262 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.097262 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 5061 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 5061 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 5061 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 5061 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 5061 # number of overall hits -system.cpu.icache.overall_hits::total 5061 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 484 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 484 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 484 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 484 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 484 # number of overall misses -system.cpu.icache.overall_misses::total 484 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16465500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16465500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16465500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16465500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16465500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16465500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5545 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5545 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5545 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5545 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5545 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5545 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.087286 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.087286 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.087286 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.087286 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.087286 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.087286 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34019.628099 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34019.628099 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34019.628099 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34019.628099 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34019.628099 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34019.628099 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 200.987114 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.098138 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.098138 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 5096 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 5096 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 5096 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 5096 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 5096 # number of overall hits +system.cpu.icache.overall_hits::total 5096 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 465 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 465 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 465 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 465 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 465 # number of overall misses +system.cpu.icache.overall_misses::total 465 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14626000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14626000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14626000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14626000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14626000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14626000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5561 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5561 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5561 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5561 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5561 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5561 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.083618 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.083618 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.083618 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.083618 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.083618 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.083618 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31453.763441 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 31453.763441 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 31453.763441 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 31453.763441 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 31453.763441 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 31453.763441 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -342,98 +500,98 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 147 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 147 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 147 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 147 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 147 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 147 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 337 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 337 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 337 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 337 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 337 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 337 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12143500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12143500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12143500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12143500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12143500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12143500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.060775 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.060775 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.060775 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.060775 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.060775 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.060775 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36034.124629 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36034.124629 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36034.124629 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36034.124629 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36034.124629 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36034.124629 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 126 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 126 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 126 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 126 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 126 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 126 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 339 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 339 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 339 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 339 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 339 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 339 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11056500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11056500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11056500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11056500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11056500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11056500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.060960 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.060960 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.060960 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.060960 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.060960 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.060960 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32615.044248 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32615.044248 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32615.044248 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 32615.044248 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32615.044248 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 32615.044248 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 103.051665 # Cycle average of tags in use -system.cpu.dcache.total_refs 4061 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 102.726852 # Cycle average of tags in use +system.cpu.dcache.total_refs 4058 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 27.815068 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 27.794521 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 103.051665 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025159 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025159 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 3022 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3022 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits +system.cpu.dcache.occ_blocks::cpu.data 102.726852 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025080 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025080 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 3017 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3017 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1035 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1035 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 4055 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4055 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4055 # number of overall hits -system.cpu.dcache.overall_hits::total 4055 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 121 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 121 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 530 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 530 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 530 # number of overall misses -system.cpu.dcache.overall_misses::total 530 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4244000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4244000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 15546000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15546000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19790000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19790000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19790000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19790000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3143 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3143 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 4052 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4052 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4052 # number of overall hits +system.cpu.dcache.overall_hits::total 4052 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 128 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 128 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 407 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 407 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 535 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 535 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 535 # number of overall misses +system.cpu.dcache.overall_misses::total 535 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5512500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5512500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14390000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14390000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19902500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19902500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19902500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19902500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3145 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3145 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 4585 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 4585 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 4585 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 4585 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.038498 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.038498 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.115594 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.115594 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.115594 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.115594 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35074.380165 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 35074.380165 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38009.779951 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38009.779951 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37339.622642 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37339.622642 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37339.622642 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37339.622642 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 4587 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 4587 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 4587 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 4587 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040700 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040700 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.282247 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.282247 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.116634 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.116634 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.116634 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.116634 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43066.406250 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 43066.406250 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35356.265356 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35356.265356 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37200.934579 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37200.934579 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37200.934579 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37200.934579 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -442,14 +600,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 384 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 384 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 384 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 384 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 324 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 324 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 389 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 389 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 389 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 389 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 63 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses @@ -458,103 +616,103 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146 system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2501000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2501000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3322000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3322000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5823000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5823000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5823000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5823000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020045 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020045 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3018500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3018500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3172000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3172000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6190500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6190500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6190500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6190500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020032 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020032 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031843 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.031843 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031843 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.031843 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39698.412698 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39698.412698 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40024.096386 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40024.096386 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 39883.561644 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 39883.561644 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 39883.561644 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 39883.561644 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031829 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.031829 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031829 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.031829 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47912.698413 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47912.698413 # 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Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.005025 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.005000 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 198.449350 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 36.125184 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.006056 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001102 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.007159 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 200.252174 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 36.004069 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.006111 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001099 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.007210 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 335 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 337 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 63 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 398 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 400 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # 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number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 63 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 400 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 402 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 337 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 339 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 483 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 337 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 485 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 339 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 483 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.994065 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 485 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.994100 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.995000 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.995025 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994065 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994100 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.995859 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994065 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.995876 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994100 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.995859 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35237.313433 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38690.476190 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 35783.919598 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39012.048193 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39012.048193 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35237.313433 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38873.287671 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 36340.956341 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35237.313433 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38873.287671 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 36340.956341 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.995876 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 31796.735905 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 46904.761905 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34176.250000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 37204.819277 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 37204.819277 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 31796.735905 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41390.410959 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34696.687371 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 31796.735905 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41390.410959 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34696.687371 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -563,50 +721,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 335 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 337 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 398 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 400 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 335 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 337 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 481 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 483 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 337 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 481 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10738000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2244000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12982000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2981500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2981500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10738000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5225500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15963500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10738000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5225500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15963500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 483 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9509513 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2743056 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12252569 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2822546 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2822546 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9509513 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5565602 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15075115 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9509513 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5565602 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15075115 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994100 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995000 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995025 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994100 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.995859 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995876 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994100 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.995859 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32053.731343 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35619.047619 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32618.090452 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35921.686747 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35921.686747 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32053.731343 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35791.095890 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33188.149688 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32053.731343 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35791.095890 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33188.149688 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995876 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28218.139466 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43540.571429 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 30631.422500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 34006.578313 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 34006.578313 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28218.139466 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38120.561644 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31211.418219 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28218.139466 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38120.561644 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31211.418219 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index ff9862a27..c68736462 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,953 +1,1112 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000110 # Number of seconds simulated -sim_ticks 109894000 # Number of ticks simulated -final_tick 109894000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000109 # Number of seconds simulated +sim_ticks 108678000 # Number of ticks simulated +final_tick 108678000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 161995 # Simulator instruction rate (inst/s) -host_op_rate 161994 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16590549 # Simulator tick rate (ticks/s) -host_mem_usage 228988 # Number of bytes of host memory used -host_seconds 6.62 # Real time elapsed on the host -sim_insts 1073027 # Number of instructions simulated -sim_ops 1073027 # Number of ops (including micro ops) simulated +host_inst_rate 97735 # Simulator instruction rate (inst/s) +host_op_rate 97735 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9914053 # Simulator tick rate (ticks/s) +host_mem_usage 237564 # Number of bytes of host memory used +host_seconds 10.96 # Real time elapsed on the host +sim_insts 1071369 # Number of instructions simulated +sim_ops 1071369 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 23040 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 5632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 5504 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 384 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::total 42880 # Number of bytes read from this memory +system.physmem.bytes_read::total 42752 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 23040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 5632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 256 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 29184 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 5504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 29056 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 360 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 88 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 86 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 6 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::total 670 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 209656578 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 97839736 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 51249386 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 11647588 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 2329518 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7570932 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 2329518 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7570932 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 390194187 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 209656578 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 51249386 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 2329518 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 2329518 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 265564999 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 209656578 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 97839736 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 51249386 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 11647588 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 2329518 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7570932 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 2329518 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7570932 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 390194187 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 668 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 212002429 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 98934467 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 50645025 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 11777913 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 3533374 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7655643 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 1177791 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7655643 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 393382285 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 212002429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 50645025 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 3533374 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 1177791 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 267358619 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 212002429 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 98934467 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 50645025 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 11777913 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 3533374 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7655643 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 1177791 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7655643 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 393382285 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 669 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 993 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 42752 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 42752 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 76 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 50 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 71 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 36 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 31 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 23 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 21 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 54 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 56 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 73 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 61 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 5 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 21 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 79 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 44 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 108650000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 669 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 76 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 401 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 192 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 3390669 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 18414669 # Sum of mem lat for all requests +system.physmem.totBusLat 2676000 # Total cycles spent in databus access +system.physmem.totBankLat 12348000 # Total cycles spent in bank access +system.physmem.avgQLat 5068.26 # Average queueing delay per request +system.physmem.avgBankLat 18457.40 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 27525.66 # Average memory access latency +system.physmem.avgRdBW 393.38 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 393.38 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 2.46 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.17 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 513 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 76.68 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 162406.58 # Average gap between requests system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 219789 # number of cpu cycles simulated +system.cpu0.numCycles 217357 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 85747 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 83485 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 1265 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 83551 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 81101 # Number of BTB hits +system.cpu0.BPredUnit.lookups 85486 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 83146 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 1297 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 83094 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 80730 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 507 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.usedRAS 510 # Number of times the RAS was used to get a target. system.cpu0.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 17217 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 509162 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 85747 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 81608 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 167267 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3854 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 13783 # Number of cycles fetch has spent blocked +system.cpu0.fetch.icacheStallCycles 17254 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 507547 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 85486 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 81240 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 166653 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3954 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 12694 # Number of cycles fetch has spent blocked system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1302 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 6029 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 502 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 202015 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.520417 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.209670 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.PendingTrapStallCycles 1571 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 6105 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 500 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 200686 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.529060 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.210670 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 34748 17.20% 17.20% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 82895 41.03% 58.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 589 0.29% 58.53% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 956 0.47% 59.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 519 0.26% 59.26% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 78871 39.04% 98.30% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 675 0.33% 98.63% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 356 0.18% 98.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2406 1.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 34033 16.96% 16.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 82572 41.14% 58.10% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 593 0.30% 58.40% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 970 0.48% 58.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 529 0.26% 59.15% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 78464 39.10% 98.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 697 0.35% 98.59% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 363 0.18% 98.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2465 1.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 202015 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.390133 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.316595 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 17805 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 15234 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 166234 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 301 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2441 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 506087 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 2441 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18480 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 1523 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 13039 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 165885 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 647 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 502881 # Number of instructions processed by rename -system.cpu0.rename.LSQFullEvents 252 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 343651 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 1003098 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 1003098 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 330631 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13020 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 904 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 932 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 3938 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 161147 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 81377 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 78673 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 78441 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 420405 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 949 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 417702 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 122 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10651 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 9804 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 390 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 202015 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.067678 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.086169 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 200686 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.393298 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.335085 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 18097 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 14161 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 165636 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 283 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2509 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 504485 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 2509 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18775 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 695 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12879 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 165279 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 549 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 501228 # Number of instructions processed by rename +system.cpu0.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 155 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 342771 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 999720 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 999720 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 329211 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13560 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 922 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 944 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 3899 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 160553 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 81037 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 78269 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 78067 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 419118 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 951 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 416267 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 155 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 11107 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 10171 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 392 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 200686 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.074220 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.084012 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 33785 16.72% 16.72% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5274 2.61% 19.33% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 80485 39.84% 59.18% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 79928 39.57% 98.74% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1527 0.76% 99.50% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 645 0.32% 99.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 270 0.13% 99.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 87 0.04% 99.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 14 0.01% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 33200 16.54% 16.54% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5091 2.54% 19.08% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 80178 39.95% 59.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 79595 39.66% 98.69% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1563 0.78% 99.47% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 681 0.34% 99.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 279 0.14% 99.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 88 0.04% 99.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 11 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 202015 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 200686 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 46 19.74% 19.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 19.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 19.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 19.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 19.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 19.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 19.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 19.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 19.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 19.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 19.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 19.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 19.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 19.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 19.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 19.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 19.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 19.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 19.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 19.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 19.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 19.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 19.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 19.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 19.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 19.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 19.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 19.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 73 31.33% 51.07% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 114 48.93% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 45 20.36% 20.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 20.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 20.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 20.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 20.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 20.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 20.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 20.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 20.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 20.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 20.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 20.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 20.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 20.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 20.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 20.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 20.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 20.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 20.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 20.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 20.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 20.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 20.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 20.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 20.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 20.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 20.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 20.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 20.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 64 28.96% 49.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 112 50.68% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 176241 42.19% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 160662 38.46% 80.66% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 80799 19.34% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 175769 42.23% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 160047 38.45% 80.67% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 80451 19.33% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 417702 # Type of FU issued -system.cpu0.iq.rate 1.900468 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 233 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000558 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1037774 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 432063 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 415867 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 416267 # Type of FU issued +system.cpu0.iq.rate 1.915130 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 221 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000531 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1033596 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 431231 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 414361 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 417935 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 416488 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 78173 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 77814 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2242 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2358 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 58 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1418 # Number of stores squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 55 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1433 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 20 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2441 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1114 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 500579 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 311 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 161147 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 81377 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 838 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 51 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 2509 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 439 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 34 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 498940 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 337 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 160553 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 81037 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 840 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 58 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 383 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1089 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1472 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 416616 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 160343 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1086 # Number of squashed instructions skipped in execute +system.cpu0.iew.memOrderViolationEvents 55 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 377 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1128 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1505 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 415155 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 159727 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1112 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 79225 # number of nop insts executed -system.cpu0.iew.exec_refs 241004 # number of memory reference insts executed -system.cpu0.iew.exec_branches 82800 # Number of branches executed -system.cpu0.iew.exec_stores 80661 # Number of stores executed -system.cpu0.iew.exec_rate 1.895527 # Inst execution rate -system.cpu0.iew.wb_sent 416200 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 415867 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 246464 # num instructions producing a value -system.cpu0.iew.wb_consumers 248856 # num instructions consuming a value +system.cpu0.iew.exec_nop 78871 # number of nop insts executed +system.cpu0.iew.exec_refs 240043 # number of memory reference insts executed +system.cpu0.iew.exec_branches 82509 # Number of branches executed +system.cpu0.iew.exec_stores 80316 # Number of stores executed +system.cpu0.iew.exec_rate 1.910014 # Inst execution rate +system.cpu0.iew.wb_sent 414703 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 414361 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 245547 # num instructions producing a value +system.cpu0.iew.wb_consumers 248019 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.892119 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.990388 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.906361 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.990033 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 12251 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 12749 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1265 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 199591 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.446493 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.132962 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1297 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 198194 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.452991 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.132633 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 34293 17.18% 17.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 82677 41.42% 58.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2432 1.22% 59.82% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 705 0.35% 60.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 565 0.28% 60.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 77961 39.06% 99.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 418 0.21% 99.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 251 0.13% 99.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 289 0.14% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 33728 17.02% 17.02% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 82160 41.45% 58.47% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2430 1.23% 59.70% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 731 0.37% 60.07% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 570 0.29% 60.35% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 77594 39.15% 99.51% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 452 0.23% 99.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 239 0.12% 99.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 290 0.15% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 199591 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 488298 # Number of instructions committed -system.cpu0.commit.committedOps 488298 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 198194 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 486168 # Number of instructions committed +system.cpu0.commit.committedOps 486168 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 238864 # Number of memory references committed -system.cpu0.commit.loads 158905 # Number of loads committed +system.cpu0.commit.refs 237799 # Number of memory references committed +system.cpu0.commit.loads 158195 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 81846 # Number of branches committed +system.cpu0.commit.branches 81491 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 328962 # Number of committed integer instructions. +system.cpu0.commit.int_insts 327542 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 289 # number cycles where commit BW limit reached +system.cpu0.commit.bw_lim_events 290 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 698690 # The number of ROB reads -system.cpu0.rob.rob_writes 1003556 # The number of ROB writes -system.cpu0.timesIdled 327 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 17774 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 409636 # Number of Instructions Simulated -system.cpu0.committedOps 409636 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 409636 # Number of Instructions Simulated -system.cpu0.cpi 0.536547 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.536547 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.863769 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.863769 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 745424 # number of integer regfile reads -system.cpu0.int_regfile_writes 335847 # number of integer regfile writes +system.cpu0.rob.rob_reads 695660 # The number of ROB reads +system.cpu0.rob.rob_writes 1000360 # The number of ROB writes +system.cpu0.timesIdled 319 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 16671 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 407861 # Number of Instructions Simulated +system.cpu0.committedOps 407861 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 407861 # Number of Instructions Simulated +system.cpu0.cpi 0.532919 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.532919 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.876457 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.876457 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 742624 # number of integer regfile reads +system.cpu0.int_regfile_writes 334702 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 242810 # number of misc regfile reads +system.cpu0.misc_regfile_reads 241901 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.icache.replacements 299 # number of replacements -system.cpu0.icache.tagsinuse 247.576197 # Cycle average of tags in use -system.cpu0.icache.total_refs 5285 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 591 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 8.942470 # Average number of references to valid blocks. +system.cpu0.icache.replacements 305 # number of replacements +system.cpu0.icache.tagsinuse 247.227558 # Cycle average of tags in use +system.cpu0.icache.total_refs 5357 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 596 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 8.988255 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 247.576197 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.483547 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.483547 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5285 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5285 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5285 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5285 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5285 # number of overall hits -system.cpu0.icache.overall_hits::total 5285 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 744 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 744 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 744 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 744 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 744 # number of overall misses -system.cpu0.icache.overall_misses::total 744 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 28183000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 28183000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 28183000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 28183000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 28183000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 28183000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6029 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6029 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6029 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6029 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6029 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6029 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.123404 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.123404 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.123404 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.123404 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.123404 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.123404 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 37880.376344 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 37880.376344 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 37880.376344 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 37880.376344 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 37880.376344 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 37880.376344 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 53 # number of cycles access was blocked +system.cpu0.icache.occ_blocks::cpu0.inst 247.227558 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.482866 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.482866 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5357 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5357 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5357 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5357 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5357 # number of overall hits +system.cpu0.icache.overall_hits::total 5357 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 748 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 748 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 748 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 748 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 748 # number of overall misses +system.cpu0.icache.overall_misses::total 748 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 25787000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 25787000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 25787000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 25787000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 25787000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 25787000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6105 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6105 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6105 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 6105 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6105 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 6105 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.122523 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.122523 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.122523 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.122523 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.122523 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.122523 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 34474.598930 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 34474.598930 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 34474.598930 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 34474.598930 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 34474.598930 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 34474.598930 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.500000 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 152 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 152 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 152 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 152 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 152 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 152 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 592 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 592 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 592 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 592 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 592 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 592 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 22043000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 22043000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 22043000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 22043000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 22043000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 22043000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.098192 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.098192 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.098192 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.098192 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.098192 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.098192 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37234.797297 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37234.797297 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37234.797297 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 37234.797297 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37234.797297 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 37234.797297 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 151 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 151 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 151 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 151 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 151 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 151 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 597 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 597 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 597 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 597 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 597 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 597 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 20662500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 20662500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 20662500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 20662500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 20662500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 20662500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.097789 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.097789 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.097789 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.097789 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.097789 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.097789 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 34610.552764 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 34610.552764 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 34610.552764 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 34610.552764 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 34610.552764 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 34610.552764 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.tagsinuse 144.284283 # Cycle average of tags in use -system.cpu0.dcache.total_refs 160925 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 144.093465 # Cycle average of tags in use +system.cpu0.dcache.total_refs 160308 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 946.617647 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 942.988235 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 144.284283 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.281805 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.281805 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 81643 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 81643 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 79364 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 79364 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 161007 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 161007 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 161007 # number of overall hits -system.cpu0.dcache.overall_hits::total 161007 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 465 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 465 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 553 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 553 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1018 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1018 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1018 # number of overall misses -system.cpu0.dcache.overall_misses::total 1018 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 14129000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 14129000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 26395982 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 26395982 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 370000 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 370000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 40524982 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 40524982 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 40524982 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 40524982 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 82108 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 82108 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 79917 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 79917 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.occ_blocks::cpu0.data 144.093465 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.281433 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.281433 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 81376 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 81376 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 79021 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 79021 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 22 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 22 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 160397 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 160397 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 160397 # number of overall hits +system.cpu0.dcache.overall_hits::total 160397 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 473 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 473 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 541 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 541 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses::cpu0.data 20 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 20 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1014 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1014 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1014 # number of overall misses +system.cpu0.dcache.overall_misses::total 1014 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 11124000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11124000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 22939498 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 22939498 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 377000 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 377000 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 34063498 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 34063498 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 34063498 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 34063498 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 81849 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 81849 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 79562 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 79562 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 162025 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 162025 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 162025 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 162025 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005663 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.005663 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006920 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.006920 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006283 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006283 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006283 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006283 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30384.946237 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 30384.946237 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 47732.336347 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 47732.336347 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 17619.047619 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 17619.047619 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39808.430255 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 39808.430255 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39808.430255 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 39808.430255 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 319 # number of cycles access was blocked +system.cpu0.dcache.demand_accesses::cpu0.data 161411 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 161411 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 161411 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 161411 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005779 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.005779 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006800 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.006800 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.476190 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.476190 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006282 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006282 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006282 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006282 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23517.970402 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 23517.970402 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42402.029575 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 42402.029575 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 18850 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 18850 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33593.193294 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33593.193294 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33593.193294 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33593.193294 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 196 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 24 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 14 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.291667 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 276 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 276 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 381 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 381 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 657 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 657 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 657 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 657 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 189 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 172 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 172 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 361 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 361 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 361 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5343500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5343500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6330000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6330000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 328000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 328000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11673500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11673500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11673500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11673500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002302 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002302 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002152 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002152 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002228 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002228 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002228 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002228 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28272.486772 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28272.486772 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36802.325581 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36802.325581 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 15619.047619 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 15619.047619 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32336.565097 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32336.565097 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32336.565097 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32336.565097 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 282 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 282 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 652 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 652 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 652 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 652 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 191 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 191 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 171 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 171 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 20 # number of SwapReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::total 20 # number of SwapReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4857000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4857000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5583500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5583500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 337000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 337000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10440500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10440500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10440500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10440500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002334 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002334 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002149 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002149 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.476190 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.476190 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002243 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002243 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002243 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002243 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25429.319372 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25429.319372 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32652.046784 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32652.046784 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 16850 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 16850 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28841.160221 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28841.160221 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28841.160221 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28841.160221 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 184127 # number of cpu cycles simulated +system.cpu1.numCycles 181799 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 48566 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 45425 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 1525 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 41634 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 40784 # Number of BTB hits +system.cpu1.BPredUnit.lookups 59567 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 56529 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 1500 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 52860 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 52019 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 857 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.usedRAS 823 # Number of times the RAS was used to get a target. system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 32363 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 265611 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 48566 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 41641 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 96301 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4375 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 40077 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.NoActiveThreadStallCycles 6455 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 1055 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 23564 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 345 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 179027 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.483637 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.076927 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 25837 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 338154 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 59567 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 52842 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 115388 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4298 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 25769 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.NoActiveThreadStallCycles 6220 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.PendingTrapStallCycles 1046 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 17180 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 322 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 176992 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.910561 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.213171 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 82726 46.21% 46.21% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 49826 27.83% 74.04% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 7772 4.34% 78.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3158 1.76% 80.15% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 709 0.40% 80.54% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 29207 16.31% 96.86% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1125 0.63% 97.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 886 0.49% 97.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3618 2.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 61604 34.81% 34.81% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 57789 32.65% 67.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 4656 2.63% 70.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3206 1.81% 71.90% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 672 0.38% 72.28% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 43499 24.58% 96.86% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1205 0.68% 97.54% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 866 0.49% 98.03% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3495 1.97% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 179027 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.263764 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.442542 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 39330 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 35122 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 88807 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 6541 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2772 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 261671 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 2772 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 40116 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 20114 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 14157 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 82544 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 12869 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 259082 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 41 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 180494 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 488461 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 488461 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 165372 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 15122 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1240 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1383 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 15783 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 71004 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 32715 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 34344 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 27479 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 212625 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 7991 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 216005 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 69 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 12464 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 11017 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 740 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 179027 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.206550 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.298788 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 176992 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.327653 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.860043 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 29997 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 23620 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 110723 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 3705 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2727 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 334194 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2727 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 30767 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 10715 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 12086 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 107285 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 7192 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 331783 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 53 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 234003 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 646246 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 646246 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 218850 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 15153 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1212 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1340 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 9848 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 96301 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 46898 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 45474 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 41683 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 277198 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 4877 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 277583 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 147 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 12330 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 11288 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 591 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 176992 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.568336 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.306945 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 80193 44.79% 44.79% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 27393 15.30% 60.09% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 32961 18.41% 78.51% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 33539 18.73% 97.24% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3241 1.81% 99.05% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1264 0.71% 99.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 324 0.18% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 51 0.03% 99.97% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 58949 33.31% 33.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 18466 10.43% 43.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 46965 26.54% 70.27% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 47589 26.89% 97.16% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3312 1.87% 99.03% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1274 0.72% 99.75% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 318 0.18% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 58 0.03% 99.97% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 179027 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 176992 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 20 6.78% 6.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 6.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 65 22.03% 28.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 210 71.19% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 20 6.43% 6.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 6.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 81 26.05% 32.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 210 67.52% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 107139 49.60% 49.60% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.60% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.60% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 76812 35.56% 85.16% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 32054 14.84% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 132190 47.62% 47.62% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 99212 35.74% 83.36% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 46181 16.64% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 216005 # Type of FU issued -system.cpu1.iq.rate 1.173131 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 295 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001366 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 611401 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 233118 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 214044 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 277583 # Type of FU issued +system.cpu1.iq.rate 1.526868 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 311 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001120 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 732616 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 294445 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 275571 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 216300 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 277894 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 27354 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 41481 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2609 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2645 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1525 # Number of stores squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1604 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2772 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 1710 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 53 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 255983 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 380 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 71004 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 32715 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1159 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 52 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 2727 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 837 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 60 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 328541 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 420 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 96301 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 46898 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1140 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 60 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 38 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 484 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 1213 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1697 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 214708 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 69981 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1297 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 40 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 494 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 1175 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1669 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 276246 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 95320 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1337 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 35367 # number of nop insts executed -system.cpu1.iew.exec_refs 101954 # number of memory reference insts executed -system.cpu1.iew.exec_branches 44806 # Number of branches executed -system.cpu1.iew.exec_stores 31973 # Number of stores executed -system.cpu1.iew.exec_rate 1.166086 # Inst execution rate -system.cpu1.iew.wb_sent 214321 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 214044 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 118861 # num instructions producing a value -system.cpu1.iew.wb_consumers 123754 # num instructions consuming a value +system.cpu1.iew.exec_nop 46466 # number of nop insts executed +system.cpu1.iew.exec_refs 141403 # number of memory reference insts executed +system.cpu1.iew.exec_branches 55896 # Number of branches executed +system.cpu1.iew.exec_stores 46083 # Number of stores executed +system.cpu1.iew.exec_rate 1.519513 # Inst execution rate +system.cpu1.iew.wb_sent 275857 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 275571 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 158251 # num instructions producing a value +system.cpu1.iew.wb_consumers 163120 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.162480 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.960462 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.515800 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.970151 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 14492 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 7251 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1525 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 169801 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.422188 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.937267 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 14237 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 4286 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1500 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 168046 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.870327 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.085151 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 80979 47.69% 47.69% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 42780 25.19% 72.88% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6215 3.66% 76.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 8147 4.80% 81.34% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1520 0.90% 82.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 27830 16.39% 98.63% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 515 0.30% 98.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 1002 0.59% 99.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 813 0.48% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 57008 33.92% 33.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 53849 32.04% 65.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6186 3.68% 69.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 5193 3.09% 72.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1537 0.91% 73.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 41906 24.94% 98.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 558 0.33% 98.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 997 0.59% 99.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 812 0.48% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 169801 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 241489 # Number of instructions committed -system.cpu1.commit.committedOps 241489 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 168046 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 314301 # Number of instructions committed +system.cpu1.commit.committedOps 314301 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 99585 # Number of memory references committed -system.cpu1.commit.loads 68395 # Number of loads committed -system.cpu1.commit.membars 6536 # Number of memory barriers committed -system.cpu1.commit.branches 43685 # Number of branches committed +system.cpu1.commit.refs 138950 # Number of memory references committed +system.cpu1.commit.loads 93656 # Number of loads committed +system.cpu1.commit.membars 3574 # Number of memory barriers committed +system.cpu1.commit.branches 54833 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 165393 # Number of committed integer instructions. +system.cpu1.commit.int_insts 215906 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 813 # number cycles where commit BW limit reached +system.cpu1.commit.bw_lim_events 812 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 424382 # The number of ROB reads -system.cpu1.rob.rob_writes 514748 # The number of ROB writes -system.cpu1.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 5100 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 35660 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 200479 # Number of Instructions Simulated -system.cpu1.committedOps 200479 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 200479 # Number of Instructions Simulated -system.cpu1.cpi 0.918435 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.918435 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.088808 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.088808 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 365766 # number of integer regfile reads -system.cpu1.int_regfile_writes 171568 # number of integer regfile writes +system.cpu1.rob.rob_reads 495185 # The number of ROB reads +system.cpu1.rob.rob_writes 659817 # The number of ROB writes +system.cpu1.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 4807 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 35556 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 265102 # Number of Instructions Simulated +system.cpu1.committedOps 265102 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 265102 # Number of Instructions Simulated +system.cpu1.cpi 0.685770 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.685770 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.458215 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.458215 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 483798 # number of integer regfile reads +system.cpu1.int_regfile_writes 224930 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 103658 # number of misc regfile reads +system.cpu1.misc_regfile_reads 143054 # number of misc regfile reads system.cpu1.misc_regfile_writes 646 # number of misc regfile writes system.cpu1.icache.replacements 321 # number of replacements -system.cpu1.icache.tagsinuse 92.890627 # Cycle average of tags in use -system.cpu1.icache.total_refs 23041 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 438 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 52.605023 # Average number of references to valid blocks. +system.cpu1.icache.tagsinuse 91.372145 # Cycle average of tags in use +system.cpu1.icache.total_refs 16670 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 436 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 38.233945 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 92.890627 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.181427 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.181427 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 23041 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 23041 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 23041 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 23041 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 23041 # number of overall hits -system.cpu1.icache.overall_hits::total 23041 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 523 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 523 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 523 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 523 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 523 # number of overall misses -system.cpu1.icache.overall_misses::total 523 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10934000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 10934000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 10934000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 10934000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 10934000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 10934000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 23564 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 23564 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 23564 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 23564 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 23564 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 23564 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022195 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.022195 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022195 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.022195 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022195 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.022195 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20906.309751 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 20906.309751 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20906.309751 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 20906.309751 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20906.309751 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 20906.309751 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 66 # number of cycles access was blocked +system.cpu1.icache.occ_blocks::cpu1.inst 91.372145 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.178461 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.178461 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 16670 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 16670 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 16670 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 16670 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 16670 # number of overall hits +system.cpu1.icache.overall_hits::total 16670 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 510 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 510 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 510 # 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number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 99050 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 99050 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 99050 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 99050 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.007711 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.007711 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003206 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.003206 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.818182 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.818182 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005654 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.005654 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005654 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.005654 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14520.481928 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14520.481928 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21772.413793 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 21772.413793 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 10287.037037 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 10287.037037 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16398.214286 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16398.214286 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16398.214286 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16398.214286 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -956,364 +1115,364 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 238 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 238 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 257 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 257 # number of ReadReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 37 # number of WriteReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::total 37 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 275 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 275 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 275 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 275 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 160 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 52 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2446500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2446500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1653500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1653500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 904000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 904000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4100000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4100000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4100000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4100000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003755 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003755 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003310 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003310 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.753623 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.753623 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003567 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.003567 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003567 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.003567 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15290.625000 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15290.625000 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16053.398058 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16053.398058 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 17384.615385 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 17384.615385 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15589.353612 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15589.353612 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15589.353612 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15589.353612 # average overall mshr miss latency +system.cpu1.dcache.demand_mshr_hits::cpu1.data 294 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 294 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 294 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 294 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 158 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 158 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 54 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 266 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 266 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1540500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1540500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1377000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1377000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 447500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 447500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2917500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2917500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2917500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2917500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002936 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002936 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002388 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002388 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.818182 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.818182 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002686 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.002686 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002686 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.002686 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 9750 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 9750 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12750 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12750 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 8287.037037 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 8287.037037 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 10968.045113 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 10968.045113 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 10968.045113 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 10968.045113 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 183836 # number of cpu cycles simulated +system.cpu2.numCycles 181474 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.BPredUnit.lookups 53962 # Number of BP lookups -system.cpu2.BPredUnit.condPredicted 50907 # Number of conditional branches predicted -system.cpu2.BPredUnit.condIncorrect 1502 # Number of conditional branches incorrect -system.cpu2.BPredUnit.BTBLookups 47302 # Number of BTB lookups -system.cpu2.BPredUnit.BTBHits 46374 # Number of BTB hits +system.cpu2.BPredUnit.lookups 55930 # Number of BP lookups +system.cpu2.BPredUnit.condPredicted 52799 # Number of conditional branches predicted +system.cpu2.BPredUnit.condIncorrect 1548 # Number of conditional branches incorrect +system.cpu2.BPredUnit.BTBLookups 49143 # Number of BTB lookups +system.cpu2.BPredUnit.BTBHits 48122 # Number of BTB hits system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.BPredUnit.usedRAS 814 # Number of times the RAS was used to get a target. +system.cpu2.BPredUnit.usedRAS 857 # Number of times the RAS was used to get a target. system.cpu2.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu2.fetch.icacheStallCycles 29545 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 300535 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 53962 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 47188 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 106111 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 4305 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 35885 # Number of cycles fetch has spent blocked +system.cpu2.fetch.icacheStallCycles 28647 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 313051 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 55930 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 48979 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 109339 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 4440 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 31939 # Number of cycles fetch has spent blocked system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.NoActiveThreadStallCycles 6446 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 1035 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 21240 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 294 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 181756 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.653508 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.139245 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.NoActiveThreadStallCycles 6238 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.PendingTrapStallCycles 1022 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 20302 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 327 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 180005 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.739124 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.167787 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 75645 41.62% 41.62% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 54116 29.77% 71.39% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 6682 3.68% 75.07% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3224 1.77% 76.84% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 665 0.37% 77.21% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 35775 19.68% 96.89% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1232 0.68% 97.57% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 880 0.48% 98.05% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3537 1.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 70666 39.26% 39.26% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 55453 30.81% 70.06% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 6160 3.42% 73.49% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3207 1.78% 75.27% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 684 0.38% 75.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 38160 21.20% 96.85% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1206 0.67% 97.52% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 867 0.48% 98.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3602 2.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 181756 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.293533 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.634799 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 35633 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 31817 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 99530 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 5601 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2729 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 296271 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2729 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 36405 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 17349 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 13658 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 94174 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 10995 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 293755 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 37 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 205188 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 562117 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 562117 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 190142 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 15046 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1228 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1359 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 13734 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 82915 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 39246 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 39773 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 34011 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 242760 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 6943 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 245051 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 73 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 12414 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 11373 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 664 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 181756 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.348242 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.310708 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 180005 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.308198 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.725046 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 34354 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 28279 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 103112 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 5207 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2815 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 308841 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2815 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 35130 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 15148 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 12314 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 98150 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 10210 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 306064 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 44 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 214486 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 588858 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 588858 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 198873 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 15613 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1249 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1373 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 13264 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 87101 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 41559 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 41593 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 36327 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 253620 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 6426 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 255375 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 71 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 12537 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 11608 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 622 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 180005 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.418711 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.312032 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 73115 40.23% 40.23% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 24368 13.41% 53.63% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 39333 21.64% 75.27% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 39995 22.00% 97.28% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3268 1.80% 99.08% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1268 0.70% 99.77% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 298 0.16% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 56 0.03% 99.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 55 0.03% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 68069 37.82% 37.82% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 23048 12.80% 50.62% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 41620 23.12% 73.74% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 42277 23.49% 97.23% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3294 1.83% 99.06% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1277 0.71% 99.77% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 306 0.17% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 181756 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 180005 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 20 6.83% 6.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 6.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 63 21.50% 28.33% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 210 71.67% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 21 7.02% 7.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 7.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 7.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 7.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 7.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 7.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 7.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 7.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 7.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 7.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 7.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 7.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 7.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 7.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 7.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 7.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 7.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 7.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 7.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 7.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 7.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 7.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 7.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 7.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 7.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 7.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 7.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 7.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 68 22.74% 29.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 210 70.23% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 118754 48.46% 48.46% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.46% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.46% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.46% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.46% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.46% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.46% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.46% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.46% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 87780 35.82% 84.28% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 38517 15.72% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 123049 48.18% 48.18% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.18% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.18% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.18% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.18% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.18% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.18% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.18% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.18% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.18% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.18% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.18% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.18% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.18% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.18% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.18% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.18% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.18% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.18% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.18% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.18% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.18% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.18% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.18% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.18% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.18% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.18% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.18% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.18% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 91506 35.83% 84.02% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 40820 15.98% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 245051 # Type of FU issued -system.cpu2.iq.rate 1.332987 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 293 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001196 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 672224 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 262158 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 243059 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 255375 # Type of FU issued +system.cpu2.iq.rate 1.407226 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 299 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001171 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 691125 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 272626 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 253322 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 245344 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 255674 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 33799 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 36105 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2624 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 41 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1621 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2679 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1636 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2729 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 1758 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 40 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 290501 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 383 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 82915 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 39246 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1163 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2815 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 752 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 48 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 302670 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 388 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 87101 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 41559 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1159 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 48 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 41 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 513 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1158 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1671 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 243729 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 81914 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1322 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 43 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 509 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 1214 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1723 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 254008 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 86102 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1367 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 40798 # number of nop insts executed -system.cpu2.iew.exec_refs 120340 # number of memory reference insts executed -system.cpu2.iew.exec_branches 50195 # Number of branches executed -system.cpu2.iew.exec_stores 38426 # Number of stores executed -system.cpu2.iew.exec_rate 1.325796 # Inst execution rate -system.cpu2.iew.wb_sent 243343 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 243059 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 137174 # num instructions producing a value -system.cpu2.iew.wb_consumers 142058 # num instructions consuming a value +system.cpu2.iew.exec_nop 42624 # number of nop insts executed +system.cpu2.iew.exec_refs 126828 # number of memory reference insts executed +system.cpu2.iew.exec_branches 52054 # Number of branches executed +system.cpu2.iew.exec_stores 40726 # Number of stores executed +system.cpu2.iew.exec_rate 1.399694 # Inst execution rate +system.cpu2.iew.wb_sent 253605 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 253322 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 143679 # num instructions producing a value +system.cpu2.iew.wb_consumers 148564 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.322151 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.965620 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.395913 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.967119 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 14265 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 6279 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1502 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 172582 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.600480 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.009191 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 14523 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 5804 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1548 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 170953 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.685416 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.035354 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 72897 42.24% 42.24% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 48196 27.93% 70.17% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 6187 3.58% 73.75% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 7136 4.13% 77.89% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1545 0.90% 78.78% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 34295 19.87% 98.65% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 518 0.30% 98.95% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 991 0.57% 99.53% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 817 0.47% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 67602 39.54% 39.54% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 50009 29.25% 68.80% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 6225 3.64% 72.44% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 6684 3.91% 76.35% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1541 0.90% 77.25% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 36526 21.37% 98.62% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 553 0.32% 98.94% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 1000 0.58% 99.52% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 813 0.48% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 172582 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 276214 # Number of instructions committed -system.cpu2.commit.committedOps 276214 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 170953 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 288127 # Number of instructions committed +system.cpu2.commit.committedOps 288127 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 117916 # Number of memory references committed -system.cpu2.commit.loads 80291 # Number of loads committed -system.cpu2.commit.membars 5562 # Number of memory barriers committed -system.cpu2.commit.branches 49152 # Number of branches committed +system.cpu2.commit.refs 124345 # Number of memory references committed +system.cpu2.commit.loads 84422 # Number of loads committed +system.cpu2.commit.membars 5089 # Number of memory barriers committed +system.cpu2.commit.branches 50979 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 189186 # Number of committed integer instructions. +system.cpu2.commit.int_insts 197443 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 817 # number cycles where commit BW limit reached +system.cpu2.commit.bw_lim_events 813 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 461657 # The number of ROB reads -system.cpu2.rob.rob_writes 583698 # The number of ROB writes -system.cpu2.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 2080 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 35951 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 230713 # Number of Instructions Simulated -system.cpu2.committedOps 230713 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 230713 # Number of Instructions Simulated -system.cpu2.cpi 0.796817 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.796817 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.254994 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.254994 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 420543 # number of integer regfile reads -system.cpu2.int_regfile_writes 196056 # number of integer regfile writes +system.cpu2.rob.rob_reads 472203 # The number of ROB reads +system.cpu2.rob.rob_writes 608127 # The number of ROB writes +system.cpu2.timesIdled 210 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1469 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 35881 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 241270 # Number of Instructions Simulated +system.cpu2.committedOps 241270 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 241270 # Number of Instructions Simulated +system.cpu2.cpi 0.752161 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.752161 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.329502 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.329502 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 440107 # number of integer regfile reads +system.cpu2.int_regfile_writes 204983 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 121964 # number of misc regfile reads +system.cpu2.misc_regfile_reads 128465 # number of misc regfile reads system.cpu2.misc_regfile_writes 646 # number of misc regfile writes system.cpu2.icache.replacements 323 # number of replacements -system.cpu2.icache.tagsinuse 86.140818 # Cycle average of tags in use -system.cpu2.icache.total_refs 20746 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 436 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 47.582569 # Average number of references to valid blocks. +system.cpu2.icache.tagsinuse 83.164978 # Cycle average of tags in use +system.cpu2.icache.total_refs 19795 # Total number of references to valid blocks. +system.cpu2.icache.sampled_refs 438 # Sample count of references to valid blocks. +system.cpu2.icache.avg_refs 45.194064 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 86.140818 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.168244 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.168244 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 20746 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 20746 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 20746 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 20746 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 20746 # number of overall hits -system.cpu2.icache.overall_hits::total 20746 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 494 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 494 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 494 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 494 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 494 # number of overall misses -system.cpu2.icache.overall_misses::total 494 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6486500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 6486500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 6486500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 6486500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 6486500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 6486500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 21240 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 21240 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 21240 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 21240 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 21240 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 21240 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.023258 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.023258 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.023258 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.023258 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.023258 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.023258 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13130.566802 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 13130.566802 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13130.566802 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 13130.566802 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13130.566802 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 13130.566802 # average overall miss latency +system.cpu2.icache.occ_blocks::cpu2.inst 83.164978 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.162432 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.162432 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 19795 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 19795 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 19795 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 19795 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 19795 # number of overall hits +system.cpu2.icache.overall_hits::total 19795 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 507 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 507 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 507 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 507 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 507 # number of overall misses +system.cpu2.icache.overall_misses::total 507 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6587500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 6587500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 6587500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 6587500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 6587500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 6587500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 20302 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 20302 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 20302 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 20302 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 20302 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 20302 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024973 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.024973 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024973 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.024973 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024973 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.024973 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 12993.096647 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 12993.096647 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 12993.096647 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 12993.096647 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 12993.096647 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 12993.096647 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1322,106 +1481,106 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs nan system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 58 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 58 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 58 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 58 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 436 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 436 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 436 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 436 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 436 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 436 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5217500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 5217500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5217500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 5217500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5217500 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 5217500 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.020527 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.020527 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.020527 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.020527 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.020527 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.020527 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11966.743119 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 11966.743119 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 11966.743119 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 11966.743119 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 11966.743119 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 11966.743119 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 69 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 69 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 69 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 69 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 438 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 438 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 438 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 438 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 438 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 438 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5265000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 5265000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5265000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 5265000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5265000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 5265000 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021574 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021574 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021574 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.021574 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021574 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.021574 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12020.547945 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12020.547945 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12020.547945 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 12020.547945 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12020.547945 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 12020.547945 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 0 # number of replacements -system.cpu2.dcache.tagsinuse 26.073093 # Cycle average of tags in use -system.cpu2.dcache.total_refs 43891 # Total number of references to valid blocks. -system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 1513.482759 # Average number of references to valid blocks. +system.cpu2.dcache.tagsinuse 24.743159 # Cycle average of tags in use +system.cpu2.dcache.total_refs 46094 # Total number of references to valid blocks. +system.cpu2.dcache.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu2.dcache.avg_refs 1646.214286 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 26.073093 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.050924 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.050924 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 47692 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 47692 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 37413 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 37413 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 85105 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 85105 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 85105 # number of overall hits -system.cpu2.dcache.overall_hits::total 85105 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 405 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 405 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 141 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 141 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 59 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 59 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 546 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 546 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 546 # number of overall misses -system.cpu2.dcache.overall_misses::total 546 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 9305500 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 9305500 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2828000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2828000 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 998500 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 998500 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 12133500 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 12133500 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 12133500 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 12133500 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 48097 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 48097 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 37554 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 37554 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 85651 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 85651 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 85651 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 85651 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.008420 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.008420 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003755 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.003755 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.830986 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.830986 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.006375 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.006375 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.006375 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.006375 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 22976.543210 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 22976.543210 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20056.737589 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 20056.737589 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 16923.728814 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 16923.728814 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 22222.527473 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 22222.527473 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 22222.527473 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 22222.527473 # average overall miss latency +system.cpu2.dcache.occ_blocks::cpu2.data 24.743159 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.048326 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.048326 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 49553 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 49553 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 39712 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 39712 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 89265 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 89265 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 89265 # number of overall hits +system.cpu2.dcache.overall_hits::total 89265 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 426 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 426 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 142 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 142 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 568 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 568 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 568 # number of overall misses +system.cpu2.dcache.overall_misses::total 568 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5684000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 5684000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2389500 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2389500 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 598500 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 598500 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 8073500 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 8073500 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 8073500 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 8073500 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 49979 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 49979 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 39854 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 39854 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 89833 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 89833 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 89833 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 89833 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.008524 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.008524 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003563 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.003563 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.840580 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.840580 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.006323 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.006323 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.006323 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.006323 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 13342.723005 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 13342.723005 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 16827.464789 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 16827.464789 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10318.965517 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 10318.965517 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14213.908451 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 14213.908451 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14213.908451 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 14213.908451 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1430,364 +1589,364 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 239 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 239 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 34 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 273 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 273 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 273 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 273 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 166 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 166 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 266 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 266 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 35 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 301 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 301 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 301 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 301 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 160 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 107 # number of WriteReq MSHR misses system.cpu2.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 59 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 59 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 273 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 273 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 273 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 273 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2062000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2062000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1458000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1458000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 880500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 880500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3520000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3520000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3520000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3520000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003451 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003451 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002849 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002849 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.830986 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.830986 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003187 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.003187 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003187 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.003187 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12421.686747 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 12421.686747 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13626.168224 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13626.168224 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 14923.728814 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 14923.728814 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12893.772894 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12893.772894 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12893.772894 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12893.772894 # average overall mshr miss latency +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1316000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1316000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1150500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1150500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 482500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 482500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2466500 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 2466500 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2466500 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 2466500 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003201 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003201 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002685 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002685 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.840580 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.840580 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.002972 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.002972 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.002972 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.002972 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 8225 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 8225 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 10752.336449 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 10752.336449 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8318.965517 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8318.965517 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9237.827715 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9237.827715 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9237.827715 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9237.827715 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 183564 # number of cpu cycles simulated +system.cpu3.numCycles 181164 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.BPredUnit.lookups 54292 # Number of BP lookups -system.cpu3.BPredUnit.condPredicted 51137 # Number of conditional branches predicted -system.cpu3.BPredUnit.condIncorrect 1552 # Number of conditional branches incorrect -system.cpu3.BPredUnit.BTBLookups 47375 # Number of BTB lookups -system.cpu3.BPredUnit.BTBHits 46456 # Number of BTB hits +system.cpu3.BPredUnit.lookups 41552 # Number of BP lookups +system.cpu3.BPredUnit.condPredicted 38392 # Number of conditional branches predicted +system.cpu3.BPredUnit.condIncorrect 1515 # Number of conditional branches incorrect +system.cpu3.BPredUnit.BTBLookups 34829 # Number of BTB lookups +system.cpu3.BPredUnit.BTBHits 33780 # Number of BTB hits system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.BPredUnit.usedRAS 865 # Number of times the RAS was used to get a target. +system.cpu3.BPredUnit.usedRAS 860 # Number of times the RAS was used to get a target. system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu3.fetch.icacheStallCycles 29332 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 302436 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 54292 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 47321 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 106466 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 4424 # Number of cycles fetch has spent squashing -system.cpu3.fetch.BlockedCycles 35508 # Number of cycles fetch has spent blocked +system.cpu3.fetch.icacheStallCycles 36927 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 218203 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 41552 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 34640 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 84802 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 4380 # Number of cycles fetch has spent squashing +system.cpu3.fetch.BlockedCycles 47727 # Number of cycles fetch has spent blocked system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.NoActiveThreadStallCycles 6464 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 1083 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 21183 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 338 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 181653 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.664911 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.146175 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.NoActiveThreadStallCycles 6229 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.PendingTrapStallCycles 974 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 28719 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 307 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 179453 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.215934 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 1.926514 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 75187 41.39% 41.39% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 54224 29.85% 71.24% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 6571 3.62% 74.86% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3185 1.75% 76.61% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 729 0.40% 77.01% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 36075 19.86% 96.87% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1175 0.65% 97.52% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 882 0.49% 98.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3625 2.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 94651 52.74% 52.74% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 45326 25.26% 78.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 10365 5.78% 83.78% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3238 1.80% 85.58% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 710 0.40% 85.98% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 19490 10.86% 96.84% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1177 0.66% 97.49% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 887 0.49% 97.99% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3609 2.01% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 181653 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.295766 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.647578 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 35528 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 31409 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 99893 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 5564 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2795 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 298258 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 2795 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 36311 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 17134 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 13439 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 94588 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 10922 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 295479 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LSQFullEvents 43 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenamedOperands 206753 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 566043 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 566043 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 191392 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 15361 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1256 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1388 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 13950 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 83468 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 39555 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 39943 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 34309 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 244369 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 6827 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 246724 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 64 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 12382 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 11033 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 652 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 181653 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.358216 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.312562 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 179453 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.229361 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.204450 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 46454 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 40187 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 74815 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 8979 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2789 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 213927 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2789 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 47212 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 26606 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 12751 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 66126 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 17740 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 211407 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LSQFullEvents 35 # Number of times rename has blocked due to LSQ full +system.cpu3.rename.RenamedOperands 144414 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 382760 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 382760 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 129180 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 15234 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1257 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1396 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 20650 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 54196 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 23010 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 27226 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 17768 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 169289 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 10641 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 175038 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 41 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 12721 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 11252 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 865 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 179453 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 0.975397 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.233089 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 72528 39.93% 39.93% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 24126 13.28% 53.21% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 39707 21.86% 75.07% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 40305 22.19% 97.25% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3272 1.80% 99.06% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1282 0.71% 99.76% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 320 0.18% 99.94% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 60 0.03% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 92486 51.54% 51.54% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 34868 19.43% 70.97% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 23272 12.97% 83.94% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 23945 13.34% 97.28% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3213 1.79% 99.07% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1245 0.69% 99.76% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 315 0.18% 99.94% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 48 0.03% 99.97% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 181653 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 179453 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 22 7.41% 7.41% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 7.41% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 7.41% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 7.41% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 7.41% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 7.41% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 7.41% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 7.41% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 7.41% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 7.41% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 7.41% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 7.41% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 7.41% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 7.41% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 7.41% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 7.41% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 7.41% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 7.41% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 7.41% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 7.41% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 7.41% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 7.41% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 7.41% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 7.41% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 7.41% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 7.41% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 7.41% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.41% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 7.41% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 65 21.89% 29.29% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 210 70.71% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 20 6.92% 6.92% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 6.92% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.92% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.92% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.92% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.92% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.92% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.92% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.92% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.92% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.92% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.92% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.92% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.92% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.92% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.92% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.92% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.92% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.92% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.92% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.92% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.92% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.92% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.92% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.92% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.92% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.92% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.92% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.92% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 59 20.42% 27.34% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 210 72.66% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 119576 48.47% 48.47% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.47% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.47% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.47% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.47% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.47% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.47% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.47% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.47% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.47% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.47% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.47% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.47% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.47% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.47% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.47% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.47% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.47% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.47% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.47% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.47% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.47% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.47% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.47% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.47% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.47% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.47% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.47% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.47% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 88284 35.78% 84.25% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 38864 15.75% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 90201 51.53% 51.53% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 51.53% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 51.53% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 51.53% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 51.53% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 51.53% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 51.53% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 51.53% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 51.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 51.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 51.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 51.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 51.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 51.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 51.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 51.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 51.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 51.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 51.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 51.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 51.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 51.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 51.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 51.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 51.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 51.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 51.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 51.53% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 51.53% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 62467 35.69% 87.22% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 22370 12.78% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 246724 # Type of FU issued -system.cpu3.iq.rate 1.344076 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 297 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001204 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 675462 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 263617 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 244690 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 175038 # Type of FU issued +system.cpu3.iq.rate 0.966185 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 289 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001651 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 529859 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 192688 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 173081 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 247021 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 175327 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 34138 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 17671 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2601 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1592 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2642 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1490 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2795 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 1688 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 50 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 292203 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 375 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 83468 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 39555 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1173 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 48 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 2789 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 857 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 208183 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 370 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 54196 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 23010 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1178 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 39 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 498 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1226 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1724 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 245374 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 82515 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1350 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 37 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 501 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1172 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1673 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 173760 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 53123 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1278 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 41007 # number of nop insts executed -system.cpu3.iew.exec_refs 121290 # number of memory reference insts executed -system.cpu3.iew.exec_branches 50490 # Number of branches executed -system.cpu3.iew.exec_stores 38775 # Number of stores executed -system.cpu3.iew.exec_rate 1.336722 # Inst execution rate -system.cpu3.iew.wb_sent 244974 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 244690 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 138171 # num instructions producing a value -system.cpu3.iew.wb_consumers 143054 # num instructions consuming a value +system.cpu3.iew.exec_nop 28253 # number of nop insts executed +system.cpu3.iew.exec_refs 75420 # number of memory reference insts executed +system.cpu3.iew.exec_branches 37599 # Number of branches executed +system.cpu3.iew.exec_stores 22297 # Number of stores executed +system.cpu3.iew.exec_rate 0.959131 # Inst execution rate +system.cpu3.iew.wb_sent 173368 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 173081 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 92251 # num instructions producing a value +system.cpu3.iew.wb_consumers 97140 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.332996 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.965866 # average fanout of values written-back +system.cpu3.iew.wb_rate 0.955383 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.949671 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 14351 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 6175 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1552 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 172395 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.611613 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 2.012919 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 14656 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 9776 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1515 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 170436 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.135365 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.770418 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 72191 41.88% 41.88% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 48466 28.11% 69.99% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 6229 3.61% 73.60% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 7040 4.08% 77.69% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1522 0.88% 78.57% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 34600 20.07% 98.64% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 541 0.31% 98.95% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 992 0.58% 99.53% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 814 0.47% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 95921 56.28% 56.28% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 35624 20.90% 77.18% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 6200 3.64% 80.82% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 10664 6.26% 87.08% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1534 0.90% 87.98% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 18221 10.69% 98.67% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 461 0.27% 98.94% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 1004 0.59% 99.53% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 807 0.47% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 172395 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 277834 # Number of instructions committed -system.cpu3.commit.committedOps 277834 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 170436 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 193507 # Number of instructions committed +system.cpu3.commit.committedOps 193507 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 118830 # Number of memory references committed -system.cpu3.commit.loads 80867 # Number of loads committed -system.cpu3.commit.membars 5460 # Number of memory barriers committed -system.cpu3.commit.branches 49386 # Number of branches committed +system.cpu3.commit.refs 73074 # Number of memory references committed +system.cpu3.commit.loads 51554 # Number of loads committed +system.cpu3.commit.membars 9056 # Number of memory barriers committed +system.cpu3.commit.branches 36531 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 190336 # Number of committed integer instructions. +system.cpu3.commit.int_insts 131724 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.bw_lim_events 814 # number cycles where commit BW limit reached +system.cpu3.commit.bw_lim_events 807 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 463179 # The number of ROB reads -system.cpu3.rob.rob_writes 587180 # The number of ROB writes -system.cpu3.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1911 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 36223 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 232199 # Number of Instructions Simulated -system.cpu3.committedOps 232199 # Number of Ops (including micro ops) Simulated -system.cpu3.committedInsts_total 232199 # Number of Instructions Simulated -system.cpu3.cpi 0.790546 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.790546 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.264948 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.264948 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 423588 # number of integer regfile reads -system.cpu3.int_regfile_writes 197545 # number of integer regfile writes +system.cpu3.rob.rob_reads 377205 # The number of ROB reads +system.cpu3.rob.rob_writes 419128 # The number of ROB writes +system.cpu3.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1711 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 36191 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 157136 # Number of Instructions Simulated +system.cpu3.committedOps 157136 # Number of Ops (including micro ops) Simulated +system.cpu3.committedInsts_total 157136 # Number of Instructions Simulated +system.cpu3.cpi 1.152912 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.152912 # CPI: Total CPI of All Threads +system.cpu3.ipc 0.867369 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.867369 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 286066 # number of integer regfile reads +system.cpu3.int_regfile_writes 135262 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 122942 # number of misc regfile reads +system.cpu3.misc_regfile_reads 77098 # number of misc regfile reads system.cpu3.misc_regfile_writes 646 # number of misc regfile writes -system.cpu3.icache.replacements 321 # number of replacements -system.cpu3.icache.tagsinuse 83.581511 # Cycle average of tags in use -system.cpu3.icache.total_refs 20679 # Total number of references to valid blocks. +system.cpu3.icache.replacements 322 # number of replacements +system.cpu3.icache.tagsinuse 86.042865 # Cycle average of tags in use +system.cpu3.icache.total_refs 28227 # Total number of references to valid blocks. system.cpu3.icache.sampled_refs 436 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 47.428899 # Average number of references to valid blocks. +system.cpu3.icache.avg_refs 64.740826 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 83.581511 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.163245 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.163245 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 20679 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 20679 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 20679 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 20679 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 20679 # number of overall hits -system.cpu3.icache.overall_hits::total 20679 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 504 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 504 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 504 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 504 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 504 # number of overall misses -system.cpu3.icache.overall_misses::total 504 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6381500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 6381500 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 6381500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 6381500 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 6381500 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 6381500 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 21183 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 21183 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 21183 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 21183 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 21183 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 21183 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023793 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.023793 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023793 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.023793 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023793 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.023793 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 12661.706349 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 12661.706349 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 12661.706349 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 12661.706349 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 12661.706349 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 12661.706349 # average overall miss latency +system.cpu3.icache.occ_blocks::cpu3.inst 86.042865 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.168052 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.168052 # 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number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1904,288 +2063,288 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 248 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 248 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 31 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 31 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 279 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 279 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 279 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 279 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 155 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 204 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 204 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 34 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 238 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 238 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 238 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 238 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 165 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 41749.253731 # average overall mshr miss latency +system.l2c.overall_mshr_miss_rate::total 0.310729 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 36411.567867 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 42656.432432 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 42455.023256 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41858.571429 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 33501.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 56002 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 28002 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 56002 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 38316.561338 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10211.105263 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10056.444444 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10027.263158 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10225.550000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10132.315789 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40862.851064 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56501.076923 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 45834.750000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 42584.833333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 43027.916031 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 36411.567867 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41652.880952 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42455.023256 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51376.200000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 33501.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 46616.846154 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 28002 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 43616.923077 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39239.113602 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 36411.567867 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41652.880952 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42455.023256 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51376.200000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 33501.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 46616.846154 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 28002 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 43616.923077 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39239.113602 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |