diff options
| author | Lisa Hsu <Lisa.Hsu@amd.com> | 2010-02-25 10:08:41 -0800 |
|---|---|---|
| committer | Lisa Hsu <Lisa.Hsu@amd.com> | 2010-02-25 10:08:41 -0800 |
| commit | ee20a7c0bddf1f2a1913ddb176910bdce4c13b9c (patch) | |
| tree | 93b9bd8be890468c550b85eae4b467285b4d6811 /tests/quick | |
| parent | 7f3cd9a9fd636c1e48dcec20de3f6c14214d0ce4 (diff) | |
| download | gem5-ee20a7c0bddf1f2a1913ddb176910bdce4c13b9c.tar.xz | |
stats: update stats for the changes I pushed re: shared cache occupancy
Diffstat (limited to 'tests/quick')
114 files changed, 3068 insertions, 1269 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini index 5ab5381fc..24854ed7e 100644 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini @@ -79,6 +79,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -113,6 +114,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -147,6 +149,7 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=10 +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 @@ -188,7 +191,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout index 4ad6292c5..c9e5e8882 100755 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 29 2010 09:13:03 -M5 revision 23ae96d82d21+ 6704+ default qtip tip inorder_hello_alpha -M5 started Jan 29 2010 09:13:04 -M5 executing on zooks +M5 compiled Feb 24 2010 23:12:40 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 02:21:00 +M5 executing on SC2B0619 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt index b9a12afbb..77487dead 100644 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 23048 # Simulator instruction rate (inst/s) -host_mem_usage 153228 # Number of bytes of host memory used -host_seconds 0.28 # Real time elapsed on the host -host_tick_rate 112412599 # Simulator tick rate (ticks/s) +host_inst_rate 37021 # Simulator instruction rate (inst/s) +host_mem_usage 190468 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host +host_tick_rate 180549624 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000031 # Number of seconds simulated @@ -72,6 +72,8 @@ system.cpu.dcache.demand_mshr_misses 182 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.025315 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 103.689640 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56217.032967 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53217.032967 # average overall mshr miss latency @@ -143,6 +145,8 @@ system.cpu.icache.demand_mshr_misses 285 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.063659 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 130.373495 # Average occupied blocks per context system.cpu.icache.overall_accesses 7277 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55521.594684 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52863.157895 # average overall mshr miss latency @@ -234,6 +238,8 @@ system.cpu.l2cache.demand_mshr_misses 452 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.005540 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 181.532273 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 453 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52069.690265 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 39956.858407 # average overall mshr miss latency diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 9978c29e9..1b5a762f3 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -109,7 +109,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -281,7 +281,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -316,7 +316,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout index 207a844c8..0bdde157a 100755 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 6 2009 11:03:45 -M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip -M5 started Jul 6 2009 11:11:06 -M5 executing on maize -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing +M5 compiled Feb 24 2010 23:12:54 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 01:04:08 +M5 executing on SC2B0619 +command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt index 584bdfccf..7fffd3b0b 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 76035 # Simulator instruction rate (inst/s) -host_mem_usage 189864 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -host_tick_rate 148017846 # Simulator tick rate (ticks/s) +host_inst_rate 104903 # Simulator instruction rate (inst/s) +host_mem_usage 190976 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 203948336 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6386 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated @@ -93,6 +93,8 @@ system.cpu.dcache.demand_mshr_misses 188 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.026922 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 110.270477 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2658 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 34900.722022 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 36010.638298 # average overall mshr miss latency @@ -199,6 +201,8 @@ system.cpu.icache.demand_mshr_misses 307 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.077417 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 158.550695 # Average occupied blocks per context system.cpu.icache.overall_accesses 1802 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 35400.943396 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35286.644951 # average overall mshr miss latency @@ -387,6 +391,8 @@ system.cpu.l2cache.demand_mshr_misses 480 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.006558 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 214.901533 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34440.625000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31275 # average overall mshr miss latency diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini index adc37d29a..a69256420 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -57,7 +57,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout index 52c0469fb..0053084d5 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 16:38:39 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 16:57:23 -M5 executing on zizzer +M5 compiled Feb 24 2010 23:12:40 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 03:01:37 +M5 executing on SC2B0619 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt index 3077042e9..301281a5e 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 272186 # Simulator instruction rate (inst/s) -host_mem_usage 192556 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 135226078 # Simulator tick rate (ticks/s) +host_inst_rate 1228467 # Simulator instruction rate (inst/s) +host_mem_usage 182556 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 587751371 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index c0449a709..9b07b770c 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -45,7 +45,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -80,7 +80,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -115,7 +115,7 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 @@ -157,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout index 9f3354a73..7ee1b22c1 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2009 06:58:26 -M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff -M5 started Apr 22 2009 07:17:21 -M5 executing on maize +M5 compiled Feb 24 2010 23:12:40 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 02:20:02 +M5 executing on SC2B0619 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt index fcff4ad2a..998b710c1 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 244055 # Simulator instruction rate (inst/s) -host_mem_usage 201804 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 1274748085 # Simulator tick rate (ticks/s) +host_inst_rate 605866 # Simulator instruction rate (inst/s) +host_mem_usage 190120 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 3109075847 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000034 # Number of seconds simulated @@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses 182 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.025418 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 104.111261 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -119,6 +121,8 @@ system.cpu.icache.demand_mshr_misses 279 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.062817 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 128.649737 # Average occupied blocks per context system.cpu.icache.overall_accesses 6415 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55849.462366 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency @@ -207,6 +211,8 @@ system.cpu.l2cache.demand_mshr_misses 446 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.005491 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 179.928092 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 447 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index f6582aa5c..c164849b4 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -109,7 +109,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -281,7 +281,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -316,7 +316,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr index bb8489f81..67f69f09d 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr @@ -1,5 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) +warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout index 8a4be24f4..703e5cb77 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 6 2009 11:03:45 -M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip -M5 started Jul 6 2009 11:11:07 -M5 executing on maize +M5 compiled Feb 24 2010 23:12:40 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 02:44:06 +M5 executing on SC2B0619 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 9712e8b8d..48416d4fa 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 18690 # Simulator instruction rate (inst/s) -host_mem_usage 188768 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 56136046 # Simulator tick rate (ticks/s) +host_inst_rate 86395 # Simulator instruction rate (inst/s) +host_mem_usage 189960 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 257307637 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated sim_seconds 0.000007 # Number of seconds simulated @@ -93,6 +93,8 @@ system.cpu.dcache.demand_mshr_misses 98 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.011202 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 45.884316 # Average occupied blocks per context system.cpu.dcache.overall_accesses 867 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 36556.994819 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency @@ -199,6 +201,8 @@ system.cpu.icache.demand_mshr_misses 181 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.043324 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 88.727286 # Average occupied blocks per context system.cpu.icache.overall_accesses 747 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 35989.361702 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35298.342541 # average overall mshr miss latency @@ -386,6 +390,8 @@ system.cpu.l2cache.demand_mshr_misses 266 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.003380 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 110.762790 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 266 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34342.105263 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini index 255dbd855..c65c23354 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -57,7 +57,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr index bb8489f81..67f69f09d 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr @@ -1,5 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) +warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout index 0cca599d2..870c07405 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 16:38:39 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 16:39:03 -M5 executing on zizzer +M5 compiled Feb 24 2010 23:12:40 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 02:37:14 +M5 executing on SC2B0619 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt index 8610ea2cd..eeba7561c 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 312515 # Simulator instruction rate (inst/s) -host_mem_usage 191632 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 151541696 # Simulator tick rate (ticks/s) +host_inst_rate 794145 # Simulator instruction rate (inst/s) +host_mem_usage 181656 # Number of bytes of host memory used +host_seconds 0.00 # Real time elapsed on the host +host_tick_rate 371138444 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index b2b4a540c..f316dec65 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -45,7 +45,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -80,7 +80,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -115,7 +115,7 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 @@ -157,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr index bb8489f81..67f69f09d 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr @@ -1,5 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) +warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout index 103381b7c..2135491a6 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2009 06:58:26 -M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff -M5 started Apr 22 2009 07:17:22 -M5 executing on maize +M5 compiled Feb 24 2010 23:12:40 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 03:11:06 +M5 executing on SC2B0619 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt index 72ee5d06d..3c63125e0 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 89461 # Simulator instruction rate (inst/s) -host_mem_usage 200972 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 597928210 # Simulator tick rate (ticks/s) +host_inst_rate 400715 # Simulator instruction rate (inst/s) +host_mem_usage 189300 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 2582342449 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000017 # Number of seconds simulated @@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses 93 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.011615 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 47.575114 # Average occupied blocks per context system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -119,6 +121,8 @@ system.cpu.icache.demand_mshr_misses 163 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.039276 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 80.437325 # Average occupied blocks per context system.cpu.icache.overall_accesses 2586 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -206,6 +210,8 @@ system.cpu.l2cache.demand_mshr_misses 245 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.003139 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 102.857609 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini index fdc787e7b..44238b502 100644 --- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini @@ -58,7 +58,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout index 15f79c280..34f5f5b68 100755 --- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 27 2009 00:45:04 -M5 revision 44a3d32f3217 6414 default qtip tip runnableagainstatupdate.patch -M5 started Jul 27 2009 00:45:05 -M5 executing on fajita +M5 compiled Feb 25 2010 04:11:39 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 04:11:44 +M5 executing on SC2B0619 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt index ece84babb..5099003da 100644 --- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 9392 # Simulator instruction rate (inst/s) -host_mem_usage 189932 # Number of bytes of host memory used -host_seconds 0.59 # Real time elapsed on the host -host_tick_rate 4693453 # Simulator tick rate (ticks/s) +host_inst_rate 1074248 # Simulator instruction rate (inst/s) +host_mem_usage 180696 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 511253720 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5498 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini index 8d2a24508..35f5062a0 100644 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini @@ -133,6 +133,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -167,6 +168,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -201,6 +203,7 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=10 +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 @@ -242,7 +245,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout index ce217f494..f2df8b5ab 100755 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 31 2010 17:08:14 -M5 revision 01508015f86b 6964 default qtip tip inorder_hello_mips -M5 started Jan 31 2010 17:08:15 -M5 executing on zooks +M5 compiled Feb 24 2010 23:13:04 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 03:11:23 +M5 executing on SC2B0619 command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt index df2d539f4..93acca574 100644 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 19644 # Simulator instruction rate (inst/s) -host_mem_usage 155856 # Number of bytes of host memory used -host_seconds 0.30 # Real time elapsed on the host -host_tick_rate 98307932 # Simulator tick rate (ticks/s) +host_inst_rate 38577 # Simulator instruction rate (inst/s) +host_mem_usage 191640 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host +host_tick_rate 192989817 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5827 # Number of instructions simulated sim_seconds 0.000029 # Number of seconds simulated @@ -72,6 +72,8 @@ system.cpu.dcache.demand_mshr_misses 151 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.021604 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 88.491296 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56245.033113 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53245.033113 # average overall mshr miss latency @@ -135,6 +137,8 @@ system.cpu.icache.demand_mshr_misses 303 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.066095 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 135.362853 # Average occupied blocks per context system.cpu.icache.overall_accesses 5874 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55801.980198 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52801.980198 # average overall mshr miss latency @@ -219,6 +223,8 @@ system.cpu.l2cache.demand_mshr_misses 439 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.005708 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 187.032260 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52111.617312 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40054.669704 # average overall mshr miss latency diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini index 962f6ed05..a93b6565a 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini @@ -163,6 +163,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -334,6 +335,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -368,6 +370,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -409,7 +412,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout index 74dedc1d0..f2820f9aa 100755 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 2 2010 07:01:31 -M5 revision a538feb8a617 6813 default qtip tip qbase fixhelp.patch -M5 started Jan 2 2010 07:03:10 -M5 executing on fajita -command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing +M5 compiled Feb 24 2010 23:13:04 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 03:11:23 +M5 executing on SC2B0619 +command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt index 85a5a75dd..e79cbdaa4 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 48407 # Simulator instruction rate (inst/s) -host_mem_usage 206048 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host -host_tick_rate 131379529 # Simulator tick rate (ticks/s) +host_inst_rate 82851 # Simulator instruction rate (inst/s) +host_mem_usage 191760 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 224354167 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5169 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated @@ -93,6 +93,8 @@ system.cpu.dcache.demand_mshr_misses 155 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.022292 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 91.308954 # Average occupied blocks per context system.cpu.dcache.overall_accesses 3246 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 29592.807425 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 36045.161290 # average overall mshr miss latency @@ -191,6 +193,8 @@ system.cpu.icache.demand_mshr_misses 329 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.076179 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 156.015053 # Average occupied blocks per context system.cpu.icache.overall_accesses 2220 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 35681.279621 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 34902.735562 # average overall mshr miss latency @@ -372,6 +376,8 @@ system.cpu.l2cache.demand_mshr_misses 466 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.006413 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 210.151573 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 470 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34356.223176 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31162.017167 # average overall mshr miss latency diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini index 5d677c743..0e0904624 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini @@ -111,7 +111,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout index a364f6e08..5dbd10419 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 2 2010 07:01:31 -M5 revision a538feb8a617 6813 default qtip tip qbase fixhelp.patch -M5 started Jan 2 2010 07:03:10 -M5 executing on fajita -command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic +M5 compiled Feb 24 2010 23:13:04 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 03:11:22 +M5 executing on SC2B0619 +command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt index 090c28d32..a6694501e 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 449580 # Simulator instruction rate (inst/s) -host_mem_usage 197348 # Number of bytes of host memory used +host_inst_rate 1101929 # Simulator instruction rate (inst/s) +host_mem_usage 183300 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 220987561 # Simulator tick rate (ticks/s) +host_tick_rate 525428314 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5827 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini index 3e36bc6f8..aecf3d2c5 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -99,6 +99,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -133,6 +134,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -167,6 +169,7 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=10 +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 @@ -208,7 +211,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout index f5b9b6f90..31e8564a2 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 2 2010 07:01:31 -M5 revision a538feb8a617 6813 default qtip tip qbase fixhelp.patch -M5 started Jan 2 2010 07:03:09 -M5 executing on fajita -command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing +M5 compiled Feb 24 2010 23:13:04 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 03:11:22 +M5 executing on SC2B0619 +command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt index 14247d496..5c8b8dc04 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 21056 # Simulator instruction rate (inst/s) -host_mem_usage 204976 # Number of bytes of host memory used -host_seconds 0.28 # Real time elapsed on the host -host_tick_rate 118397165 # Simulator tick rate (ticks/s) +host_inst_rate 534293 # Simulator instruction rate (inst/s) +host_mem_usage 190944 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 2928316372 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5827 # Number of instructions simulated sim_seconds 0.000033 # Number of seconds simulated @@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses 151 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.021457 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 87.887695 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -112,6 +114,8 @@ system.cpu.icache.demand_mshr_misses 303 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.065174 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 133.475693 # Average occupied blocks per context system.cpu.icache.overall_accesses 5829 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55722.772277 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency @@ -193,6 +197,8 @@ system.cpu.l2cache.demand_mshr_misses 439 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.005638 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 184.758016 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini index 6b0ea33cd..508240960 100644 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini @@ -110,6 +110,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -281,6 +282,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -315,6 +317,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -356,7 +359,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/power/linux/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/power/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr index a2692a6c9..4c710c177 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr @@ -1,5 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: allowing mmap of file @ fd 4294967295. This will break if not /dev/zero. +warn: allowing mmap of file @ fd 13202840. This will break if not /dev/zero. For more information see: http://www.m5sim.org/warn/3a2134f6 hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/00.hello/ref/power/linux/o3-timing/simout index bc2c673ec..85fc6bc9f 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 15 2009 15:43:13 -M5 revision b43c2c69a460 6694 default hello-world-outputs.patch qtip tip -M5 started Oct 15 2009 15:49:09 -M5 executing on frontend01 +M5 compiled Feb 24 2010 23:13:07 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 24 2010 23:13:11 +M5 executing on SC2B0619 command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt index 59c9aa334..4d658aa1d 100644 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 103409 # Simulator instruction rate (inst/s) -host_mem_usage 271924 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 212174700 # Simulator tick rate (ticks/s) +host_inst_rate 51828 # Simulator instruction rate (inst/s) +host_mem_usage 189300 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host +host_tick_rate 106468871 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5800 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated @@ -93,6 +93,8 @@ system.cpu.dcache.demand_mshr_misses 121 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.016127 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 66.056188 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2482 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 33461.363636 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 35202.479339 # average overall mshr miss latency @@ -192,6 +194,8 @@ system.cpu.icache.demand_mshr_misses 330 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.077734 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 159.198376 # Average occupied blocks per context system.cpu.icache.overall_accesses 1463 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 36616.094987 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 34771.212121 # average overall mshr miss latency @@ -373,6 +377,8 @@ system.cpu.l2cache.demand_mshr_misses 426 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.005513 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 180.652204 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 434 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34374.413146 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31194.835681 # average overall mshr miss latency diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini index 129c166c3..930fa65ed 100644 --- a/tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini @@ -58,7 +58,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/power/linux/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/power/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/power/linux/simple-atomic/simerr index a2692a6c9..a2a4d88c2 100755 --- a/tests/quick/00.hello/ref/power/linux/simple-atomic/simerr +++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/simerr @@ -1,5 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: allowing mmap of file @ fd 4294967295. This will break if not /dev/zero. +warn: allowing mmap of file @ fd 13074680. This will break if not /dev/zero. For more information see: http://www.m5sim.org/warn/3a2134f6 hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/simout b/tests/quick/00.hello/ref/power/linux/simple-atomic/simout index 410d89b19..23b972156 100755 --- a/tests/quick/00.hello/ref/power/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 15 2009 15:43:13 -M5 revision b43c2c69a460 6694 default hello-world-outputs.patch qtip tip -M5 started Oct 15 2009 15:49:56 -M5 executing on frontend01 +M5 compiled Feb 24 2010 23:13:07 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 24 2010 23:13:11 +M5 executing on SC2B0619 command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt index 325ee615a..8c0754d0c 100644 --- a/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 259216 # Simulator instruction rate (inst/s) -host_mem_usage 263696 # Number of bytes of host memory used +host_inst_rate 277162 # Simulator instruction rate (inst/s) +host_mem_usage 181156 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 128114508 # Simulator tick rate (ticks/s) +host_tick_rate 136566988 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5801 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini index ade758841..7b5adc160 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -57,7 +57,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout index 4273b735d..ec097652e 100755 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 18:04:32 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 18:05:07 -M5 executing on zizzer +M5 compiled Feb 25 2010 03:11:27 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 03:37:59 +M5 executing on SC2B0619 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt index e9a2222d7..01cd0d37d 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 314858 # Simulator instruction rate (inst/s) -host_mem_usage 193720 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 157107957 # Simulator tick rate (ticks/s) +host_inst_rate 897027 # Simulator instruction rate (inst/s) +host_mem_usage 182692 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 434663663 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5340 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini index 928e1a6a9..8f9e543cc 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -45,7 +45,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -80,7 +80,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -115,7 +115,7 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 @@ -157,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout index 788a84f52..9485c1bb2 100755 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2009 06:58:47 -M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff -M5 started Apr 22 2009 07:32:52 -M5 executing on maize +M5 compiled Feb 25 2010 03:11:27 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 03:37:59 +M5 executing on SC2B0619 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt index 2f90cc999..11fb745f1 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 165633 # Simulator instruction rate (inst/s) -host_mem_usage 203084 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 893371492 # Simulator tick rate (ticks/s) +host_inst_rate 462498 # Simulator instruction rate (inst/s) +host_mem_usage 190336 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 2452978454 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5340 # Number of instructions simulated sim_seconds 0.000029 # Number of seconds simulated @@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses 150 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.020107 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 82.357482 # Average occupied blocks per context system.cpu.dcache.overall_accesses 1389 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 55720 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 52720 # average overall mshr miss latency @@ -103,6 +105,8 @@ system.cpu.icache.demand_mshr_misses 257 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.057478 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 117.715481 # Average occupied blocks per context system.cpu.icache.overall_accesses 5384 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55673.151751 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52673.151751 # average overall mshr miss latency @@ -175,6 +179,8 @@ system.cpu.l2cache.demand_mshr_misses 389 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.004176 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 136.844792 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 392 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini index 911046b97..49018d812 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini @@ -57,7 +57,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout index 0030aae6b..d7f9758f3 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 8 2009 12:09:45 -M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch -M5 started Aug 8 2009 12:09:46 -M5 executing on tater +M5 compiled Feb 25 2010 03:41:05 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 04:11:29 +M5 executing on SC2B0619 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt index a72432b3a..8b2e120b0 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 23019 # Simulator instruction rate (inst/s) -host_mem_usage 193704 # Number of bytes of host memory used -host_seconds 0.41 # Real time elapsed on the host -host_tick_rate 13302912 # Simulator tick rate (ticks/s) +host_inst_rate 940985 # Simulator instruction rate (inst/s) +host_mem_usage 185436 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 530148334 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9519 # Number of instructions simulated sim_seconds 0.000006 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini index 5db260ab9..64e4a7561 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini @@ -45,7 +45,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -80,7 +80,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -115,7 +115,7 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 @@ -157,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout index 299195d5b..de395dbab 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 8 2009 12:09:45 -M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch -M5 started Aug 8 2009 12:09:46 -M5 executing on tater +M5 compiled Feb 25 2010 03:41:05 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 04:11:30 +M5 executing on SC2B0619 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt index e83d6fcbe..a1830d00b 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 21415 # Simulator instruction rate (inst/s) -host_mem_usage 201336 # Number of bytes of host memory used -host_seconds 0.44 # Real time elapsed on the host -host_tick_rate 66853602 # Simulator tick rate (ticks/s) +host_inst_rate 605496 # Simulator instruction rate (inst/s) +host_mem_usage 193040 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 1857026858 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9519 # Number of instructions simulated sim_seconds 0.000030 # Number of seconds simulated @@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses 152 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.019744 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 80.872189 # Average occupied blocks per context system.cpu.dcache.overall_accesses 1987 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -103,6 +105,8 @@ system.cpu.icache.demand_mshr_misses 228 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.052069 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 106.638328 # Average occupied blocks per context system.cpu.icache.overall_accesses 6887 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency @@ -175,6 +179,8 @@ system.cpu.l2cache.demand_mshr_misses 360 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.003910 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 128.120518 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 361 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index 4e95f234f..dcbe2d23b 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -71,7 +71,7 @@ numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 numRobs=1 -numThreads=1 +numThreads=2 phase=0 predType=tournament progress_interval=0 @@ -109,7 +109,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -281,7 +281,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -316,7 +316,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -377,7 +377,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index 43c668adc..660b124b5 100755 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 6 2009 11:03:45 -M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip -M5 started Jul 6 2009 11:11:05 -M5 executing on maize +M5 compiled Feb 24 2010 23:12:40 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 02:20:32 +M5 executing on SC2B0619 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 66bc81d29..016b2b2d7 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 36918 # Simulator instruction rate (inst/s) -host_mem_usage 190384 # Number of bytes of host memory used -host_seconds 0.35 # Real time elapsed on the host -host_tick_rate 41160042 # Simulator tick rate (ticks/s) +host_inst_rate 95914 # Simulator instruction rate (inst/s) +host_mem_usage 191488 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host +host_tick_rate 106648956 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 12773 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated @@ -65,40 +65,38 @@ system.cpu.committedInsts_total 12773 # Nu system.cpu.cpi::0 4.463514 # CPI: Cycles Per Instruction system.cpu.cpi::1 4.462815 # CPI: Cycles Per Instruction system.cpu.cpi_total 2.231582 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses::0 3925 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3925 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses 3925 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency::0 35473.913043 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 35473.913043 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::0 36849.514563 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits::0 3580 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3580 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 3580 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency::0 12238500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 12238500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::0 0.087898 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 345 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 345 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_rate 0.087898 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 345 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits::0 139 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 139 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency::0 7591000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 7591000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.052484 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052484 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses::0 206 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 206 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses::0 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 1730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency::0 33703.947368 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33703.947368 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::0 36103.448276 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits::0 970 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 970 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits 970 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency::0 25615000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 25615000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::0 0.439306 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 760 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 760 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_rate 0.439306 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 760 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits::0 586 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 586 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_miss_latency::0 6282000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 6282000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.100578 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.100578 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses::0 174 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 174 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -109,27 +107,19 @@ system.cpu.dcache.blocked::no_targets 0 # nu system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 5655 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 5655 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 5655 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency::0 34256.561086 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::1 0 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34256.561086 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::0 36507.894737 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 4550 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4550 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 4550 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency::0 37853500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 37853500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.195402 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 1105 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1105 # number of demand (read+write) misses +system.cpu.dcache.demand_miss_rate 0.195402 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1105 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits::0 725 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 725 # number of demand (read+write) MSHR hits @@ -137,8 +127,8 @@ system.cpu.dcache.demand_mshr_miss_latency::0 13873000 system.cpu.dcache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 13873000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate::0 0.067197 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.067197 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses::0 380 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 380 # number of demand (read+write) MSHR misses @@ -147,30 +137,24 @@ system.cpu.dcache.mshr_cap_events::0 0 # nu system.cpu.dcache.mshr_cap_events::1 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events::total 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses::0 5655 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 5655 # number of overall (read+write) accesses +system.cpu.dcache.occ_%::0 0.054614 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 223.700041 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 5655 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency::0 34256.561086 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::1 0 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34256.561086 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::0 36507.894737 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 4550 # number of overall hits -system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 4550 # number of overall hits +system.cpu.dcache.overall_hits 4550 # number of overall hits system.cpu.dcache.overall_miss_latency::0 37853500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::1 0 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 37853500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.195402 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 1105 # number of overall misses -system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 1105 # number of overall misses +system.cpu.dcache.overall_miss_rate 0.195402 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1105 # number of overall misses system.cpu.dcache.overall_mshr_hits::0 725 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::1 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 725 # number of overall MSHR hits @@ -178,8 +162,8 @@ system.cpu.dcache.overall_mshr_miss_latency::0 13873000 system.cpu.dcache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 13873000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate::0 0.067197 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.067197 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses::0 380 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::1 0 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 380 # number of overall MSHR misses @@ -254,22 +238,21 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 22904 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses::0 4113 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 4113 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 4113 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency::0 35793.697979 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35793.697979 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::0 35516.155089 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::0 3272 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 3272 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 3272 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency::0 30102500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 30102500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::0 0.204474 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 841 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 841 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_rate 0.204474 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 841 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits::0 222 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 222 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_miss_latency::0 21984500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 21984500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::0 0.150498 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.150498 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses::0 619 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 619 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -280,27 +263,19 @@ system.cpu.icache.blocked::no_targets 0 # nu system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 4113 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 4113 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 4113 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency::0 35793.697979 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::1 0 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35793.697979 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency::0 35516.155089 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.icache.demand_hits::0 3272 # number of demand (read+write) hits -system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 3272 # number of demand (read+write) hits +system.cpu.icache.demand_hits 3272 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency::0 30102500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 30102500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.204474 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 841 # number of demand (read+write) misses -system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 841 # number of demand (read+write) misses +system.cpu.icache.demand_miss_rate 0.204474 # miss rate for demand accesses +system.cpu.icache.demand_misses 841 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits::0 222 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 222 # number of demand (read+write) MSHR hits @@ -308,8 +283,8 @@ system.cpu.icache.demand_mshr_miss_latency::0 21984500 system.cpu.icache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 21984500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate::0 0.150498 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.150498 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses::0 619 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 619 # number of demand (read+write) MSHR misses @@ -318,30 +293,24 @@ system.cpu.icache.mshr_cap_events::0 0 # nu system.cpu.icache.mshr_cap_events::1 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events::total 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses::0 4113 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 4113 # number of overall (read+write) accesses +system.cpu.icache.occ_%::0 0.156877 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 321.284131 # Average occupied blocks per context +system.cpu.icache.overall_accesses 4113 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency::0 35793.697979 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::1 0 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35793.697979 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency::0 35516.155089 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 3272 # number of overall hits -system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 3272 # number of overall hits +system.cpu.icache.overall_hits 3272 # number of overall hits system.cpu.icache.overall_miss_latency::0 30102500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::1 0 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 30102500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.204474 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 841 # number of overall misses -system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 841 # number of overall misses +system.cpu.icache.overall_miss_rate 0.204474 # miss rate for overall accesses +system.cpu.icache.overall_misses 841 # number of overall misses system.cpu.icache.overall_mshr_hits::0 222 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::1 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 222 # number of overall MSHR hits @@ -349,8 +318,8 @@ system.cpu.icache.overall_mshr_miss_latency::0 21984500 system.cpu.icache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 21984500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate::0 0.150498 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.150498 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses::0 619 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::1 0 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 619 # number of overall MSHR misses @@ -563,48 +532,47 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses::0 146 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 146 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency::0 34643.835616 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34643.835616 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::0 31589.041096 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_miss_latency::0 5058000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 5058000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses::0 146 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 146 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::0 4612000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4612000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses::0 146 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses::0 825 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 825 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses 825 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency::0 34555.285541 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34555.285541 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::0 31414.337789 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits::0 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_miss_latency::0 28439000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 28439000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate::0 0.997576 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses::0 823 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 823 # number of ReadReq misses +system.cpu.l2cache.ReadReq_miss_rate 0.997576 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 823 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency::0 25854000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25854000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::0 0.997576 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997576 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses::0 823 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 823 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses::0 28 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 28 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 28 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency::0 34482.142857 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 34482.142857 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::0 31357.142857 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_miss_latency::0 965500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 965500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses::0 28 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 28 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 28 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency::0 878000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 878000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses::0 28 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 28 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6750 # average number of cycles each access was blocked @@ -615,27 +583,19 @@ system.cpu.l2cache.blocked::no_targets 0 # nu system.cpu.l2cache.blocked_cycles::no_mshrs 27000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses::0 971 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 971 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 971 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency::0 34568.627451 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total no_value # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::1 0 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34568.627451 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::0 31440.660475 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.l2cache.demand_hits::0 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits system.cpu.l2cache.demand_miss_latency::0 33497000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 33497000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate::0 0.997940 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.l2cache.demand_misses::0 969 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 969 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_rate 0.997940 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 969 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits::0 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 0 # number of demand (read+write) MSHR hits @@ -643,8 +603,8 @@ system.cpu.l2cache.demand_mshr_miss_latency::0 30466000 system.cpu.l2cache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 30466000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate::0 0.997940 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997940 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses::0 969 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 969 # number of demand (read+write) MSHR misses @@ -653,30 +613,24 @@ system.cpu.l2cache.mshr_cap_events::0 0 # nu system.cpu.l2cache.mshr_cap_events::1 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events::total 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses::0 971 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 971 # number of overall (read+write) accesses +system.cpu.l2cache.occ_%::0 0.013297 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 435.713880 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 971 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency::0 34568.627451 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::1 0 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34568.627451 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::0 31440.660475 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits::0 2 # number of overall hits -system.cpu.l2cache.overall_hits::1 0 # number of overall hits -system.cpu.l2cache.overall_hits::total 2 # number of overall hits +system.cpu.l2cache.overall_hits 2 # number of overall hits system.cpu.l2cache.overall_miss_latency::0 33497000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::1 0 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 33497000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate::0 0.997940 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.l2cache.overall_misses::0 969 # number of overall misses -system.cpu.l2cache.overall_misses::1 0 # number of overall misses -system.cpu.l2cache.overall_misses::total 969 # number of overall misses +system.cpu.l2cache.overall_miss_rate 0.997940 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 969 # number of overall misses system.cpu.l2cache.overall_mshr_hits::0 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::1 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 0 # number of overall MSHR hits @@ -684,8 +638,8 @@ system.cpu.l2cache.overall_mshr_miss_latency::0 30466000 system.cpu.l2cache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 30466000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate::0 0.997940 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997940 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses::0 969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::1 0 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 969 # number of overall MSHR misses diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini index e7d27f8d6..0cc32d77e 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -109,7 +109,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -281,7 +281,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -316,7 +316,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout index 6d075503d..a6f645c41 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 6 2009 11:07:18 -M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip -M5 started Jul 6 2009 11:11:24 -M5 executing on maize +M5 compiled Feb 25 2010 03:11:27 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 03:38:00 +M5 executing on SC2B0619 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 4b0bc6800..d92dfc078 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1945 # Simulator instruction rate (inst/s) -host_mem_usage 190344 # Number of bytes of host memory used -host_seconds 7.43 # Real time elapsed on the host -host_tick_rate 3735278 # Simulator tick rate (ticks/s) +host_inst_rate 72869 # Simulator instruction rate (inst/s) +host_mem_usage 190800 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host +host_tick_rate 139786869 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 14449 # Number of instructions simulated sim_seconds 0.000028 # Number of seconds simulated @@ -95,6 +95,8 @@ system.cpu.dcache.demand_mshr_misses 167 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.026530 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 108.665251 # Average occupied blocks per context system.cpu.dcache.overall_accesses 5286 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 32057.347670 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 35607.784431 # average overall mshr miss latency @@ -182,6 +184,8 @@ system.cpu.icache.demand_mshr_misses 359 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.110760 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 226.836007 # Average occupied blocks per context system.cpu.icache.overall_accesses 7356 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 33620.560748 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 34869.080780 # average overall mshr miss latency @@ -354,6 +358,8 @@ system.cpu.l2cache.demand_mshr_misses 503 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.007680 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 251.642612 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 507 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34252.485089 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31057.654076 # average overall mshr miss latency diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini index 75d383c46..0d783c1db 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini @@ -57,7 +57,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout index 3b6aca04c..a758d34e6 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 18:04:32 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 18:05:08 -M5 executing on zizzer +M5 compiled Feb 25 2010 03:11:27 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 03:38:01 +M5 executing on SC2B0619 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt index bb032e871..970d208fc 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 587404 # Simulator instruction rate (inst/s) -host_mem_usage 193520 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 292299724 # Simulator tick rate (ticks/s) +host_inst_rate 1098364 # Simulator instruction rate (inst/s) +host_mem_usage 182400 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 540894569 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 15175 # Number of instructions simulated sim_seconds 0.000008 # Number of seconds simulated diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini index ab1742f70..777caa173 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -45,7 +45,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -80,7 +80,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -115,7 +115,7 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 @@ -157,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout index 76cbb3c5f..2c0f40a56 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2009 06:58:47 -M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff -M5 started Apr 22 2009 07:32:53 -M5 executing on maize +M5 compiled Feb 25 2010 03:11:27 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 03:38:01 +M5 executing on SC2B0619 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt index 5c475dff1..07c8914c3 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 286976 # Simulator instruction rate (inst/s) -host_mem_usage 202788 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 804151064 # Simulator tick rate (ticks/s) +host_inst_rate 227392 # Simulator instruction rate (inst/s) +host_mem_usage 190044 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 637540839 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 15175 # Number of instructions simulated sim_seconds 0.000043 # Number of seconds simulated @@ -52,6 +52,8 @@ system.cpu.dcache.demand_mshr_misses 155 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.023864 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 97.747327 # Average occupied blocks per context system.cpu.dcache.overall_accesses 3668 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -105,6 +107,8 @@ system.cpu.icache.demand_mshr_misses 280 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.074743 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 153.073222 # Average occupied blocks per context system.cpu.icache.overall_accesses 15221 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55700 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52700 # average overall mshr miss latency @@ -177,6 +181,8 @@ system.cpu.l2cache.demand_mshr_misses 416 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.005323 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 174.433606 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 418 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index 40be52d31..e7e943434 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -8,11 +8,11 @@ type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux mem_mode=atomic -pal=/dist/m5/system/binaries/ts_osfpal +pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -74,7 +74,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -109,7 +109,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -181,7 +181,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -216,7 +216,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -264,7 +264,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.disk2] @@ -284,7 +284,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -312,7 +312,7 @@ hash_delay=1 latency=50000 max_miss_count=0 mshrs=20 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=500000 @@ -343,7 +343,7 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=92 -prefetch_cache_check_push=true +num_cpus=2 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 @@ -410,7 +410,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout index fbb703fe5..643403e5a 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 6 2009 11:02:48 -M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip -M5 started Jul 6 2009 11:10:46 -M5 executing on maize +M5 compiled Feb 24 2010 23:13:04 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 24 2010 23:13:12 +M5 executing on SC2B0619 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1870335522500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 7f868c60a..591b54757 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -1,29 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 4214021 # Simulator instruction rate (inst/s) -host_mem_usage 277380 # Number of bytes of host memory used -host_seconds 14.99 # Real time elapsed on the host -host_tick_rate 124797908529 # Simulator tick rate (ticks/s) +host_inst_rate 2090501 # Simulator instruction rate (inst/s) +host_mem_usage 278608 # Number of bytes of host memory used +host_seconds 30.21 # Real time elapsed on the host +host_tick_rate 61910551280 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 63154034 # Number of instructions simulated sim_seconds 1.870336 # Number of seconds simulated sim_ticks 1870335522500 # Number of ticks simulated -system.cpu0.dcache.LoadLockedReq_accesses 188297 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_hits 172138 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_miss_rate 0.085817 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_misses 16159 # number of LoadLockedReq misses -system.cpu0.dcache.ReadReq_accesses 8981669 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_hits 7298106 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_rate 0.187444 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 1683563 # number of ReadReq misses -system.cpu0.dcache.StoreCondReq_accesses 187338 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_hits 159838 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_rate 0.146793 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_misses 27500 # number of StoreCondReq misses -system.cpu0.dcache.WriteReq_accesses 5748261 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_hits 5374453 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_rate 0.065030 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 373808 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_accesses::0 188297 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 188297 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_hits::0 172138 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 172138 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.085817 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses::0 16159 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 16159 # number of LoadLockedReq misses +system.cpu0.dcache.ReadReq_accesses::0 8981669 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8981669 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_hits::0 7298106 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7298106 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_rate::0 0.187444 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses::0 1683563 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1683563 # number of ReadReq misses +system.cpu0.dcache.StoreCondReq_accesses::0 187338 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 187338 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_hits::0 159838 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 159838 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.146793 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses::0 27500 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 27500 # number of StoreCondReq misses +system.cpu0.dcache.WriteReq_accesses::0 5748261 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5748261 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_hits::0 5374453 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5374453 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_rate::0 0.065030 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses::0 373808 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 373808 # number of WriteReq misses system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.dcache.avg_refs 6.629793 # Average number of references to valid blocks. @@ -32,31 +44,57 @@ system.cpu0.dcache.blocked::no_targets 0 # nu system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 14729930 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu0.dcache.demand_accesses::0 14729930 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14729930 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency::0 0 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu0.dcache.demand_hits 12672559 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::0 12672559 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12672559 # number of demand (read+write) hits system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.139673 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 2057371 # number of demand (read+write) misses +system.cpu0.dcache.demand_miss_rate::0 0.139673 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu0.dcache.demand_misses::0 2057371 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2057371 # number of demand (read+write) misses system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.overall_accesses 14729930 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu0.dcache.occ_%::0 0.985990 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::0 504.827058 # Average occupied blocks per context +system.cpu0.dcache.overall_accesses::0 14729930 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14729930 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency::0 0 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total no_value # average overall miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 12672559 # number of overall hits +system.cpu0.dcache.overall_hits::0 12672559 # number of overall hits +system.cpu0.dcache.overall_hits::1 0 # number of overall hits +system.cpu0.dcache.overall_hits::total 12672559 # number of overall hits system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.139673 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 2057371 # number of overall misses +system.cpu0.dcache.overall_miss_rate::0 0.139673 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu0.dcache.overall_misses::0 2057371 # number of overall misses +system.cpu0.dcache.overall_misses::1 0 # number of overall misses +system.cpu0.dcache.overall_misses::total 2057371 # number of overall misses system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -83,10 +121,13 @@ system.cpu0.dtb.write_accesses 189050 # DT system.cpu0.dtb.write_acv 99 # DTB write access violations system.cpu0.dtb.write_hits 5936899 # DTB write hits system.cpu0.dtb.write_misses 726 # DTB write misses -system.cpu0.icache.ReadReq_accesses 57230132 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_hits 56345132 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_rate 0.015464 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses 885000 # number of ReadReq misses +system.cpu0.icache.ReadReq_accesses::0 57230132 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 57230132 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_hits::0 56345132 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 56345132 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_rate::0 0.015464 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses::0 885000 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 885000 # number of ReadReq misses system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.avg_refs 63.672859 # Average number of references to valid blocks. @@ -95,31 +136,57 @@ system.cpu0.icache.blocked::no_targets 0 # nu system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 57230132 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu0.icache.demand_accesses::0 57230132 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 57230132 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency::0 0 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu0.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu0.icache.demand_hits 56345132 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::0 56345132 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 56345132 # number of demand (read+write) hits system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate 0.015464 # miss rate for demand accesses -system.cpu0.icache.demand_misses 885000 # number of demand (read+write) misses +system.cpu0.icache.demand_miss_rate::0 0.015464 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu0.icache.demand_misses::0 885000 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 885000 # number of demand (read+write) misses system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.overall_accesses 57230132 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu0.icache.occ_%::0 0.998525 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::0 511.244754 # Average occupied blocks per context +system.cpu0.icache.overall_accesses::0 57230132 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 57230132 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency::0 0 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total no_value # average overall miss latency system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 56345132 # number of overall hits +system.cpu0.icache.overall_hits::0 56345132 # number of overall hits +system.cpu0.icache.overall_hits::1 0 # number of overall hits +system.cpu0.icache.overall_hits::total 56345132 # number of overall hits system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate 0.015464 # miss rate for overall accesses -system.cpu0.icache.overall_misses 885000 # number of overall misses +system.cpu0.icache.overall_miss_rate::0 0.015464 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu0.icache.overall_misses::0 885000 # number of overall misses +system.cpu0.icache.overall_misses::1 0 # number of overall misses +system.cpu0.icache.overall_misses::total 885000 # number of overall misses system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -240,22 +307,34 @@ system.cpu0.not_idle_fraction 0.015300 # Pe system.cpu0.numCycles 3740670933 # number of cpu cycles simulated system.cpu0.num_insts 57222076 # Number of instructions executed system.cpu0.num_refs 15330887 # Number of memory references -system.cpu1.dcache.LoadLockedReq_accesses 16418 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_hits 15129 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_miss_rate 0.078511 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_misses 1289 # number of LoadLockedReq misses -system.cpu1.dcache.ReadReq_accesses 1150965 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_hits 1109315 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_rate 0.036187 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses 41650 # number of ReadReq misses -system.cpu1.dcache.StoreCondReq_accesses 16345 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_hits 13438 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_miss_rate 0.177853 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_misses 2907 # number of StoreCondReq misses -system.cpu1.dcache.WriteReq_accesses 733305 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_hits 702803 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_rate 0.041595 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses 30502 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_accesses::0 16418 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_hits::0 15129 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 15129 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.078511 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_misses::0 1289 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 1289 # number of LoadLockedReq misses +system.cpu1.dcache.ReadReq_accesses::0 1150965 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1150965 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_hits::0 1109315 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1109315 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_rate::0 0.036187 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses::0 41650 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 41650 # number of ReadReq misses +system.cpu1.dcache.StoreCondReq_accesses::0 16345 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 16345 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_hits::0 13438 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 13438 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.177853 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses::0 2907 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 2907 # number of StoreCondReq misses +system.cpu1.dcache.WriteReq_accesses::0 733305 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 733305 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_hits::0 702803 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 702803 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_rate::0 0.041595 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses::0 30502 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 30502 # number of WriteReq misses system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.avg_refs 29.279155 # Average number of references to valid blocks. @@ -264,31 +343,57 @@ system.cpu1.dcache.blocked::no_targets 0 # nu system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses 1884270 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu1.dcache.demand_accesses::0 1884270 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency::0 0 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu1.dcache.demand_hits 1812118 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::0 1812118 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1812118 # number of demand (read+write) hits system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.038292 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 72152 # number of demand (read+write) misses +system.cpu1.dcache.demand_miss_rate::0 0.038292 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu1.dcache.demand_misses::0 72152 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 72152 # number of demand (read+write) misses system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.overall_accesses 1884270 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu1.dcache.occ_%::0 0.765530 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 391.951263 # Average occupied blocks per context +system.cpu1.dcache.overall_accesses::0 1884270 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency::0 0 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total no_value # average overall miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 1812118 # number of overall hits +system.cpu1.dcache.overall_hits::0 1812118 # number of overall hits +system.cpu1.dcache.overall_hits::1 0 # number of overall hits +system.cpu1.dcache.overall_hits::total 1812118 # number of overall hits system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.038292 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 72152 # number of overall misses +system.cpu1.dcache.overall_miss_rate::0 0.038292 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu1.dcache.overall_misses::0 72152 # number of overall misses +system.cpu1.dcache.overall_misses::1 0 # number of overall misses +system.cpu1.dcache.overall_misses::total 72152 # number of overall misses system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -315,10 +420,13 @@ system.cpu1.dtb.write_accesses 103280 # DT system.cpu1.dtb.write_acv 58 # DTB write access violations system.cpu1.dtb.write_hits 751446 # DTB write hits system.cpu1.dtb.write_misses 415 # DTB write misses -system.cpu1.icache.ReadReq_accesses 5935766 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_hits 5832136 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_rate 0.017459 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses 103630 # number of ReadReq misses +system.cpu1.icache.ReadReq_accesses::0 5935766 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 5935766 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_hits::0 5832136 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 5832136 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_rate::0 0.017459 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses::0 103630 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 103630 # number of ReadReq misses system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.avg_refs 56.293119 # Average number of references to valid blocks. @@ -327,31 +435,57 @@ system.cpu1.icache.blocked::no_targets 0 # nu system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses 5935766 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu1.icache.demand_accesses::0 5935766 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 5935766 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency::0 0 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu1.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu1.icache.demand_hits 5832136 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::0 5832136 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 5832136 # number of demand (read+write) hits system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate 0.017459 # miss rate for demand accesses -system.cpu1.icache.demand_misses 103630 # number of demand (read+write) misses +system.cpu1.icache.demand_miss_rate::0 0.017459 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu1.icache.demand_misses::0 103630 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 103630 # number of demand (read+write) misses system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.overall_accesses 5935766 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu1.icache.occ_%::0 0.834231 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 427.126317 # Average occupied blocks per context +system.cpu1.icache.overall_accesses::0 5935766 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 5935766 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency::0 0 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total no_value # average overall miss latency system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits 5832136 # number of overall hits +system.cpu1.icache.overall_hits::0 5832136 # number of overall hits +system.cpu1.icache.overall_hits::1 0 # number of overall hits +system.cpu1.icache.overall_hits::total 5832136 # number of overall hits system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate 0.017459 # miss rate for overall accesses -system.cpu1.icache.overall_misses 103630 # number of overall misses +system.cpu1.icache.overall_miss_rate::0 0.017459 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu1.icache.overall_misses::0 103630 # number of overall misses +system.cpu1.icache.overall_misses::1 0 # number of overall misses +system.cpu1.icache.overall_misses::total 103630 # number of overall misses system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -467,12 +601,16 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iocache.ReadReq_accesses 175 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_misses 175 # number of ReadReq misses -system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_misses 41552 # number of WriteReq misses +system.iocache.ReadReq_accesses::1 175 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_misses::1 175 # number of ReadReq misses +system.iocache.ReadReq_misses::total 175 # number of ReadReq misses +system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses +system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. @@ -481,31 +619,57 @@ system.iocache.blocked::no_targets 0 # nu system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.demand_accesses 41727 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency 0 # average overall miss latency +system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 41727 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses +system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency +system.iocache.demand_avg_miss_latency::1 0 # average overall miss latency +system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.demand_hits 0 # number of demand (read+write) hits +system.iocache.demand_hits::0 0 # number of demand (read+write) hits +system.iocache.demand_hits::1 0 # number of demand (read+write) hits +system.iocache.demand_hits::total 0 # number of demand (read+write) hits system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.iocache.demand_miss_rate 1 # miss rate for demand accesses -system.iocache.demand_misses 41727 # number of demand (read+write) misses +system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses +system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses +system.iocache.demand_misses::0 0 # number of demand (read+write) misses +system.iocache.demand_misses::1 41727 # number of demand (read+write) misses +system.iocache.demand_misses::total 41727 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.overall_accesses 41727 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency 0 # average overall miss latency +system.iocache.occ_%::1 0.027215 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 0.435437 # Average occupied blocks per context +system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 41727 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses +system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency +system.iocache.overall_avg_miss_latency::1 0 # average overall miss latency +system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.iocache.overall_hits 0 # number of overall hits +system.iocache.overall_hits::0 0 # number of overall hits +system.iocache.overall_hits::1 0 # number of overall hits +system.iocache.overall_hits::total 0 # number of overall hits system.iocache.overall_miss_latency 0 # number of overall miss cycles -system.iocache.overall_miss_rate 1 # miss rate for overall accesses -system.iocache.overall_misses 41727 # number of overall misses +system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses +system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses +system.iocache.overall_misses::0 0 # number of overall misses +system.iocache.overall_misses::1 41727 # number of overall misses +system.iocache.overall_misses::total 41727 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses system.iocache.overall_mshr_misses 0 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -516,18 +680,37 @@ system.iocache.tagsinuse 0.435437 # Cy system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41520 # number of writebacks -system.l2c.ReadExReq_accesses 306247 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 306247 # number of ReadExReq misses -system.l2c.ReadReq_accesses 2724267 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits 1759731 # number of ReadReq hits -system.l2c.ReadReq_miss_rate 0.354053 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 964536 # number of ReadReq misses -system.l2c.UpgradeReq_accesses 125007 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 125007 # number of UpgradeReq misses -system.l2c.Writeback_accesses 427641 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 427641 # number of Writeback hits +system.l2c.ReadExReq_accesses::0 282023 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 24224 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 306247 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 282023 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 24224 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 306247 # number of ReadExReq misses +system.l2c.ReadReq_accesses::0 2581928 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 142339 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2724267 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits::0 1623113 # number of ReadReq hits +system.l2c.ReadReq_hits::1 136618 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1759731 # number of ReadReq hits +system.l2c.ReadReq_miss_rate::0 0.371356 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.040193 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 958815 # number of ReadReq misses +system.l2c.ReadReq_misses::1 5721 # number of ReadReq misses +system.l2c.ReadReq_misses::total 964536 # number of ReadReq misses +system.l2c.UpgradeReq_accesses::0 117429 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 7578 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 125007 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 117429 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 7578 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 125007 # number of UpgradeReq misses +system.l2c.Writeback_accesses::0 427641 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 427641 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 427641 # number of Writeback hits +system.l2c.Writeback_hits::total 427641 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.avg_refs 1.788900 # Average number of references to valid blocks. @@ -536,31 +719,73 @@ system.l2c.blocked::no_targets 0 # nu system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 3030514 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 0 # average overall miss latency +system.l2c.demand_accesses::0 2863951 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 166563 # number of demand (read+write) accesses +system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3030514 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 no_value # average overall miss latency +system.l2c.demand_avg_miss_latency::total no_value # average overall miss latency system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.demand_hits 1759731 # number of demand (read+write) hits +system.l2c.demand_hits::0 1623113 # number of demand (read+write) hits +system.l2c.demand_hits::1 136618 # number of demand (read+write) hits +system.l2c.demand_hits::2 0 # number of demand (read+write) hits +system.l2c.demand_hits::total 1759731 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.419329 # miss rate for demand accesses -system.l2c.demand_misses 1270783 # number of demand (read+write) misses +system.l2c.demand_miss_rate::0 0.433261 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.179782 # miss rate for demand accesses +system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses +system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses +system.l2c.demand_misses::0 1240838 # number of demand (read+write) misses +system.l2c.demand_misses::1 29945 # number of demand (read+write) misses +system.l2c.demand_misses::2 0 # number of demand (read+write) misses +system.l2c.demand_misses::total 1270783 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::2 no_value # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 3030514 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 0 # average overall miss latency +system.l2c.occ_%::0 0.079636 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.003863 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.382298 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 5219.016701 # Average occupied blocks per context +system.l2c.occ_blocks::1 253.146931 # Average occupied blocks per context +system.l2c.occ_blocks::2 25054.312004 # Average occupied blocks per context +system.l2c.overall_accesses::0 2863951 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 166563 # number of overall (read+write) accesses +system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3030514 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 no_value # average overall miss latency +system.l2c.overall_avg_miss_latency::total no_value # average overall miss latency system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.overall_hits 1759731 # number of overall hits +system.l2c.overall_hits::0 1623113 # number of overall hits +system.l2c.overall_hits::1 136618 # number of overall hits +system.l2c.overall_hits::2 0 # number of overall hits +system.l2c.overall_hits::total 1759731 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate 0.419329 # miss rate for overall accesses -system.l2c.overall_misses 1270783 # number of overall misses +system.l2c.overall_miss_rate::0 0.433261 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.179782 # miss rate for overall accesses +system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses +system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses +system.l2c.overall_misses::0 1240838 # number of overall misses +system.l2c.overall_misses::1 29945 # number of overall misses +system.l2c.overall_misses::2 0 # number of overall misses +system.l2c.overall_misses::total 1270783 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::2 no_value # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses system.l2c.overall_mshr_misses 0 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index d098a0440..5eca545be 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -8,11 +8,11 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux mem_mode=atomic -pal=/dist/m5/system/binaries/ts_osfpal +pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -74,7 +74,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -109,7 +109,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -157,7 +157,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.disk2] @@ -177,7 +177,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -205,7 +205,7 @@ hash_delay=1 latency=50000 max_miss_count=0 mshrs=20 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=500000 @@ -236,7 +236,7 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=92 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 @@ -303,7 +303,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout index ee81c2844..a264b4253 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 6 2009 11:02:48 -M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip -M5 started Jul 6 2009 11:10:46 -M5 executing on maize +M5 compiled Feb 24 2010 23:13:04 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 24 2010 23:13:11 +M5 executing on SC2B0619 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1829332258000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 0982d41b4..8a27a93dd 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -1,29 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 4370209 # Simulator instruction rate (inst/s) -host_mem_usage 276044 # Number of bytes of host memory used -host_seconds 13.74 # Real time elapsed on the host -host_tick_rate 133154437863 # Simulator tick rate (ticks/s) +host_inst_rate 2156504 # Simulator instruction rate (inst/s) +host_mem_usage 277176 # Number of bytes of host memory used +host_seconds 27.84 # Real time elapsed on the host +host_tick_rate 65706739181 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 60038305 # Number of instructions simulated sim_seconds 1.829332 # Number of seconds simulated sim_ticks 1829332258000 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses 200303 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 183141 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_rate 0.085680 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 17162 # number of LoadLockedReq misses -system.cpu.dcache.ReadReq_accesses 9529487 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_hits 7807782 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_rate 0.180671 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1721705 # number of ReadReq misses -system.cpu.dcache.StoreCondReq_accesses 199282 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits 169415 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_rate 0.149873 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses 29867 # number of StoreCondReq misses -system.cpu.dcache.WriteReq_accesses 6152574 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_hits 5753150 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_rate 0.064920 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 399424 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_accesses::0 200303 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits::0 183141 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.085680 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 17162 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses +system.cpu.dcache.ReadReq_accesses::0 9529487 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9529487 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits::0 7807782 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7807782 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_rate::0 0.180671 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 1721705 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1721705 # number of ReadReq misses +system.cpu.dcache.StoreCondReq_accesses::0 199282 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::0 169415 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 169415 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_rate::0 0.149873 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses::0 29867 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 29867 # number of StoreCondReq misses +system.cpu.dcache.WriteReq_accesses::0 6152574 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_hits::0 5753150 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5753150 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_rate::0 0.064920 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 399424 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 399424 # number of WriteReq misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 6.870767 # Average number of references to valid blocks. @@ -32,31 +44,57 @@ system.cpu.dcache.blocked::no_targets 0 # nu system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 15682061 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu.dcache.demand_accesses::0 15682061 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15682061 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.dcache.demand_hits 13560932 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::0 13560932 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13560932 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.135258 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2121129 # number of demand (read+write) misses +system.cpu.dcache.demand_miss_rate::0 0.135258 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.dcache.demand_misses::0 2121129 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2121129 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 15682061 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu.dcache.occ_%::0 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 511.997802 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 15682061 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 13560932 # number of overall hits +system.cpu.dcache.overall_hits::0 13560932 # number of overall hits +system.cpu.dcache.overall_hits::1 0 # number of overall hits +system.cpu.dcache.overall_hits::total 13560932 # number of overall hits system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.135258 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2121129 # number of overall misses +system.cpu.dcache.overall_miss_rate::0 0.135258 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.dcache.overall_misses::0 2121129 # number of overall misses +system.cpu.dcache.overall_misses::1 0 # number of overall misses +system.cpu.dcache.overall_misses::total 2121129 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -83,10 +121,13 @@ system.cpu.dtb.write_accesses 291931 # DT system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_hits 6352498 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses -system.cpu.icache.ReadReq_accesses 60050143 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_hits 59129922 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_rate 0.015324 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 920221 # number of ReadReq misses +system.cpu.icache.ReadReq_accesses::0 60050143 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 60050143 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_hits::0 59129922 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 59129922 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_rate::0 0.015324 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 920221 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 920221 # number of ReadReq misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 64.264250 # Average number of references to valid blocks. @@ -95,31 +136,57 @@ system.cpu.icache.blocked::no_targets 0 # nu system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 60050143 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu.icache.demand_accesses::0 60050143 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 60050143 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.icache.demand_hits 59129922 # number of demand (read+write) hits +system.cpu.icache.demand_hits::0 59129922 # number of demand (read+write) hits +system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 59129922 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.015324 # miss rate for demand accesses -system.cpu.icache.demand_misses 920221 # number of demand (read+write) misses +system.cpu.icache.demand_miss_rate::0 0.015324 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.icache.demand_misses::0 920221 # number of demand (read+write) misses +system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 920221 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 60050143 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu.icache.occ_%::0 0.998467 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 511.215243 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 60050143 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 59129922 # number of overall hits +system.cpu.icache.overall_hits::0 59129922 # number of overall hits +system.cpu.icache.overall_hits::1 0 # number of overall hits +system.cpu.icache.overall_hits::total 59129922 # number of overall hits system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.015324 # miss rate for overall accesses -system.cpu.icache.overall_misses 920221 # number of overall misses +system.cpu.icache.overall_miss_rate::0 0.015324 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.icache.overall_misses::0 920221 # number of overall misses +system.cpu.icache.overall_misses::1 0 # number of overall misses +system.cpu.icache.overall_misses::total 920221 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -247,12 +314,16 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iocache.ReadReq_accesses 174 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_misses 174 # number of ReadReq misses -system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_misses 41552 # number of WriteReq misses +system.iocache.ReadReq_accesses::1 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_misses::1 174 # number of ReadReq misses +system.iocache.ReadReq_misses::total 174 # number of ReadReq misses +system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses +system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. @@ -261,31 +332,57 @@ system.iocache.blocked::no_targets 0 # nu system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.demand_accesses 41726 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency 0 # average overall miss latency +system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 41726 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses +system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency +system.iocache.demand_avg_miss_latency::1 0 # average overall miss latency +system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.demand_hits 0 # number of demand (read+write) hits +system.iocache.demand_hits::0 0 # number of demand (read+write) hits +system.iocache.demand_hits::1 0 # number of demand (read+write) hits +system.iocache.demand_hits::total 0 # number of demand (read+write) hits system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.iocache.demand_miss_rate 1 # miss rate for demand accesses -system.iocache.demand_misses 41726 # number of demand (read+write) misses +system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses +system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses +system.iocache.demand_misses::0 0 # number of demand (read+write) misses +system.iocache.demand_misses::1 41726 # number of demand (read+write) misses +system.iocache.demand_misses::total 41726 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.overall_accesses 41726 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency 0 # average overall miss latency +system.iocache.occ_%::1 0.076598 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 1.225570 # Average occupied blocks per context +system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 41726 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses +system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency +system.iocache.overall_avg_miss_latency::1 0 # average overall miss latency +system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.iocache.overall_hits 0 # number of overall hits +system.iocache.overall_hits::0 0 # number of overall hits +system.iocache.overall_hits::1 0 # number of overall hits +system.iocache.overall_hits::total 0 # number of overall hits system.iocache.overall_miss_latency 0 # number of overall miss cycles -system.iocache.overall_miss_rate 1 # miss rate for overall accesses -system.iocache.overall_misses 41726 # number of overall misses +system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses +system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses +system.iocache.overall_misses::0 0 # number of overall misses +system.iocache.overall_misses::1 41726 # number of overall misses +system.iocache.overall_misses::total 41726 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses system.iocache.overall_mshr_misses 0 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -296,18 +393,27 @@ system.iocache.tagsinuse 1.225570 # Cy system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses 304346 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 304346 # number of ReadExReq misses -system.l2c.ReadReq_accesses 2659071 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits 1696652 # number of ReadReq hits -system.l2c.ReadReq_miss_rate 0.361938 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 962419 # number of ReadReq misses -system.l2c.UpgradeReq_accesses 124945 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 124945 # number of UpgradeReq misses -system.l2c.Writeback_accesses 428893 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 428893 # number of Writeback hits +system.l2c.ReadExReq_accesses::0 304346 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 304346 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 304346 # number of ReadExReq misses +system.l2c.ReadReq_accesses::0 2659071 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2659071 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits::0 1696652 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1696652 # number of ReadReq hits +system.l2c.ReadReq_miss_rate::0 0.361938 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 962419 # number of ReadReq misses +system.l2c.ReadReq_misses::total 962419 # number of ReadReq misses +system.l2c.UpgradeReq_accesses::0 124945 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 124945 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 124945 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 124945 # number of UpgradeReq misses +system.l2c.Writeback_accesses::0 428893 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 428893 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 428893 # number of Writeback hits +system.l2c.Writeback_hits::total 428893 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.avg_refs 1.727246 # Average number of references to valid blocks. @@ -316,31 +422,59 @@ system.l2c.blocked::no_targets 0 # nu system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2963417 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 0 # average overall miss latency +system.l2c.demand_accesses::0 2963417 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2963417 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 no_value # average overall miss latency +system.l2c.demand_avg_miss_latency::total no_value # average overall miss latency system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.demand_hits 1696652 # number of demand (read+write) hits +system.l2c.demand_hits::0 1696652 # number of demand (read+write) hits +system.l2c.demand_hits::1 0 # number of demand (read+write) hits +system.l2c.demand_hits::total 1696652 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.427468 # miss rate for demand accesses -system.l2c.demand_misses 1266765 # number of demand (read+write) misses +system.l2c.demand_miss_rate::0 0.427468 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses +system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses +system.l2c.demand_misses::0 1266765 # number of demand (read+write) misses +system.l2c.demand_misses::1 0 # number of demand (read+write) misses +system.l2c.demand_misses::total 1266765 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 2963417 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 0 # average overall miss latency +system.l2c.occ_%::0 0.077203 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.384049 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 5059.576308 # Average occupied blocks per context +system.l2c.occ_blocks::1 25169.009297 # Average occupied blocks per context +system.l2c.overall_accesses::0 2963417 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2963417 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 no_value # average overall miss latency +system.l2c.overall_avg_miss_latency::total no_value # average overall miss latency system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.overall_hits 1696652 # number of overall hits +system.l2c.overall_hits::0 1696652 # number of overall hits +system.l2c.overall_hits::1 0 # number of overall hits +system.l2c.overall_hits::total 1696652 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate 0.427468 # miss rate for overall accesses -system.l2c.overall_misses 1266765 # number of overall misses +system.l2c.overall_miss_rate::0 0.427468 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses +system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses +system.l2c.overall_misses::0 1266765 # number of overall misses +system.l2c.overall_misses::1 0 # number of overall misses +system.l2c.overall_misses::total 1266765 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses system.l2c.overall_mshr_misses 0 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 85ee22259..9ac931352 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -8,11 +8,11 @@ type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux mem_mode=timing -pal=/dist/m5/system/binaries/ts_osfpal +pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -71,7 +71,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -106,7 +106,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -175,7 +175,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -210,7 +210,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -258,7 +258,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.disk2] @@ -278,7 +278,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -306,7 +306,7 @@ hash_delay=1 latency=50000 max_miss_count=0 mshrs=20 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=500000 @@ -337,7 +337,7 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=92 -prefetch_cache_check_push=true +num_cpus=2 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 @@ -404,7 +404,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout index a32910fc6..e1106068b 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 6 2009 11:02:48 -M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip -M5 started Jul 6 2009 11:10:47 -M5 executing on maize +M5 compiled Feb 24 2010 23:13:04 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 24 2010 23:33:27 +M5 executing on SC2B0619 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1972135461000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index cacc7d9bd..2f0d6d26e 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,55 +1,83 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1978894 # Simulator instruction rate (inst/s) -host_mem_usage 274156 # Number of bytes of host memory used -host_seconds 30.03 # Real time elapsed on the host -host_tick_rate 65677834484 # Simulator tick rate (ticks/s) +host_inst_rate 561145 # Simulator instruction rate (inst/s) +host_mem_usage 275328 # Number of bytes of host memory used +host_seconds 105.89 # Real time elapsed on the host +host_tick_rate 18624028525 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 59420593 # Number of instructions simulated sim_seconds 1.972135 # Number of seconds simulated sim_ticks 1972135461000 # Number of ticks simulated -system.cpu0.dcache.LoadLockedReq_accesses 192630 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_avg_miss_latency 14259.465279 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_accesses::0 192630 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 192630 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14259.465279 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11259.465279 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_hits 175911 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::0 175911 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 175911 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_miss_latency 238404000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_rate 0.086793 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_misses 16719 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.086793 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses::0 16719 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 16719 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 188247000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.086793 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.086793 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_misses 16719 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.ReadReq_accesses 8488393 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency 25694.266311 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_accesses::0 8488393 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8488393 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency::0 25694.266311 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 22694.226839 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_hits 7449690 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::0 7449690 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7449690 # number of ReadReq hits system.cpu0.dcache.ReadReq_miss_latency 26688711500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate 0.122367 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 1038703 # number of ReadReq misses +system.cpu0.dcache.ReadReq_miss_rate::0 0.122367 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses::0 1038703 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1038703 # number of ReadReq misses system.cpu0.dcache.ReadReq_mshr_miss_latency 23572561500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate 0.122367 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.122367 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_misses 1038703 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 883604000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_accesses 191666 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_avg_miss_latency 55344.484086 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_accesses::0 191666 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 191666 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 55344.484086 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 52344.484086 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_hits 163357 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::0 163357 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 163357 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_miss_latency 1566747000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_rate 0.147700 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_misses 28309 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.147700 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses::0 28309 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 28309 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_mshr_miss_latency 1481820000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.147700 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.147700 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_misses 28309 # number of StoreCondReq MSHR misses -system.cpu0.dcache.WriteReq_accesses 5847430 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency 55891.373878 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_accesses::0 5847430 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5847430 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency::0 55891.373878 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 52891.373878 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_hits 5468175 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::0 5468175 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5468175 # number of WriteReq hits system.cpu0.dcache.WriteReq_miss_latency 21197083000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate 0.064858 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 379255 # number of WriteReq misses +system.cpu0.dcache.WriteReq_miss_rate::0 0.064858 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses::0 379255 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 379255 # number of WriteReq misses system.cpu0.dcache.WriteReq_mshr_miss_latency 20059318000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate 0.064858 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.064858 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_misses 379255 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1240870000 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -60,31 +88,57 @@ system.cpu0.dcache.blocked::no_targets 0 # nu system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 14335823 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency 33770.954076 # average overall miss latency +system.cpu0.dcache.demand_accesses::0 14335823 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14335823 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency::0 33770.954076 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency 30770.925161 # average overall mshr miss latency -system.cpu0.dcache.demand_hits 12917865 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::0 12917865 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12917865 # number of demand (read+write) hits system.cpu0.dcache.demand_miss_latency 47885794500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.098910 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 1417958 # number of demand (read+write) misses +system.cpu0.dcache.demand_miss_rate::0 0.098910 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu0.dcache.demand_misses::0 1417958 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1417958 # number of demand (read+write) misses system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_miss_latency 43631879500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate 0.098910 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::0 0.098910 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_misses 1417958 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.overall_accesses 14335823 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency 33770.954076 # average overall miss latency +system.cpu0.dcache.occ_%::0 0.983612 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::0 503.609177 # Average occupied blocks per context +system.cpu0.dcache.overall_accesses::0 14335823 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14335823 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency::0 33770.954076 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency 30770.925161 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 12917865 # number of overall hits +system.cpu0.dcache.overall_hits::0 12917865 # number of overall hits +system.cpu0.dcache.overall_hits::1 0 # number of overall hits +system.cpu0.dcache.overall_hits::total 12917865 # number of overall hits system.cpu0.dcache.overall_miss_latency 47885794500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.098910 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 1417958 # number of overall misses +system.cpu0.dcache.overall_miss_rate::0 0.098910 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu0.dcache.overall_misses::0 1417958 # number of overall misses +system.cpu0.dcache.overall_misses::1 0 # number of overall misses +system.cpu0.dcache.overall_misses::total 1417958 # number of overall misses system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_miss_latency 43631879500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate 0.098910 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::0 0.098910 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_misses 1417958 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_latency 2124474000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -111,15 +165,22 @@ system.cpu0.dtb.write_accesses 195659 # DT system.cpu0.dtb.write_acv 115 # DTB write access violations system.cpu0.dtb.write_hits 6040102 # DTB write hits system.cpu0.dtb.write_misses 798 # DTB write misses -system.cpu0.icache.ReadReq_accesses 54164416 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency 14681.637172 # average ReadReq miss latency +system.cpu0.icache.ReadReq_accesses::0 54164416 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 54164416 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency::0 14681.637172 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11680.885800 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits 53248092 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::0 53248092 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 53248092 # number of ReadReq hits system.cpu0.icache.ReadReq_miss_latency 13453136500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate 0.016917 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses 916324 # number of ReadReq misses +system.cpu0.icache.ReadReq_miss_rate::0 0.016917 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses::0 916324 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 916324 # number of ReadReq misses system.cpu0.icache.ReadReq_mshr_miss_latency 10703476000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate 0.016917 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.016917 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_misses 916324 # number of ReadReq MSHR misses system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked @@ -129,31 +190,57 @@ system.cpu0.icache.blocked::no_targets 0 # nu system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 54164416 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency 14681.637172 # average overall miss latency +system.cpu0.icache.demand_accesses::0 54164416 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 54164416 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency::0 14681.637172 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu0.icache.demand_avg_mshr_miss_latency 11680.885800 # average overall mshr miss latency -system.cpu0.icache.demand_hits 53248092 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::0 53248092 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 53248092 # number of demand (read+write) hits system.cpu0.icache.demand_miss_latency 13453136500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate 0.016917 # miss rate for demand accesses -system.cpu0.icache.demand_misses 916324 # number of demand (read+write) misses +system.cpu0.icache.demand_miss_rate::0 0.016917 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu0.icache.demand_misses::0 916324 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 916324 # number of demand (read+write) misses system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu0.icache.demand_mshr_miss_latency 10703476000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate 0.016917 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::0 0.016917 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_misses 916324 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.overall_accesses 54164416 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency 14681.637172 # average overall miss latency +system.cpu0.icache.occ_%::0 0.993443 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::0 508.642782 # Average occupied blocks per context +system.cpu0.icache.overall_accesses::0 54164416 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 54164416 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency::0 14681.637172 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu0.icache.overall_avg_mshr_miss_latency 11680.885800 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 53248092 # number of overall hits +system.cpu0.icache.overall_hits::0 53248092 # number of overall hits +system.cpu0.icache.overall_hits::1 0 # number of overall hits +system.cpu0.icache.overall_hits::total 53248092 # number of overall hits system.cpu0.icache.overall_miss_latency 13453136500 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate 0.016917 # miss rate for overall accesses -system.cpu0.icache.overall_misses 916324 # number of overall misses +system.cpu0.icache.overall_miss_rate::0 0.016917 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu0.icache.overall_misses::0 916324 # number of overall misses +system.cpu0.icache.overall_misses::1 0 # number of overall misses +system.cpu0.icache.overall_misses::total 916324 # number of overall misses system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu0.icache.overall_mshr_miss_latency 10703476000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate 0.016917 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::0 0.016917 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_misses 916324 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -274,48 +361,76 @@ system.cpu0.not_idle_fraction 0.066840 # Pe system.cpu0.numCycles 3944270922 # number of cpu cycles simulated system.cpu0.num_insts 54155641 # Number of instructions executed system.cpu0.num_refs 14946215 # Number of memory references -system.cpu1.dcache.LoadLockedReq_accesses 12334 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_avg_miss_latency 13303.501946 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_accesses::0 12334 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 12334 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13303.501946 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 10303.501946 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_hits 11306 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::0 11306 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 11306 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_miss_latency 13676000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_rate 0.083347 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_misses 1028 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.083347 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_misses::0 1028 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 1028 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 10592000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate 0.083347 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.083347 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_misses 1028 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.ReadReq_accesses 1020543 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency 15771.782317 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_accesses::0 1020543 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1020543 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency::0 15771.782317 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12771.684387 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_hits 984803 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::0 984803 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 984803 # number of ReadReq hits system.cpu1.dcache.ReadReq_miss_latency 563683500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate 0.035021 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses 35740 # number of ReadReq misses +system.cpu1.dcache.ReadReq_miss_rate::0 0.035021 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses::0 35740 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 35740 # number of ReadReq misses system.cpu1.dcache.ReadReq_mshr_miss_latency 456460000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate 0.035021 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.035021 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_misses 35740 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 12526000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.StoreCondReq_accesses 12270 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_avg_miss_latency 46841.453344 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_accesses::0 12270 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 12270 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 46841.453344 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 43841.453344 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_hits 9848 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::0 9848 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 9848 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_miss_latency 113450000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_rate 0.197392 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_misses 2422 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.197392 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses::0 2422 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 2422 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_mshr_miss_latency 106184000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.197392 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.197392 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_misses 2422 # number of StoreCondReq MSHR misses -system.cpu1.dcache.WriteReq_accesses 650008 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency 54644.846691 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_accesses::0 650008 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 650008 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency::0 54644.846691 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 51644.846691 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_hits 623656 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::0 623656 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 623656 # number of WriteReq hits system.cpu1.dcache.WriteReq_miss_latency 1440001000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate 0.040541 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses 26352 # number of WriteReq misses +system.cpu1.dcache.WriteReq_miss_rate::0 0.040541 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses::0 26352 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 26352 # number of WriteReq misses system.cpu1.dcache.WriteReq_mshr_miss_latency 1360945000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate 0.040541 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.040541 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_misses 26352 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 303019000 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -326,31 +441,57 @@ system.cpu1.dcache.blocked::no_targets 0 # nu system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses 1670551 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency 32269.608001 # average overall miss latency +system.cpu1.dcache.demand_accesses::0 1670551 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 1670551 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency::0 32269.608001 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency 29269.551633 # average overall mshr miss latency -system.cpu1.dcache.demand_hits 1608459 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::0 1608459 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1608459 # number of demand (read+write) hits system.cpu1.dcache.demand_miss_latency 2003684500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.037169 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 62092 # number of demand (read+write) misses +system.cpu1.dcache.demand_miss_rate::0 0.037169 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu1.dcache.demand_misses::0 62092 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 62092 # number of demand (read+write) misses system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu1.dcache.demand_mshr_miss_latency 1817405000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate 0.037169 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::0 0.037169 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_misses 62092 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.overall_accesses 1670551 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency 32269.608001 # average overall miss latency +system.cpu1.dcache.occ_%::0 0.759529 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 388.878897 # Average occupied blocks per context +system.cpu1.dcache.overall_accesses::0 1670551 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 1670551 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency::0 32269.608001 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency 29269.551633 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 1608459 # number of overall hits +system.cpu1.dcache.overall_hits::0 1608459 # number of overall hits +system.cpu1.dcache.overall_hits::1 0 # number of overall hits +system.cpu1.dcache.overall_hits::total 1608459 # number of overall hits system.cpu1.dcache.overall_miss_latency 2003684500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.037169 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 62092 # number of overall misses +system.cpu1.dcache.overall_miss_rate::0 0.037169 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu1.dcache.overall_misses::0 62092 # number of overall misses +system.cpu1.dcache.overall_misses::1 0 # number of overall misses +system.cpu1.dcache.overall_misses::total 62092 # number of overall misses system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu1.dcache.overall_mshr_miss_latency 1817405000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate 0.037169 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::0 0.037169 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_misses 62092 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_latency 315545000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -377,15 +518,22 @@ system.cpu1.dtb.write_accesses 97040 # DT system.cpu1.dtb.write_acv 48 # DTB write access violations system.cpu1.dtb.write_hits 664141 # DTB write hits system.cpu1.dtb.write_misses 356 # DTB write misses -system.cpu1.icache.ReadReq_accesses 5268142 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency 14617.211446 # average ReadReq miss latency +system.cpu1.icache.ReadReq_accesses::0 5268142 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 5268142 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency::0 14617.211446 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11616.771124 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits 5180706 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::0 5180706 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 5180706 # number of ReadReq hits system.cpu1.icache.ReadReq_miss_latency 1278070500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate 0.016597 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses 87436 # number of ReadReq misses +system.cpu1.icache.ReadReq_miss_rate::0 0.016597 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses::0 87436 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 87436 # number of ReadReq misses system.cpu1.icache.ReadReq_mshr_miss_latency 1015724000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate 0.016597 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.016597 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_misses 87436 # number of ReadReq MSHR misses system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked @@ -395,31 +543,57 @@ system.cpu1.icache.blocked::no_targets 0 # nu system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses 5268142 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency 14617.211446 # average overall miss latency +system.cpu1.icache.demand_accesses::0 5268142 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 5268142 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency::0 14617.211446 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu1.icache.demand_avg_mshr_miss_latency 11616.771124 # average overall mshr miss latency -system.cpu1.icache.demand_hits 5180706 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::0 5180706 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 5180706 # number of demand (read+write) hits system.cpu1.icache.demand_miss_latency 1278070500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate 0.016597 # miss rate for demand accesses -system.cpu1.icache.demand_misses 87436 # number of demand (read+write) misses +system.cpu1.icache.demand_miss_rate::0 0.016597 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu1.icache.demand_misses::0 87436 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 87436 # number of demand (read+write) misses system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu1.icache.demand_mshr_miss_latency 1015724000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate 0.016597 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::0 0.016597 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_misses 87436 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.overall_accesses 5268142 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency 14617.211446 # average overall miss latency +system.cpu1.icache.occ_%::0 0.819152 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 419.405627 # Average occupied blocks per context +system.cpu1.icache.overall_accesses::0 5268142 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 5268142 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency::0 14617.211446 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu1.icache.overall_avg_mshr_miss_latency 11616.771124 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits 5180706 # number of overall hits +system.cpu1.icache.overall_hits::0 5180706 # number of overall hits +system.cpu1.icache.overall_hits::1 0 # number of overall hits +system.cpu1.icache.overall_hits::total 5180706 # number of overall hits system.cpu1.icache.overall_miss_latency 1278070500 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate 0.016597 # miss rate for overall accesses -system.cpu1.icache.overall_misses 87436 # number of overall misses +system.cpu1.icache.overall_miss_rate::0 0.016597 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu1.icache.overall_misses::0 87436 # number of overall misses +system.cpu1.icache.overall_misses::1 0 # number of overall misses +system.cpu1.icache.overall_misses::total 87436 # number of overall misses system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu1.icache.overall_mshr_miss_latency 1015724000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate 0.016597 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::0 0.016597 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_misses 87436 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -539,23 +713,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iocache.ReadReq_accesses 178 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_avg_miss_latency 115196.617978 # average ReadReq miss latency +system.iocache.ReadReq_accesses::1 178 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115196.617978 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.iocache.ReadReq_avg_mshr_miss_latency 63196.617978 # average ReadReq mshr miss latency system.iocache.ReadReq_miss_latency 20504998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_misses 178 # number of ReadReq misses +system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_misses::1 178 # number of ReadReq misses +system.iocache.ReadReq_misses::total 178 # number of ReadReq misses system.iocache.ReadReq_mshr_miss_latency 11248998 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_misses 178 # number of ReadReq MSHR misses -system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_avg_miss_latency 137902.310503 # average WriteReq miss latency +system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137902.310503 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.iocache.WriteReq_avg_mshr_miss_latency 85898.702349 # average WriteReq mshr miss latency system.iocache.WriteReq_miss_latency 5730116806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_misses 41552 # number of WriteReq misses +system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses +system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses system.iocache.WriteReq_mshr_miss_latency 3569262880 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses system.iocache.avg_blocked_cycles::no_mshrs 6169.706090 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked @@ -565,31 +751,57 @@ system.iocache.blocked::no_targets 0 # nu system.iocache.blocked_cycles::no_mshrs 64528956 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.demand_accesses 41730 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency 137805.458998 # average overall miss latency +system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 41730 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses +system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137805.458998 # average overall miss latency +system.iocache.demand_avg_miss_latency::total inf # average overall miss latency system.iocache.demand_avg_mshr_miss_latency 85801.866235 # average overall mshr miss latency -system.iocache.demand_hits 0 # number of demand (read+write) hits +system.iocache.demand_hits::0 0 # number of demand (read+write) hits +system.iocache.demand_hits::1 0 # number of demand (read+write) hits +system.iocache.demand_hits::total 0 # number of demand (read+write) hits system.iocache.demand_miss_latency 5750621804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_rate 1 # miss rate for demand accesses -system.iocache.demand_misses 41730 # number of demand (read+write) misses +system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses +system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses +system.iocache.demand_misses::0 0 # number of demand (read+write) misses +system.iocache.demand_misses::1 41730 # number of demand (read+write) misses +system.iocache.demand_misses::total 41730 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.iocache.demand_mshr_miss_latency 3580511878 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.iocache.demand_mshr_misses 41730 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.overall_accesses 41730 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency 137805.458998 # average overall miss latency +system.iocache.occ_%::1 0.036380 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 0.582075 # Average occupied blocks per context +system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 41730 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses +system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137805.458998 # average overall miss latency +system.iocache.overall_avg_miss_latency::total inf # average overall miss latency system.iocache.overall_avg_mshr_miss_latency 85801.866235 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.iocache.overall_hits 0 # number of overall hits +system.iocache.overall_hits::0 0 # number of overall hits +system.iocache.overall_hits::1 0 # number of overall hits +system.iocache.overall_hits::total 0 # number of overall hits system.iocache.overall_miss_latency 5750621804 # number of overall miss cycles -system.iocache.overall_miss_rate 1 # miss rate for overall accesses -system.iocache.overall_misses 41730 # number of overall misses +system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses +system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses +system.iocache.overall_misses::0 0 # number of overall misses +system.iocache.overall_misses::1 41730 # number of overall misses +system.iocache.overall_misses::total 41730 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits system.iocache.overall_mshr_miss_latency 3580511878 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.iocache.overall_mshr_misses 41730 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -600,41 +812,78 @@ system.iocache.tagsinuse 0.582075 # Cy system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 1762323389000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41520 # number of writebacks -system.l2c.ReadExReq_accesses 306814 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 52002.656333 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 285538 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 21276 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 306814 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 55877.476903 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 749912.718556 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_mshr_miss_latency 40002.656333 # average ReadExReq mshr miss latency system.l2c.ReadExReq_miss_latency 15955143000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 306814 # number of ReadExReq misses +system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 285538 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 21276 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 306814 # number of ReadExReq misses system.l2c.ReadExReq_mshr_miss_latency 12273375000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 1.074512 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 14.420662 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_misses 306814 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 2090305 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 52016.275832 # average ReadReq miss latency +system.l2c.ReadReq_accesses::0 1969770 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 120535 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2090305 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52549.257150 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 5128541.212316 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.l2c.ReadReq_avg_mshr_miss_latency 40016.323583 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits 1782886 # number of ReadReq hits +system.l2c.ReadReq_hits::0 1665469 # number of ReadReq hits +system.l2c.ReadReq_hits::1 117417 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1782886 # number of ReadReq hits system.l2c.ReadReq_miss_latency 15990791500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.147069 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 307419 # number of ReadReq misses +system.l2c.ReadReq_miss_rate::0 0.154486 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.025868 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 304301 # number of ReadReq misses +system.l2c.ReadReq_misses::1 3118 # number of ReadReq misses +system.l2c.ReadReq_misses::total 307419 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_miss_latency 12301338000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.147064 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::0 0.156063 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 2.550363 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_misses 307408 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_uncacheable_latency 802543000 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses 127238 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 50741.170091 # average UpgradeReq miss latency +system.l2c.UpgradeReq_accesses::0 120870 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 6368 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 127238 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 53414.453545 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 1013851.287688 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency 40005.242145 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_miss_latency 6456205000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 127238 # number of UpgradeReq misses +system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 120870 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 6368 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 127238 # number of UpgradeReq misses system.l2c.UpgradeReq_mshr_miss_latency 5090187000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 1.052685 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 19.980842 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_misses 127238 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_mshr_uncacheable_latency 1394774000 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses 430351 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 430351 # number of Writeback hits +system.l2c.Writeback_accesses::0 430351 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 430351 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 430351 # number of Writeback hits +system.l2c.Writeback_hits::total 430351 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.avg_refs 4.554189 # Average number of references to valid blocks. @@ -643,31 +892,73 @@ system.l2c.blocked::no_targets 0 # nu system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2397119 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 52009.472790 # average overall miss latency +system.l2c.demand_accesses::0 2255308 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 141811 # number of demand (read+write) accesses +system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2397119 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 54160.431067 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 1309581.638928 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency +system.l2c.demand_avg_miss_latency::total inf # average overall miss latency system.l2c.demand_avg_mshr_miss_latency 40009.496566 # average overall mshr miss latency -system.l2c.demand_hits 1782886 # number of demand (read+write) hits +system.l2c.demand_hits::0 1665469 # number of demand (read+write) hits +system.l2c.demand_hits::1 117417 # number of demand (read+write) hits +system.l2c.demand_hits::2 0 # number of demand (read+write) hits +system.l2c.demand_hits::total 1782886 # number of demand (read+write) hits system.l2c.demand_miss_latency 31945934500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.256238 # miss rate for demand accesses -system.l2c.demand_misses 614233 # number of demand (read+write) misses +system.l2c.demand_miss_rate::0 0.261534 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.172018 # miss rate for demand accesses +system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses +system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses +system.l2c.demand_misses::0 589839 # number of demand (read+write) misses +system.l2c.demand_misses::1 24394 # number of demand (read+write) misses +system.l2c.demand_misses::2 0 # number of demand (read+write) misses +system.l2c.demand_misses::total 614233 # number of demand (read+write) misses system.l2c.demand_mshr_hits 11 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 24574713000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.256233 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 0.272345 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 4.331272 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.l2c.demand_mshr_misses 614222 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 2397119 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 52009.472790 # average overall miss latency +system.l2c.occ_%::0 0.090499 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.002713 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.377667 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 5930.966720 # Average occupied blocks per context +system.l2c.occ_blocks::1 177.784506 # Average occupied blocks per context +system.l2c.occ_blocks::2 24750.754224 # Average occupied blocks per context +system.l2c.overall_accesses::0 2255308 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 141811 # number of overall (read+write) accesses +system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2397119 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 54160.431067 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 1309581.638928 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency +system.l2c.overall_avg_miss_latency::total inf # average overall miss latency system.l2c.overall_avg_mshr_miss_latency 40009.496566 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits 1782886 # number of overall hits +system.l2c.overall_hits::0 1665469 # number of overall hits +system.l2c.overall_hits::1 117417 # number of overall hits +system.l2c.overall_hits::2 0 # number of overall hits +system.l2c.overall_hits::total 1782886 # number of overall hits system.l2c.overall_miss_latency 31945934500 # number of overall miss cycles -system.l2c.overall_miss_rate 0.256238 # miss rate for overall accesses -system.l2c.overall_misses 614233 # number of overall misses +system.l2c.overall_miss_rate::0 0.261534 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.172018 # miss rate for overall accesses +system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses +system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses +system.l2c.overall_misses::0 589839 # number of overall misses +system.l2c.overall_misses::1 24394 # number of overall misses +system.l2c.overall_misses::2 0 # number of overall misses +system.l2c.overall_misses::total 614233 # number of overall misses system.l2c.overall_mshr_hits 11 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 24574713000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.256233 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 0.272345 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 4.331272 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.l2c.overall_mshr_misses 614222 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 2197317000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index 64bcede47..e4db07faf 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -8,11 +8,11 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux mem_mode=timing -pal=/dist/m5/system/binaries/ts_osfpal +pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -71,7 +71,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -106,7 +106,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -154,7 +154,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.disk2] @@ -174,7 +174,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -202,7 +202,7 @@ hash_delay=1 latency=50000 max_miss_count=0 mshrs=20 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=500000 @@ -233,7 +233,7 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=92 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 @@ -300,7 +300,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout index 5109c8767..36f5fe7a9 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 6 2009 11:02:48 -M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip -M5 started Jul 6 2009 11:10:46 -M5 executing on maize +M5 compiled Feb 24 2010 23:13:04 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 24 2010 23:13:12 +M5 executing on SC2B0619 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1930164593000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 3dedbe829..fafd614fd 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,55 +1,83 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1870819 # Simulator instruction rate (inst/s) -host_mem_usage 272832 # Number of bytes of host memory used -host_seconds 30.04 # Real time elapsed on the host -host_tick_rate 64245310717 # Simulator tick rate (ticks/s) +host_inst_rate 828053 # Simulator instruction rate (inst/s) +host_mem_usage 274124 # Number of bytes of host memory used +host_seconds 67.88 # Real time elapsed on the host +host_tick_rate 28436098912 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 56205703 # Number of instructions simulated sim_seconds 1.930165 # Number of seconds simulated sim_ticks 1930164593000 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses 200404 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 14361.546017 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::0 200404 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200404 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14361.546017 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11361.546017 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits 183095 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::0 183095 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183095 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_miss_latency 248584000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate 0.086371 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 17309 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.086371 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 17309 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17309 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_mshr_miss_latency 196657000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.086371 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.086371 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_misses 17309 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses 8888653 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 25452.354477 # average ReadReq miss latency +system.cpu.dcache.ReadReq_accesses::0 8888653 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8888653 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 25452.354477 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22452.311493 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits 7818479 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::0 7818479 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7818479 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 27238448000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.120398 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1070174 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_rate::0 0.120398 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 1070174 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1070174 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_miss_latency 24027880000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.120398 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.120398 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 1070174 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable_latency 862763000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses 199383 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_avg_miss_latency 56004.366085 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_accesses::0 199383 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199383 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_avg_miss_latency::0 56004.366085 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53004.366085 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_hits 169379 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::0 169379 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 169379 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_miss_latency 1680355000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_rate 0.150484 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses 30004 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_miss_rate::0 0.150484 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses::0 30004 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 30004 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_mshr_miss_latency 1590343000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.150484 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.150484 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_misses 30004 # number of StoreCondReq MSHR misses -system.cpu.dcache.WriteReq_accesses 6160337 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56004.022652 # average WriteReq miss latency +system.cpu.dcache.WriteReq_accesses::0 6160337 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6160337 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 56004.022652 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53004.022652 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits 5759482 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::0 5759482 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5759482 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 22449492500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.065070 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 400855 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_rate::0 0.065070 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 400855 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 400855 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_miss_latency 21246927500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.065070 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.065070 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 400855 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1201243500 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -60,31 +88,57 @@ system.cpu.dcache.blocked::no_targets 0 # nu system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 15048990 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 33777.675695 # average overall miss latency +system.cpu.dcache.demand_accesses::0 15048990 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15048990 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 33777.675695 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 30777.644424 # average overall mshr miss latency -system.cpu.dcache.demand_hits 13577961 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::0 13577961 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13577961 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 49687940500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.097749 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1471029 # number of demand (read+write) misses +system.cpu.dcache.demand_miss_rate::0 0.097749 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.dcache.demand_misses::0 1471029 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1471029 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 45274807500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.097749 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.097749 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 1471029 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 15048990 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 33777.675695 # average overall miss latency +system.cpu.dcache.occ_%::0 0.999969 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 511.984142 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 15048990 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15048990 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 33777.675695 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 30777.644424 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 13577961 # number of overall hits +system.cpu.dcache.overall_hits::0 13577961 # number of overall hits +system.cpu.dcache.overall_hits::1 0 # number of overall hits +system.cpu.dcache.overall_hits::total 13577961 # number of overall hits system.cpu.dcache.overall_miss_latency 49687940500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.097749 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1471029 # number of overall misses +system.cpu.dcache.overall_miss_rate::0 0.097749 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.dcache.overall_misses::0 1471029 # number of overall misses +system.cpu.dcache.overall_misses::1 0 # number of overall misses +system.cpu.dcache.overall_misses::total 1471029 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 45274807500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.097749 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.097749 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 1471029 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 2064006500 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -111,15 +165,22 @@ system.cpu.dtb.write_accesses 291931 # DT system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_hits 6360093 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses -system.cpu.icache.ReadReq_accesses 56217537 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 14711.221983 # average ReadReq miss latency +system.cpu.icache.ReadReq_accesses::0 56217537 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56217537 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 14711.221983 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 11710.491665 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 55286436 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::0 55286436 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55286436 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 13697633500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.016562 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 931101 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_rate::0 0.016562 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 931101 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 931101 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_miss_latency 10903650500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.016562 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.016562 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 931101 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked @@ -129,31 +190,57 @@ system.cpu.icache.blocked::no_targets 0 # nu system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 56217537 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 14711.221983 # average overall miss latency +system.cpu.icache.demand_accesses::0 56217537 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56217537 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 14711.221983 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 11710.491665 # average overall mshr miss latency -system.cpu.icache.demand_hits 55286436 # number of demand (read+write) hits +system.cpu.icache.demand_hits::0 55286436 # number of demand (read+write) hits +system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55286436 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 13697633500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.016562 # miss rate for demand accesses -system.cpu.icache.demand_misses 931101 # number of demand (read+write) misses +system.cpu.icache.demand_miss_rate::0 0.016562 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.icache.demand_misses::0 931101 # number of demand (read+write) misses +system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 931101 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 10903650500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.016562 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.016562 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 931101 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 56217537 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 14711.221983 # average overall miss latency +system.cpu.icache.occ_%::0 0.993281 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 508.559728 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 56217537 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56217537 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 14711.221983 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 11710.491665 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 55286436 # number of overall hits +system.cpu.icache.overall_hits::0 55286436 # number of overall hits +system.cpu.icache.overall_hits::1 0 # number of overall hits +system.cpu.icache.overall_hits::total 55286436 # number of overall hits system.cpu.icache.overall_miss_latency 13697633500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.016562 # miss rate for overall accesses -system.cpu.icache.overall_misses 931101 # number of overall misses +system.cpu.icache.overall_miss_rate::0 0.016562 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.icache.overall_misses::0 931101 # number of overall misses +system.cpu.icache.overall_misses::1 0 # number of overall misses +system.cpu.icache.overall_misses::total 931101 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 10903650500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.016562 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.016562 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 931101 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -281,23 +368,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iocache.ReadReq_accesses 173 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_avg_miss_latency 115254.323699 # average ReadReq miss latency +system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115254.323699 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.iocache.ReadReq_avg_mshr_miss_latency 63254.323699 # average ReadReq mshr miss latency system.iocache.ReadReq_miss_latency 19938998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_misses 173 # number of ReadReq misses +system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_misses::1 173 # number of ReadReq misses +system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.ReadReq_mshr_miss_latency 10942998 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses -system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_avg_miss_latency 137876.559636 # average WriteReq miss latency +system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137876.559636 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.iocache.WriteReq_avg_mshr_miss_latency 85873.072921 # average WriteReq mshr miss latency system.iocache.WriteReq_miss_latency 5729046806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_misses 41552 # number of WriteReq misses +system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses +system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses system.iocache.WriteReq_mshr_miss_latency 3568197926 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses system.iocache.avg_blocked_cycles::no_mshrs 6163.674943 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked @@ -307,31 +406,57 @@ system.iocache.blocked::no_targets 0 # nu system.iocache.blocked_cycles::no_mshrs 64546004 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.demand_accesses 41725 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency 137782.763427 # average overall miss latency +system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses +system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137782.763427 # average overall miss latency +system.iocache.demand_avg_miss_latency::total inf # average overall miss latency system.iocache.demand_avg_mshr_miss_latency 85779.291168 # average overall mshr miss latency -system.iocache.demand_hits 0 # number of demand (read+write) hits +system.iocache.demand_hits::0 0 # number of demand (read+write) hits +system.iocache.demand_hits::1 0 # number of demand (read+write) hits +system.iocache.demand_hits::total 0 # number of demand (read+write) hits system.iocache.demand_miss_latency 5748985804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_rate 1 # miss rate for demand accesses -system.iocache.demand_misses 41725 # number of demand (read+write) misses +system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses +system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses +system.iocache.demand_misses::0 0 # number of demand (read+write) misses +system.iocache.demand_misses::1 41725 # number of demand (read+write) misses +system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.iocache.demand_mshr_miss_latency 3579140924 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.overall_accesses 41725 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency 137782.763427 # average overall miss latency +system.iocache.occ_%::1 0.084587 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 1.353399 # Average occupied blocks per context +system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses +system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137782.763427 # average overall miss latency +system.iocache.overall_avg_miss_latency::total inf # average overall miss latency system.iocache.overall_avg_mshr_miss_latency 85779.291168 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.iocache.overall_hits 0 # number of overall hits +system.iocache.overall_hits::0 0 # number of overall hits +system.iocache.overall_hits::1 0 # number of overall hits +system.iocache.overall_hits::total 0 # number of overall hits system.iocache.overall_miss_latency 5748985804 # number of overall miss cycles -system.iocache.overall_miss_rate 1 # miss rate for overall accesses -system.iocache.overall_misses 41725 # number of overall misses +system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses +system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses +system.iocache.overall_misses::0 0 # number of overall misses +system.iocache.overall_misses::1 41725 # number of overall misses +system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits system.iocache.overall_mshr_miss_latency 3579140924 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -342,40 +467,61 @@ system.iocache.tagsinuse 1.353399 # Cy system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 1762299470000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses 304636 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 52003.289171 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 304636 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 304636 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 52003.289171 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_mshr_miss_latency 40003.289171 # average ReadExReq mshr miss latency system.l2c.ReadExReq_miss_latency 15842074000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 304636 # number of ReadExReq misses +system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 304636 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 304636 # number of ReadExReq misses system.l2c.ReadExReq_mshr_miss_latency 12186442000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_misses 304636 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 2018564 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 52016.377161 # average ReadReq miss latency +system.l2c.ReadReq_accesses::0 2018564 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2018564 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52016.377161 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.l2c.ReadReq_avg_mshr_miss_latency 40016.359280 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits 1710971 # number of ReadReq hits +system.l2c.ReadReq_hits::0 1710971 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1710971 # number of ReadReq hits system.l2c.ReadReq_miss_latency 15999873500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.152382 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 307593 # number of ReadReq misses +system.l2c.ReadReq_miss_rate::0 0.152382 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 307593 # number of ReadReq misses +system.l2c.ReadReq_misses::total 307593 # number of ReadReq misses system.l2c.ReadReq_mshr_miss_latency 12308752000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.152382 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::0 0.152382 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_misses 307593 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_uncacheable_latency 772673000 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses 126223 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 52001.810288 # average UpgradeReq miss latency +system.l2c.UpgradeReq_accesses::0 126223 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 126223 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 52001.810288 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency 40005.910175 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_miss_latency 6563824500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 126223 # number of UpgradeReq misses +system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 126223 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 126223 # number of UpgradeReq misses system.l2c.UpgradeReq_mshr_miss_latency 5049666000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_misses 126223 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_mshr_uncacheable_latency 1085299500 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses 430459 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 430459 # number of Writeback hits +system.l2c.Writeback_accesses::0 430459 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 430459 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 430459 # number of Writeback hits +system.l2c.Writeback_hits::total 430459 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.avg_refs 4.436562 # Average number of references to valid blocks. @@ -384,31 +530,59 @@ system.l2c.blocked::no_targets 0 # nu system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2323200 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 52009.864773 # average overall miss latency +system.l2c.demand_accesses::0 2323200 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2323200 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 52009.864773 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency +system.l2c.demand_avg_miss_latency::total inf # average overall miss latency system.l2c.demand_avg_mshr_miss_latency 40009.855789 # average overall mshr miss latency -system.l2c.demand_hits 1710971 # number of demand (read+write) hits +system.l2c.demand_hits::0 1710971 # number of demand (read+write) hits +system.l2c.demand_hits::1 0 # number of demand (read+write) hits +system.l2c.demand_hits::total 1710971 # number of demand (read+write) hits system.l2c.demand_miss_latency 31841947500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.263528 # miss rate for demand accesses -system.l2c.demand_misses 612229 # number of demand (read+write) misses +system.l2c.demand_miss_rate::0 0.263528 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses +system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses +system.l2c.demand_misses::0 612229 # number of demand (read+write) misses +system.l2c.demand_misses::1 0 # number of demand (read+write) misses +system.l2c.demand_misses::total 612229 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 24495194000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.263528 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 0.263528 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.l2c.demand_mshr_misses 612229 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 2323200 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 52009.864773 # average overall miss latency +system.l2c.occ_%::0 0.086363 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.380427 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 5659.865751 # Average occupied blocks per context +system.l2c.occ_blocks::1 24931.678191 # Average occupied blocks per context +system.l2c.overall_accesses::0 2323200 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2323200 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 52009.864773 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency +system.l2c.overall_avg_miss_latency::total inf # average overall miss latency system.l2c.overall_avg_mshr_miss_latency 40009.855789 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits 1710971 # number of overall hits +system.l2c.overall_hits::0 1710971 # number of overall hits +system.l2c.overall_hits::1 0 # number of overall hits +system.l2c.overall_hits::total 1710971 # number of overall hits system.l2c.overall_miss_latency 31841947500 # number of overall miss cycles -system.l2c.overall_miss_rate 0.263528 # miss rate for overall accesses -system.l2c.overall_misses 612229 # number of overall misses +system.l2c.overall_miss_rate::0 0.263528 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses +system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses +system.l2c.overall_misses::0 612229 # number of overall misses +system.l2c.overall_misses::1 0 # number of overall misses +system.l2c.overall_misses::total 612229 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 24495194000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.263528 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 0.263528 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.l2c.overall_mshr_misses 612229 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 1857972500 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini index d9595cbc3..ea5856bb6 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini @@ -53,7 +53,7 @@ type=ExeTracer type=EioProcess chkpt= errout=cerr -file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz input=None max_stack_size=67108864 output=cout diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout index 06ee016b8..c651bb2bf 100755 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 16:38:39 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 16:57:23 -M5 executing on zizzer +M5 compiled Feb 24 2010 23:12:40 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 03:02:04 +M5 executing on SC2B0619 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt index b870c6458..0e89d8fd8 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3016706 # Simulator instruction rate (inst/s) -host_mem_usage 191632 # Number of bytes of host memory used +host_inst_rate 3013906 # Simulator instruction rate (inst/s) +host_mem_usage 181592 # Number of bytes of host memory used host_seconds 0.17 # Real time elapsed on the host -host_tick_rate 1506280802 # Simulator tick rate (ticks/s) +host_tick_rate 1504585693 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500001 # Number of instructions simulated sim_seconds 0.000250 # Number of seconds simulated diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini index 5fbeffed0..f1b56a9bd 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini @@ -45,7 +45,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -80,7 +80,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -115,7 +115,7 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 @@ -153,7 +153,7 @@ type=ExeTracer type=EioProcess chkpt= errout=cerr -file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz input=None max_stack_size=67108864 output=cout diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout index b68290cbf..3a00a516f 100755 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2009 06:58:26 -M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff -M5 started Apr 22 2009 07:17:24 -M5 executing on maize +M5 compiled Feb 24 2010 23:12:40 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 02:33:34 +M5 executing on SC2B0619 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt index 2894da70d..fb5a17baa 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2302773 # Simulator instruction rate (inst/s) -host_mem_usage 201032 # Number of bytes of host memory used -host_seconds 0.22 # Real time elapsed on the host -host_tick_rate 3391978546 # Simulator tick rate (ticks/s) +host_inst_rate 1409192 # Simulator instruction rate (inst/s) +host_mem_usage 189184 # Number of bytes of host memory used +host_seconds 0.36 # Real time elapsed on the host +host_tick_rate 2076450214 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500001 # Number of instructions simulated sim_seconds 0.000737 # Number of seconds simulated @@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses 626 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.069937 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 286.463742 # Average occupied blocks per context system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -119,6 +121,8 @@ system.cpu.icache.demand_mshr_misses 403 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.129067 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 264.328816 # Average occupied blocks per context system.cpu.icache.overall_accesses 500020 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -206,6 +210,8 @@ system.cpu.l2cache.demand_mshr_misses 857 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.011298 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 370.220381 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 857 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini index b801b4825..a6af5d880 100644 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini @@ -48,7 +48,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -83,7 +83,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -115,7 +115,7 @@ type=ExeTracer type=EioProcess chkpt= errout=cerr -file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz input=None max_stack_size=67108864 output=cout @@ -160,7 +160,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -195,7 +195,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -227,7 +227,7 @@ type=ExeTracer type=EioProcess chkpt= errout=cerr -file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz input=None max_stack_size=67108864 output=cout @@ -272,7 +272,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -307,7 +307,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -339,7 +339,7 @@ type=ExeTracer type=EioProcess chkpt= errout=cerr -file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz input=None max_stack_size=67108864 output=cout @@ -384,7 +384,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -419,7 +419,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -451,7 +451,7 @@ type=ExeTracer type=EioProcess chkpt= errout=cerr -file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz input=None max_stack_size=67108864 output=cout @@ -467,7 +467,7 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=92 -prefetch_cache_check_push=true +num_cpus=4 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr index 75c83d350..1abe4a9de 100755 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr @@ -5,7 +5,3 @@ hack: be nice to actually delete the event here gzip: stdout: Broken pipe gzip: stdout: Broken pipe - -gzip: stdout: Broken pipe - -gzip: stdout: Broken pipe diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout index 6828937b6..6a26281d0 100755 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2009 06:58:26 -M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff -M5 started Apr 22 2009 07:17:24 -M5 executing on maize +M5 compiled Feb 24 2010 23:12:40 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 02:22:16 +M5 executing on SC2B0619 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt index 75b87a853..94c888d5d 100644 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 4530821 # Simulator instruction rate (inst/s) -host_mem_usage 1125932 # Number of bytes of host memory used -host_seconds 0.44 # Real time elapsed on the host -host_tick_rate 566039081 # Simulator tick rate (ticks/s) +host_inst_rate 1651065 # Simulator instruction rate (inst/s) +host_mem_usage 1114084 # Number of bytes of host memory used +host_seconds 1.21 # Real time elapsed on the host +host_tick_rate 206342663 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2000004 # Number of instructions simulated sim_seconds 0.000250 # Number of seconds simulated @@ -38,6 +38,8 @@ system.cpu0.dcache.demand_mshr_misses 0 # nu system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.occ_%::0 0.540766 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::0 276.872320 # Average occupied blocks per context system.cpu0.dcache.overall_accesses 180775 # number of overall (read+write) accesses system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency @@ -101,6 +103,8 @@ system.cpu0.icache.demand_mshr_misses 0 # nu system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.occ_%::0 0.425950 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::0 218.086151 # Average occupied blocks per context system.cpu0.icache.overall_accesses 500019 # number of overall (read+write) accesses system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency @@ -174,6 +178,8 @@ system.cpu1.dcache.demand_mshr_misses 0 # nu system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.occ_%::0 0.540766 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 276.872320 # Average occupied blocks per context system.cpu1.dcache.overall_accesses 180775 # number of overall (read+write) accesses system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency @@ -237,6 +243,8 @@ system.cpu1.icache.demand_mshr_misses 0 # nu system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.occ_%::0 0.425950 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 218.086151 # Average occupied blocks per context system.cpu1.icache.overall_accesses 500019 # number of overall (read+write) accesses system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency @@ -310,6 +318,8 @@ system.cpu2.dcache.demand_mshr_misses 0 # nu system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.dcache.occ_%::0 0.540766 # Average percentage of cache occupancy +system.cpu2.dcache.occ_blocks::0 276.872320 # Average occupied blocks per context system.cpu2.dcache.overall_accesses 180775 # number of overall (read+write) accesses system.cpu2.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency @@ -373,6 +383,8 @@ system.cpu2.icache.demand_mshr_misses 0 # nu system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.icache.occ_%::0 0.425950 # Average percentage of cache occupancy +system.cpu2.icache.occ_blocks::0 218.086151 # Average occupied blocks per context system.cpu2.icache.overall_accesses 500019 # number of overall (read+write) accesses system.cpu2.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu2.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency @@ -446,6 +458,8 @@ system.cpu3.dcache.demand_mshr_misses 0 # nu system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.dcache.occ_%::0 0.540766 # Average percentage of cache occupancy +system.cpu3.dcache.occ_blocks::0 276.872320 # Average occupied blocks per context system.cpu3.dcache.overall_accesses 180775 # number of overall (read+write) accesses system.cpu3.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency @@ -509,6 +523,8 @@ system.cpu3.icache.demand_mshr_misses 0 # nu system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.icache.occ_%::0 0.425950 # Average percentage of cache occupancy +system.cpu3.icache.occ_blocks::0 218.086151 # Average occupied blocks per context system.cpu3.icache.overall_accesses 500019 # number of overall (read+write) accesses system.cpu3.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu3.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency @@ -552,18 +568,60 @@ system.cpu3.numCycles 500032 # nu system.cpu3.num_insts 500001 # Number of instructions executed system.cpu3.num_refs 182222 # Number of memory references system.cpu3.workload.PROG:num_syscalls 18 # Number of system calls -system.l2c.ReadExReq_accesses 556 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 556 # number of ReadExReq misses -system.l2c.ReadReq_accesses 3148 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits 276 # number of ReadReq hits -system.l2c.ReadReq_miss_rate 0.912325 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 2872 # number of ReadReq misses -system.l2c.UpgradeReq_accesses 688 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 688 # number of UpgradeReq misses -system.l2c.Writeback_accesses 116 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 116 # number of Writeback hits +system.l2c.ReadExReq_accesses::0 139 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 139 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::2 139 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::3 139 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 139 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 139 # number of ReadExReq misses +system.l2c.ReadExReq_misses::2 139 # number of ReadExReq misses +system.l2c.ReadExReq_misses::3 139 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses +system.l2c.ReadReq_accesses::0 787 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 787 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::2 787 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::3 787 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 3148 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits::0 69 # number of ReadReq hits +system.l2c.ReadReq_hits::1 69 # number of ReadReq hits +system.l2c.ReadReq_hits::2 69 # number of ReadReq hits +system.l2c.ReadReq_hits::3 69 # number of ReadReq hits +system.l2c.ReadReq_hits::total 276 # number of ReadReq hits +system.l2c.ReadReq_miss_rate::0 0.912325 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.912325 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::2 0.912325 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::3 0.912325 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 3.649301 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 718 # number of ReadReq misses +system.l2c.ReadReq_misses::1 718 # number of ReadReq misses +system.l2c.ReadReq_misses::2 718 # number of ReadReq misses +system.l2c.ReadReq_misses::3 718 # number of ReadReq misses +system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses +system.l2c.UpgradeReq_accesses::0 172 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 172 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::2 172 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::3 172 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 688 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 4 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 172 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 172 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::2 172 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::3 172 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 688 # number of UpgradeReq misses +system.l2c.Writeback_accesses::0 116 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 116 # number of Writeback hits +system.l2c.Writeback_hits::total 116 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.avg_refs 0.120000 # Average number of references to valid blocks. @@ -572,31 +630,89 @@ system.l2c.blocked::no_targets 0 # nu system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 3704 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 0 # average overall miss latency +system.l2c.demand_accesses::0 926 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 926 # number of demand (read+write) accesses +system.l2c.demand_accesses::2 926 # number of demand (read+write) accesses +system.l2c.demand_accesses::3 926 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3704 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 0 # average overall miss latency +system.l2c.demand_avg_miss_latency::3 0 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.demand_hits 276 # number of demand (read+write) hits +system.l2c.demand_hits::0 69 # number of demand (read+write) hits +system.l2c.demand_hits::1 69 # number of demand (read+write) hits +system.l2c.demand_hits::2 69 # number of demand (read+write) hits +system.l2c.demand_hits::3 69 # number of demand (read+write) hits +system.l2c.demand_hits::total 276 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.925486 # miss rate for demand accesses -system.l2c.demand_misses 3428 # number of demand (read+write) misses +system.l2c.demand_miss_rate::0 0.925486 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.925486 # miss rate for demand accesses +system.l2c.demand_miss_rate::2 0.925486 # miss rate for demand accesses +system.l2c.demand_miss_rate::3 0.925486 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 3.701944 # miss rate for demand accesses +system.l2c.demand_misses::0 857 # number of demand (read+write) misses +system.l2c.demand_misses::1 857 # number of demand (read+write) misses +system.l2c.demand_misses::2 857 # number of demand (read+write) misses +system.l2c.demand_misses::3 857 # number of demand (read+write) misses +system.l2c.demand_misses::total 3428 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::2 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::3 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 3704 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 0 # average overall miss latency +system.l2c.occ_%::0 0.005715 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.005715 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.005715 # Average percentage of cache occupancy +system.l2c.occ_%::3 0.005715 # Average percentage of cache occupancy +system.l2c.occ_%::4 0.000475 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 374.558766 # Average occupied blocks per context +system.l2c.occ_blocks::1 374.558766 # Average occupied blocks per context +system.l2c.occ_blocks::2 374.558766 # Average occupied blocks per context +system.l2c.occ_blocks::3 374.558766 # Average occupied blocks per context +system.l2c.occ_blocks::4 31.139534 # Average occupied blocks per context +system.l2c.overall_accesses::0 926 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 926 # number of overall (read+write) accesses +system.l2c.overall_accesses::2 926 # number of overall (read+write) accesses +system.l2c.overall_accesses::3 926 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::3 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.overall_hits 276 # number of overall hits +system.l2c.overall_hits::0 69 # number of overall hits +system.l2c.overall_hits::1 69 # number of overall hits +system.l2c.overall_hits::2 69 # number of overall hits +system.l2c.overall_hits::3 69 # number of overall hits +system.l2c.overall_hits::total 276 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate 0.925486 # miss rate for overall accesses -system.l2c.overall_misses 3428 # number of overall misses +system.l2c.overall_miss_rate::0 0.925486 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.925486 # miss rate for overall accesses +system.l2c.overall_miss_rate::2 0.925486 # miss rate for overall accesses +system.l2c.overall_miss_rate::3 0.925486 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 3.701944 # miss rate for overall accesses +system.l2c.overall_misses::0 857 # number of overall misses +system.l2c.overall_misses::1 857 # number of overall misses +system.l2c.overall_misses::2 857 # number of overall misses +system.l2c.overall_misses::3 857 # number of overall misses +system.l2c.overall_misses::total 3428 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::2 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::3 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses system.l2c.overall_mshr_misses 0 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini index 02b245760..29d69ea29 100644 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini @@ -45,7 +45,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -80,7 +80,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -112,7 +112,7 @@ type=ExeTracer type=EioProcess chkpt= errout=cerr -file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz input=None max_stack_size=67108864 output=cout @@ -154,7 +154,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -189,7 +189,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -221,7 +221,7 @@ type=ExeTracer type=EioProcess chkpt= errout=cerr -file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz input=None max_stack_size=67108864 output=cout @@ -263,7 +263,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -298,7 +298,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -330,7 +330,7 @@ type=ExeTracer type=EioProcess chkpt= errout=cerr -file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz input=None max_stack_size=67108864 output=cout @@ -372,7 +372,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -407,7 +407,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -439,7 +439,7 @@ type=ExeTracer type=EioProcess chkpt= errout=cerr -file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz input=None max_stack_size=67108864 output=cout @@ -455,7 +455,7 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=92 -prefetch_cache_check_push=true +num_cpus=4 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr index 75c83d350..1abe4a9de 100755 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr @@ -5,7 +5,3 @@ hack: be nice to actually delete the event here gzip: stdout: Broken pipe gzip: stdout: Broken pipe - -gzip: stdout: Broken pipe - -gzip: stdout: Broken pipe diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout index 8902435b9..3215ccd26 100755 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2009 06:58:26 -M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff -M5 started Apr 22 2009 07:17:25 -M5 executing on maize +M5 compiled Feb 24 2010 23:12:40 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 02:28:17 +M5 executing on SC2B0619 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt index 2214f40ec..17c7f3b49 100644 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2185563 # Simulator instruction rate (inst/s) -host_mem_usage 208428 # Number of bytes of host memory used -host_seconds 0.92 # Real time elapsed on the host -host_tick_rate 806662952 # Simulator tick rate (ticks/s) +host_inst_rate 1192031 # Simulator instruction rate (inst/s) +host_mem_usage 196580 # Number of bytes of host memory used +host_seconds 1.68 # Real time elapsed on the host +host_tick_rate 440023932 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1999941 # Number of instructions simulated sim_seconds 0.000738 # Number of seconds simulated @@ -50,6 +50,8 @@ system.cpu0.dcache.demand_mshr_misses 635 # nu system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.occ_%::0 0.533035 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::0 272.914158 # Average occupied blocks per context system.cpu0.dcache.overall_accesses 180771 # number of overall (read+write) accesses system.cpu0.dcache.overall_avg_miss_latency 55480.314961 # average overall miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency 52480.314961 # average overall mshr miss latency @@ -119,6 +121,8 @@ system.cpu0.icache.demand_mshr_misses 463 # nu system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.occ_%::0 0.421784 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::0 215.953225 # Average occupied blocks per context system.cpu0.icache.overall_accesses 500000 # number of overall (read+write) accesses system.cpu0.icache.overall_avg_miss_latency 50723.542117 # average overall miss latency system.cpu0.icache.overall_avg_mshr_miss_latency 47723.542117 # average overall mshr miss latency @@ -204,6 +208,8 @@ system.cpu1.dcache.demand_mshr_misses 635 # nu system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.occ_%::0 0.533029 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 272.910830 # Average occupied blocks per context system.cpu1.dcache.overall_accesses 180768 # number of overall (read+write) accesses system.cpu1.dcache.overall_avg_miss_latency 55464.566929 # average overall miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency 52464.566929 # average overall mshr miss latency @@ -273,6 +279,8 @@ system.cpu1.icache.demand_mshr_misses 463 # nu system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.occ_%::0 0.421779 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 215.951034 # Average occupied blocks per context system.cpu1.icache.overall_accesses 499994 # number of overall (read+write) accesses system.cpu1.icache.overall_avg_miss_latency 50764.578834 # average overall miss latency system.cpu1.icache.overall_avg_mshr_miss_latency 47764.578834 # average overall mshr miss latency @@ -358,6 +366,8 @@ system.cpu2.dcache.demand_mshr_misses 635 # nu system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.dcache.occ_%::0 0.533049 # Average percentage of cache occupancy +system.cpu2.dcache.occ_blocks::0 272.921161 # Average occupied blocks per context system.cpu2.dcache.overall_accesses 180775 # number of overall (read+write) accesses system.cpu2.dcache.overall_avg_miss_latency 55451.968504 # average overall miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency 52451.968504 # average overall mshr miss latency @@ -427,6 +437,8 @@ system.cpu2.icache.demand_mshr_misses 463 # nu system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.icache.occ_%::0 0.421796 # Average percentage of cache occupancy +system.cpu2.icache.occ_blocks::0 215.959580 # Average occupied blocks per context system.cpu2.icache.overall_accesses 500020 # number of overall (read+write) accesses system.cpu2.icache.overall_avg_miss_latency 50710.583153 # average overall miss latency system.cpu2.icache.overall_avg_mshr_miss_latency 47710.583153 # average overall mshr miss latency @@ -512,6 +524,8 @@ system.cpu3.dcache.demand_mshr_misses 635 # nu system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.dcache.occ_%::0 0.533040 # Average percentage of cache occupancy +system.cpu3.dcache.occ_blocks::0 272.916356 # Average occupied blocks per context system.cpu3.dcache.overall_accesses 180772 # number of overall (read+write) accesses system.cpu3.dcache.overall_avg_miss_latency 55478.740157 # average overall miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency 52478.740157 # average overall mshr miss latency @@ -581,6 +595,8 @@ system.cpu3.icache.demand_mshr_misses 463 # nu system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.icache.occ_%::0 0.421787 # Average percentage of cache occupancy +system.cpu3.icache.occ_blocks::0 215.955045 # Average occupied blocks per context system.cpu3.icache.overall_accesses 500003 # number of overall (read+write) accesses system.cpu3.icache.overall_avg_miss_latency 50717.062635 # average overall miss latency system.cpu3.icache.overall_avg_mshr_miss_latency 47717.062635 # average overall mshr miss latency @@ -624,36 +640,102 @@ system.cpu3.numCycles 1476774 # nu system.cpu3.num_insts 499984 # Number of instructions executed system.cpu3.num_refs 182219 # Number of memory references system.cpu3.workload.PROG:num_syscalls 18 # Number of system calls -system.l2c.ReadExReq_accesses 556 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 52008.992806 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 139 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 139 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::2 139 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::3 139 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 208035.971223 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 208035.971223 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::2 208035.971223 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::3 208035.971223 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 832143.884892 # average ReadExReq miss latency system.l2c.ReadExReq_avg_mshr_miss_latency 40008.992806 # average ReadExReq mshr miss latency system.l2c.ReadExReq_miss_latency 28917000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 556 # number of ReadExReq misses +system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 139 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 139 # number of ReadExReq misses +system.l2c.ReadExReq_misses::2 139 # number of ReadExReq misses +system.l2c.ReadExReq_misses::3 139 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses system.l2c.ReadExReq_mshr_miss_latency 22245000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 4 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 4 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::2 4 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::3 4 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 16 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_misses 556 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 3148 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 52008.008357 # average ReadReq miss latency +system.l2c.ReadReq_accesses::0 787 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 787 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::2 787 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::3 787 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 3148 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 208032.033426 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 208032.033426 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::2 208032.033426 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::3 208032.033426 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 832128.133705 # average ReadReq miss latency system.l2c.ReadReq_avg_mshr_miss_latency 40008.008357 # average ReadReq mshr miss latency -system.l2c.ReadReq_hits 276 # number of ReadReq hits +system.l2c.ReadReq_hits::0 69 # number of ReadReq hits +system.l2c.ReadReq_hits::1 69 # number of ReadReq hits +system.l2c.ReadReq_hits::2 69 # number of ReadReq hits +system.l2c.ReadReq_hits::3 69 # number of ReadReq hits +system.l2c.ReadReq_hits::total 276 # number of ReadReq hits system.l2c.ReadReq_miss_latency 149367000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.912325 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 2872 # number of ReadReq misses +system.l2c.ReadReq_miss_rate::0 0.912325 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.912325 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::2 0.912325 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::3 0.912325 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 3.649301 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 718 # number of ReadReq misses +system.l2c.ReadReq_misses::1 718 # number of ReadReq misses +system.l2c.ReadReq_misses::2 718 # number of ReadReq misses +system.l2c.ReadReq_misses::3 718 # number of ReadReq misses +system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses system.l2c.ReadReq_mshr_miss_latency 114903000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.912325 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::0 3.649301 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 3.649301 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::2 3.649301 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::3 3.649301 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 14.597205 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_misses 2872 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_accesses 688 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 52001.453488 # average UpgradeReq miss latency +system.l2c.UpgradeReq_accesses::0 172 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 172 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::2 172 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::3 172 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 688 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 208005.813953 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 208005.813953 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::2 208005.813953 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::3 208005.813953 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 832023.255814 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency 40001.453488 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_miss_latency 35777000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 688 # number of UpgradeReq misses +system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 4 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 172 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 172 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::2 172 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::3 172 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 688 # number of UpgradeReq misses system.l2c.UpgradeReq_mshr_miss_latency 27521000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 4 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 4 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::2 4 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::3 4 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 16 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_misses 688 # number of UpgradeReq MSHR misses -system.l2c.Writeback_accesses 116 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 116 # number of Writeback hits +system.l2c.Writeback_accesses::0 116 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 116 # number of Writeback hits +system.l2c.Writeback_hits::total 116 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.avg_refs 0.120000 # Average number of references to valid blocks. @@ -662,31 +744,89 @@ system.l2c.blocked::no_targets 0 # nu system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 3704 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 52008.168028 # average overall miss latency +system.l2c.demand_accesses::0 926 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 926 # number of demand (read+write) accesses +system.l2c.demand_accesses::2 926 # number of demand (read+write) accesses +system.l2c.demand_accesses::3 926 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3704 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 208032.672112 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 208032.672112 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 208032.672112 # average overall miss latency +system.l2c.demand_avg_miss_latency::3 208032.672112 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 832130.688448 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency 40008.168028 # average overall mshr miss latency -system.l2c.demand_hits 276 # number of demand (read+write) hits +system.l2c.demand_hits::0 69 # number of demand (read+write) hits +system.l2c.demand_hits::1 69 # number of demand (read+write) hits +system.l2c.demand_hits::2 69 # number of demand (read+write) hits +system.l2c.demand_hits::3 69 # number of demand (read+write) hits +system.l2c.demand_hits::total 276 # number of demand (read+write) hits system.l2c.demand_miss_latency 178284000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.925486 # miss rate for demand accesses -system.l2c.demand_misses 3428 # number of demand (read+write) misses +system.l2c.demand_miss_rate::0 0.925486 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.925486 # miss rate for demand accesses +system.l2c.demand_miss_rate::2 0.925486 # miss rate for demand accesses +system.l2c.demand_miss_rate::3 0.925486 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 3.701944 # miss rate for demand accesses +system.l2c.demand_misses::0 857 # number of demand (read+write) misses +system.l2c.demand_misses::1 857 # number of demand (read+write) misses +system.l2c.demand_misses::2 857 # number of demand (read+write) misses +system.l2c.demand_misses::3 857 # number of demand (read+write) misses +system.l2c.demand_misses::total 3428 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 137148000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.925486 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 3.701944 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 3.701944 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::2 3.701944 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::3 3.701944 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 14.807775 # mshr miss rate for demand accesses system.l2c.demand_mshr_misses 3428 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 3704 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 52008.168028 # average overall miss latency +system.l2c.occ_%::0 0.005650 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.005650 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.005650 # Average percentage of cache occupancy +system.l2c.occ_%::3 0.005650 # Average percentage of cache occupancy +system.l2c.occ_%::4 0.000464 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 370.294638 # Average occupied blocks per context +system.l2c.occ_blocks::1 370.290796 # Average occupied blocks per context +system.l2c.occ_blocks::2 370.305065 # Average occupied blocks per context +system.l2c.occ_blocks::3 370.297695 # Average occupied blocks per context +system.l2c.occ_blocks::4 30.383926 # Average occupied blocks per context +system.l2c.overall_accesses::0 926 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 926 # number of overall (read+write) accesses +system.l2c.overall_accesses::2 926 # number of overall (read+write) accesses +system.l2c.overall_accesses::3 926 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 208032.672112 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 208032.672112 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 208032.672112 # average overall miss latency +system.l2c.overall_avg_miss_latency::3 208032.672112 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 832130.688448 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency 40008.168028 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.overall_hits 276 # number of overall hits +system.l2c.overall_hits::0 69 # number of overall hits +system.l2c.overall_hits::1 69 # number of overall hits +system.l2c.overall_hits::2 69 # number of overall hits +system.l2c.overall_hits::3 69 # number of overall hits +system.l2c.overall_hits::total 276 # number of overall hits system.l2c.overall_miss_latency 178284000 # number of overall miss cycles -system.l2c.overall_miss_rate 0.925486 # miss rate for overall accesses -system.l2c.overall_misses 3428 # number of overall misses +system.l2c.overall_miss_rate::0 0.925486 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.925486 # miss rate for overall accesses +system.l2c.overall_miss_rate::2 0.925486 # miss rate for overall accesses +system.l2c.overall_miss_rate::3 0.925486 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 3.701944 # miss rate for overall accesses +system.l2c.overall_misses::0 857 # number of overall misses +system.l2c.overall_misses::1 857 # number of overall misses +system.l2c.overall_misses::2 857 # number of overall misses +system.l2c.overall_misses::3 857 # number of overall misses +system.l2c.overall_misses::total 3428 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 137148000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.925486 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 3.701944 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 3.701944 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::2 3.701944 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::3 3.701944 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 14.807775 # mshr miss rate for overall accesses system.l2c.overall_mshr_misses 3428 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini index 28f0771b6..2fffc58e2 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini @@ -109,7 +109,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -281,7 +281,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -317,7 +317,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 @@ -428,7 +428,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -600,7 +600,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -728,7 +728,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -900,7 +900,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -1028,7 +1028,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -1200,7 +1200,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -1238,7 +1238,7 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=92 -prefetch_cache_check_push=true +num_cpus=4 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index b796fed55..1d66e4129 100755 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 6 2009 11:07:18 -M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip -M5 started Jul 6 2009 11:11:25 -M5 executing on maize +M5 compiled Feb 25 2010 03:11:27 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 03:38:02 +M5 executing on SC2B0619 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 97835b389..75d6c02bb 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 21799 # Simulator instruction rate (inst/s) -host_mem_usage 200132 # Number of bytes of host memory used -host_seconds 20.14 # Real time elapsed on the host -host_tick_rate 10950015 # Simulator tick rate (ticks/s) +host_inst_rate 38759 # Simulator instruction rate (inst/s) +host_mem_usage 200852 # Number of bytes of host memory used +host_seconds 11.32 # Real time elapsed on the host +host_tick_rate 19469095 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 438923 # Number of instructions simulated sim_seconds 0.000220 # Number of seconds simulated @@ -104,6 +104,8 @@ system.cpu0.dcache.demand_mshr_misses 282 # nu system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.occ_%::0 0.055235 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::0 28.280349 # Average occupied blocks per context system.cpu0.dcache.overall_accesses 40537 # number of overall (read+write) accesses system.cpu0.dcache.overall_avg_miss_latency 20113.149847 # average overall miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency 15416.666667 # average overall mshr miss latency @@ -191,6 +193,8 @@ system.cpu0.icache.demand_mshr_misses 635 # nu system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.occ_%::0 0.187347 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::0 95.921890 # Average occupied blocks per context system.cpu0.icache.overall_accesses 83600 # number of overall (read+write) accesses system.cpu0.icache.overall_avg_miss_latency 14035.763411 # average overall miss latency system.cpu0.icache.overall_avg_mshr_miss_latency 11552.755906 # average overall mshr miss latency @@ -430,6 +434,8 @@ system.cpu1.dcache.demand_mshr_misses 275 # nu system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.occ_%::0 0.053563 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 27.424102 # Average occupied blocks per context system.cpu1.dcache.overall_accesses 40428 # number of overall (read+write) accesses system.cpu1.dcache.overall_avg_miss_latency 20280.063291 # average overall miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency 15870.909091 # average overall mshr miss latency @@ -517,6 +523,8 @@ system.cpu1.icache.demand_mshr_misses 637 # nu system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.occ_%::0 0.183643 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 94.025224 # Average occupied blocks per context system.cpu1.icache.overall_accesses 83559 # number of overall (read+write) accesses system.cpu1.icache.overall_avg_miss_latency 13800.273598 # average overall miss latency system.cpu1.icache.overall_avg_mshr_miss_latency 11301.412873 # average overall mshr miss latency @@ -754,6 +762,10 @@ system.cpu2.dcache.demand_mshr_misses 421 # nu system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.dcache.occ_%::0 0.285109 # Average percentage of cache occupancy +system.cpu2.dcache.occ_%::1 -0.006965 # Average percentage of cache occupancy +system.cpu2.dcache.occ_blocks::0 145.975885 # Average occupied blocks per context +system.cpu2.dcache.occ_blocks::1 -3.566137 # Average occupied blocks per context system.cpu2.dcache.overall_accesses 46708 # number of overall (read+write) accesses system.cpu2.dcache.overall_avg_miss_latency 40467.796610 # average overall miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency 31115.201900 # average overall mshr miss latency @@ -841,6 +853,8 @@ system.cpu2.icache.demand_mshr_misses 670 # nu system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.icache.occ_%::0 0.526897 # Average percentage of cache occupancy +system.cpu2.icache.occ_blocks::0 269.771036 # Average occupied blocks per context system.cpu2.icache.overall_accesses 88443 # number of overall (read+write) accesses system.cpu2.icache.overall_avg_miss_latency 37054.535017 # average overall miss latency system.cpu2.icache.overall_avg_mshr_miss_latency 35099.253731 # average overall mshr miss latency @@ -1080,6 +1094,8 @@ system.cpu3.dcache.demand_mshr_misses 276 # nu system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.dcache.occ_%::0 0.056978 # Average percentage of cache occupancy +system.cpu3.dcache.occ_blocks::0 29.172631 # Average occupied blocks per context system.cpu3.dcache.overall_accesses 42192 # number of overall (read+write) accesses system.cpu3.dcache.overall_avg_miss_latency 21102.848101 # average overall miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency 15920.289855 # average overall mshr miss latency @@ -1167,6 +1183,8 @@ system.cpu3.icache.demand_mshr_misses 633 # nu system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.icache.occ_%::0 0.192956 # Average percentage of cache occupancy +system.cpu3.icache.occ_blocks::0 98.793514 # Average occupied blocks per context system.cpu3.icache.overall_accesses 81998 # number of overall (read+write) accesses system.cpu3.icache.overall_avg_miss_latency 19529.880478 # average overall miss latency system.cpu3.icache.overall_avg_mshr_miss_latency 16592.417062 # average overall mshr miss latency @@ -1308,37 +1326,103 @@ system.cpu3.rename.RENAME:serializingInsts 11653 # system.cpu3.rename.RENAME:skidInsts 44534 # count of insts added to the skid buffer system.cpu3.rename.RENAME:tempSerializingInsts 11782 # count of temporary serializing insts renamed system.cpu3.timesIdled 293 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.l2c.ReadExReq_accesses 131 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 52477.099237 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::2 94 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::3 13 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 572875 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 572875 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::2 73132.978723 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::3 528807.692308 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 1747690.671031 # average ReadExReq miss latency system.l2c.ReadExReq_avg_mshr_miss_latency 40316.793893 # average ReadExReq mshr miss latency system.l2c.ReadExReq_miss_latency 6874500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 131 # number of ReadExReq misses +system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::2 94 # number of ReadExReq misses +system.l2c.ReadExReq_misses::3 13 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses system.l2c.ReadExReq_mshr_miss_latency 5281500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 10.916667 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 10.916667 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::2 1.393617 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::3 10.076923 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 33.303873 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_misses 131 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 2699 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 52060.143627 # average ReadReq miss latency +system.l2c.ReadReq_accesses::0 649 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 651 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::2 752 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::3 647 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2699 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 4142500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 7249375 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::2 63451.859956 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::3 325814.606742 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 11781141.466698 # average ReadReq miss latency system.l2c.ReadReq_avg_mshr_miss_latency 39997.282609 # average ReadReq mshr miss latency -system.l2c.ReadReq_hits 2142 # number of ReadReq hits +system.l2c.ReadReq_hits::0 642 # number of ReadReq hits +system.l2c.ReadReq_hits::1 647 # number of ReadReq hits +system.l2c.ReadReq_hits::2 295 # number of ReadReq hits +system.l2c.ReadReq_hits::3 558 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2142 # number of ReadReq hits system.l2c.ReadReq_miss_latency 28997500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.206373 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 557 # number of ReadReq misses +system.l2c.ReadReq_miss_rate::0 0.010786 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.006144 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::2 0.607713 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::3 0.137558 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.762201 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 7 # number of ReadReq misses +system.l2c.ReadReq_misses::1 4 # number of ReadReq misses +system.l2c.ReadReq_misses::2 457 # number of ReadReq misses +system.l2c.ReadReq_misses::3 89 # number of ReadReq misses +system.l2c.ReadReq_misses::total 557 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 5 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_miss_latency 22078500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.204520 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::0 0.850539 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.847926 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::2 0.734043 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::3 0.853168 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 3.285677 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_misses 552 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_accesses 114 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 11482.456140 # average UpgradeReq miss latency +system.l2c.UpgradeReq_accesses::0 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 22 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::2 52 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::3 21 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 114 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 68894.736842 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 59500 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::2 25173.076923 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::3 62333.333333 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 215901.147099 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency 40039.473684 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_miss_latency 1309000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 114 # number of UpgradeReq misses +system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 4 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 22 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::2 52 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::3 21 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 114 # number of UpgradeReq misses system.l2c.UpgradeReq_mshr_miss_latency 4564500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 6 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 5.181818 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::2 2.192308 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::3 5.428571 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 18.802697 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_misses 114 # number of UpgradeReq MSHR misses -system.l2c.Writeback_accesses 9 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 9 # number of Writeback hits +system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 9 # number of Writeback hits +system.l2c.Writeback_hits::total 9 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.avg_refs 3.998131 # Average number of references to valid blocks. @@ -1347,31 +1431,89 @@ system.l2c.blocked::no_targets 0 # nu system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2830 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 52139.534884 # average overall miss latency +system.l2c.demand_accesses::0 661 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 663 # number of demand (read+write) accesses +system.l2c.demand_accesses::2 846 # number of demand (read+write) accesses +system.l2c.demand_accesses::3 660 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2830 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 1888000 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 2242000 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 65103.448276 # average overall miss latency +system.l2c.demand_avg_miss_latency::3 351686.274510 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 4546789.722786 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency 40058.565154 # average overall mshr miss latency -system.l2c.demand_hits 2142 # number of demand (read+write) hits +system.l2c.demand_hits::0 642 # number of demand (read+write) hits +system.l2c.demand_hits::1 647 # number of demand (read+write) hits +system.l2c.demand_hits::2 295 # number of demand (read+write) hits +system.l2c.demand_hits::3 558 # number of demand (read+write) hits +system.l2c.demand_hits::total 2142 # number of demand (read+write) hits system.l2c.demand_miss_latency 35872000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.243110 # miss rate for demand accesses -system.l2c.demand_misses 688 # number of demand (read+write) misses +system.l2c.demand_miss_rate::0 0.028744 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.024133 # miss rate for demand accesses +system.l2c.demand_miss_rate::2 0.651300 # miss rate for demand accesses +system.l2c.demand_miss_rate::3 0.154545 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.858723 # miss rate for demand accesses +system.l2c.demand_misses::0 19 # number of demand (read+write) misses +system.l2c.demand_misses::1 16 # number of demand (read+write) misses +system.l2c.demand_misses::2 551 # number of demand (read+write) misses +system.l2c.demand_misses::3 102 # number of demand (read+write) misses +system.l2c.demand_misses::total 688 # number of demand (read+write) misses system.l2c.demand_mshr_hits 5 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 27360000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.241343 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 1.033283 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.030166 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::2 0.807329 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::3 1.034848 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 3.905626 # mshr miss rate for demand accesses system.l2c.demand_mshr_misses 683 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 2830 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 52139.534884 # average overall miss latency +system.l2c.occ_%::0 0.000042 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.000041 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.005574 # Average percentage of cache occupancy +system.l2c.occ_%::3 0.001194 # Average percentage of cache occupancy +system.l2c.occ_%::4 0.000088 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 2.720574 # Average occupied blocks per context +system.l2c.occ_blocks::1 2.658049 # Average occupied blocks per context +system.l2c.occ_blocks::2 365.307630 # Average occupied blocks per context +system.l2c.occ_blocks::3 78.263554 # Average occupied blocks per context +system.l2c.occ_blocks::4 5.734616 # Average occupied blocks per context +system.l2c.overall_accesses::0 661 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 663 # number of overall (read+write) accesses +system.l2c.overall_accesses::2 846 # number of overall (read+write) accesses +system.l2c.overall_accesses::3 660 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2830 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 1888000 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 2242000 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 65103.448276 # average overall miss latency +system.l2c.overall_avg_miss_latency::3 351686.274510 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 4546789.722786 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency 40058.565154 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.overall_hits 2142 # number of overall hits +system.l2c.overall_hits::0 642 # number of overall hits +system.l2c.overall_hits::1 647 # number of overall hits +system.l2c.overall_hits::2 295 # number of overall hits +system.l2c.overall_hits::3 558 # number of overall hits +system.l2c.overall_hits::total 2142 # number of overall hits system.l2c.overall_miss_latency 35872000 # number of overall miss cycles -system.l2c.overall_miss_rate 0.243110 # miss rate for overall accesses -system.l2c.overall_misses 688 # number of overall misses +system.l2c.overall_miss_rate::0 0.028744 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.024133 # miss rate for overall accesses +system.l2c.overall_miss_rate::2 0.651300 # miss rate for overall accesses +system.l2c.overall_miss_rate::3 0.154545 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.858723 # miss rate for overall accesses +system.l2c.overall_misses::0 19 # number of overall misses +system.l2c.overall_misses::1 16 # number of overall misses +system.l2c.overall_misses::2 551 # number of overall misses +system.l2c.overall_misses::3 102 # number of overall misses +system.l2c.overall_misses::total 688 # number of overall misses system.l2c.overall_mshr_hits 5 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 27360000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.241343 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 1.033283 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.030166 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::2 0.807329 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::3 1.034848 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 3.905626 # mshr miss rate for overall accesses system.l2c.overall_mshr_misses 683 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini index 1a2a2ab9f..fb5bbcb94 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini @@ -48,7 +48,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -83,7 +83,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -119,7 +119,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 @@ -169,7 +169,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -204,7 +204,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -271,7 +271,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -306,7 +306,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -373,7 +373,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -408,7 +408,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -446,7 +446,7 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=92 -prefetch_cache_check_push=true +num_cpus=4 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr index eabe42249..eabe42249 100644..100755 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout index 077b03b98..43b76147e 100644..100755 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2009 06:58:47 -M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff -M5 started Apr 22 2009 07:32:58 -M5 executing on maize +M5 compiled Feb 25 2010 03:11:27 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 03:38:16 +M5 executing on SC2B0619 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 9d16d1421..61e7810b9 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1712699 # Simulator instruction rate (inst/s) -host_mem_usage 1128716 # Number of bytes of host memory used -host_seconds 0.40 # Real time elapsed on the host -host_tick_rate 221634180 # Simulator tick rate (ticks/s) +host_inst_rate 1722968 # Simulator instruction rate (inst/s) +host_mem_usage 1115976 # Number of bytes of host memory used +host_seconds 0.39 # Real time elapsed on the host +host_tick_rate 222951866 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 677340 # Number of instructions simulated sim_seconds 0.000088 # Number of seconds simulated @@ -42,6 +42,8 @@ system.cpu0.dcache.demand_mshr_misses 0 # nu system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.occ_%::0 0.055509 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::0 28.420699 # Average occupied blocks per context system.cpu0.dcache.overall_accesses 58461 # number of overall (read+write) accesses system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency @@ -89,6 +91,8 @@ system.cpu0.icache.demand_mshr_misses 0 # nu system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.occ_%::0 0.146046 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::0 74.775474 # Average occupied blocks per context system.cpu0.icache.overall_accesses 167366 # number of overall (read+write) accesses system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency @@ -150,6 +154,8 @@ system.cpu1.dcache.demand_mshr_misses 0 # nu system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.occ_%::0 0.053884 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 27.588376 # Average occupied blocks per context system.cpu1.dcache.overall_accesses 55820 # number of overall (read+write) accesses system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency @@ -197,6 +203,8 @@ system.cpu1.icache.demand_mshr_misses 0 # nu system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.occ_%::0 0.142322 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 72.869097 # Average occupied blocks per context system.cpu1.icache.overall_accesses 167301 # number of overall (read+write) accesses system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency @@ -257,6 +265,8 @@ system.cpu2.dcache.demand_mshr_misses 0 # nu system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.dcache.occ_%::0 0.284595 # Average percentage of cache occupancy +system.cpu2.dcache.occ_blocks::0 145.712770 # Average occupied blocks per context system.cpu2.dcache.overall_accesses 82337 # number of overall (read+write) accesses system.cpu2.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency @@ -304,6 +314,8 @@ system.cpu2.icache.demand_mshr_misses 0 # nu system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.icache.occ_%::0 0.435073 # Average percentage of cache occupancy +system.cpu2.icache.occ_blocks::0 222.757301 # Average occupied blocks per context system.cpu2.icache.overall_accesses 175401 # number of overall (read+write) accesses system.cpu2.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu2.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency @@ -364,6 +376,8 @@ system.cpu3.dcache.demand_mshr_misses 0 # nu system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.dcache.occ_%::0 0.056783 # Average percentage of cache occupancy +system.cpu3.dcache.occ_blocks::0 29.073016 # Average occupied blocks per context system.cpu3.dcache.overall_accesses 53313 # number of overall (read+write) accesses system.cpu3.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency @@ -411,6 +425,8 @@ system.cpu3.icache.demand_mshr_misses 0 # nu system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.icache.occ_%::0 0.149895 # Average percentage of cache occupancy +system.cpu3.icache.occ_blocks::0 76.746014 # Average occupied blocks per context system.cpu3.icache.overall_accesses 167430 # number of overall (read+write) accesses system.cpu3.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu3.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency @@ -437,18 +453,60 @@ system.cpu3.not_idle_fraction 0.954494 # Pe system.cpu3.numCycles 173308 # number of cpu cycles simulated system.cpu3.num_insts 167398 # Number of instructions executed system.cpu3.num_refs 53394 # Number of memory references -system.l2c.ReadExReq_accesses 136 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 136 # number of ReadExReq misses -system.l2c.ReadReq_accesses 1649 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits 1226 # number of ReadReq hits -system.l2c.ReadReq_miss_rate 0.256519 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 423 # number of ReadReq misses -system.l2c.UpgradeReq_accesses 106 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 106 # number of UpgradeReq misses -system.l2c.Writeback_accesses 9 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 9 # number of Writeback hits +system.l2c.ReadExReq_accesses::0 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::2 99 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::3 13 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::2 99 # number of ReadExReq misses +system.l2c.ReadExReq_misses::3 13 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses +system.l2c.ReadReq_accesses::0 370 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 371 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::2 538 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::3 370 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1649 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits::0 367 # number of ReadReq hits +system.l2c.ReadReq_hits::1 368 # number of ReadReq hits +system.l2c.ReadReq_hits::2 190 # number of ReadReq hits +system.l2c.ReadReq_hits::3 301 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1226 # number of ReadReq hits +system.l2c.ReadReq_miss_rate::0 0.008108 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.008086 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::2 0.646840 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::3 0.186486 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.849521 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 3 # number of ReadReq misses +system.l2c.ReadReq_misses::1 3 # number of ReadReq misses +system.l2c.ReadReq_misses::2 348 # number of ReadReq misses +system.l2c.ReadReq_misses::3 69 # number of ReadReq misses +system.l2c.ReadReq_misses::total 423 # number of ReadReq misses +system.l2c.UpgradeReq_accesses::0 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::2 48 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::3 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 106 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 4 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 20 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::2 48 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::3 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 106 # number of UpgradeReq misses +system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 9 # number of Writeback hits +system.l2c.Writeback_hits::total 9 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.avg_refs 2.968447 # Average number of references to valid blocks. @@ -457,31 +515,89 @@ system.l2c.blocked::no_targets 0 # nu system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 1785 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 0 # average overall miss latency +system.l2c.demand_accesses::0 382 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 383 # number of demand (read+write) accesses +system.l2c.demand_accesses::2 637 # number of demand (read+write) accesses +system.l2c.demand_accesses::3 383 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1785 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 0 # average overall miss latency +system.l2c.demand_avg_miss_latency::3 0 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.demand_hits 1226 # number of demand (read+write) hits +system.l2c.demand_hits::0 367 # number of demand (read+write) hits +system.l2c.demand_hits::1 368 # number of demand (read+write) hits +system.l2c.demand_hits::2 190 # number of demand (read+write) hits +system.l2c.demand_hits::3 301 # number of demand (read+write) hits +system.l2c.demand_hits::total 1226 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.313165 # miss rate for demand accesses -system.l2c.demand_misses 559 # number of demand (read+write) misses +system.l2c.demand_miss_rate::0 0.039267 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.039164 # miss rate for demand accesses +system.l2c.demand_miss_rate::2 0.701727 # miss rate for demand accesses +system.l2c.demand_miss_rate::3 0.214099 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.994258 # miss rate for demand accesses +system.l2c.demand_misses::0 15 # number of demand (read+write) misses +system.l2c.demand_misses::1 15 # number of demand (read+write) misses +system.l2c.demand_misses::2 447 # number of demand (read+write) misses +system.l2c.demand_misses::3 82 # number of demand (read+write) misses +system.l2c.demand_misses::total 559 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::2 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::3 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 1785 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 0 # average overall miss latency +system.l2c.occ_%::0 0.000044 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.000029 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.004314 # Average percentage of cache occupancy +system.l2c.occ_%::3 0.001011 # Average percentage of cache occupancy +system.l2c.occ_%::4 0.000098 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 2.865859 # Average occupied blocks per context +system.l2c.occ_blocks::1 1.883074 # Average occupied blocks per context +system.l2c.occ_blocks::2 282.753459 # Average occupied blocks per context +system.l2c.occ_blocks::3 66.228089 # Average occupied blocks per context +system.l2c.occ_blocks::4 6.390048 # Average occupied blocks per context +system.l2c.overall_accesses::0 382 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 383 # number of overall (read+write) accesses +system.l2c.overall_accesses::2 637 # number of overall (read+write) accesses +system.l2c.overall_accesses::3 383 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1785 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::3 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.overall_hits 1226 # number of overall hits +system.l2c.overall_hits::0 367 # number of overall hits +system.l2c.overall_hits::1 368 # number of overall hits +system.l2c.overall_hits::2 190 # number of overall hits +system.l2c.overall_hits::3 301 # number of overall hits +system.l2c.overall_hits::total 1226 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate 0.313165 # miss rate for overall accesses -system.l2c.overall_misses 559 # number of overall misses +system.l2c.overall_miss_rate::0 0.039267 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.039164 # miss rate for overall accesses +system.l2c.overall_miss_rate::2 0.701727 # miss rate for overall accesses +system.l2c.overall_miss_rate::3 0.214099 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.994258 # miss rate for overall accesses +system.l2c.overall_misses::0 15 # number of overall misses +system.l2c.overall_misses::1 15 # number of overall misses +system.l2c.overall_misses::2 447 # number of overall misses +system.l2c.overall_misses::3 82 # number of overall misses +system.l2c.overall_misses::total 559 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::2 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::3 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses system.l2c.overall_mshr_misses 0 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini index c778c454d..f3434ec9b 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini @@ -45,7 +45,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -80,7 +80,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -116,7 +116,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 @@ -163,7 +163,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -198,7 +198,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -262,7 +262,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -297,7 +297,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -361,7 +361,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -396,7 +396,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -434,7 +434,7 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=92 -prefetch_cache_check_push=true +num_cpus=4 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr index eabe42249..eabe42249 100644..100755 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout index 304f6e9bf..a76dcd8cb 100644..100755 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2009 06:58:47 -M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff -M5 started Apr 22 2009 07:32:59 -M5 executing on maize +M5 compiled Feb 25 2010 03:11:27 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 03:38:17 +M5 executing on SC2B0619 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index bfbb72508..a432347b0 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1057647 # Simulator instruction rate (inst/s) -host_mem_usage 211204 # Number of bytes of host memory used -host_seconds 0.62 # Real time elapsed on the host -host_tick_rate 427981185 # Simulator tick rate (ticks/s) +host_inst_rate 920855 # Simulator instruction rate (inst/s) +host_mem_usage 198472 # Number of bytes of host memory used +host_seconds 0.71 # Real time elapsed on the host +host_tick_rate 372636983 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 650423 # Number of instructions simulated sim_seconds 0.000263 # Number of seconds simulated @@ -60,6 +60,8 @@ system.cpu0.dcache.demand_mshr_misses 262 # nu system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.occ_%::0 0.048480 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::0 24.821539 # Average occupied blocks per context system.cpu0.dcache.overall_accesses 56889 # number of overall (read+write) accesses system.cpu0.dcache.overall_avg_miss_latency 16950.381679 # average overall miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency 13950.381679 # average overall mshr miss latency @@ -113,6 +115,8 @@ system.cpu0.icache.demand_mshr_misses 358 # nu system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.occ_%::0 0.127582 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::0 65.321793 # Average occupied blocks per context system.cpu0.icache.overall_accesses 161568 # number of overall (read+write) accesses system.cpu0.icache.overall_avg_miss_latency 14758.379888 # average overall miss latency system.cpu0.icache.overall_avg_mshr_miss_latency 11758.379888 # average overall mshr miss latency @@ -192,6 +196,8 @@ system.cpu1.dcache.demand_mshr_misses 262 # nu system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.occ_%::0 0.049924 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 25.561342 # Average occupied blocks per context system.cpu1.dcache.overall_accesses 56189 # number of overall (read+write) accesses system.cpu1.dcache.overall_avg_miss_latency 17095.419847 # average overall miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency 14095.419847 # average overall mshr miss latency @@ -245,6 +251,8 @@ system.cpu1.icache.demand_mshr_misses 359 # nu system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.occ_%::0 0.131739 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 67.450287 # Average occupied blocks per context system.cpu1.icache.overall_accesses 162202 # number of overall (read+write) accesses system.cpu1.icache.overall_avg_miss_latency 14391.364903 # average overall miss latency system.cpu1.icache.overall_avg_mshr_miss_latency 11391.364903 # average overall mshr miss latency @@ -323,6 +331,8 @@ system.cpu2.dcache.demand_mshr_misses 362 # nu system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.dcache.occ_%::0 0.275555 # Average percentage of cache occupancy +system.cpu2.dcache.occ_blocks::0 141.084106 # Average occupied blocks per context system.cpu2.dcache.overall_accesses 73844 # number of overall (read+write) accesses system.cpu2.dcache.overall_avg_miss_latency 35787.292818 # average overall miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency 32787.292818 # average overall mshr miss latency @@ -376,6 +386,8 @@ system.cpu2.icache.demand_mshr_misses 467 # nu system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.icache.occ_%::0 0.414415 # Average percentage of cache occupancy +system.cpu2.icache.occ_blocks::0 212.180630 # Average occupied blocks per context system.cpu2.icache.overall_accesses 158416 # number of overall (read+write) accesses system.cpu2.icache.overall_avg_miss_latency 39665.952891 # average overall miss latency system.cpu2.icache.overall_avg_mshr_miss_latency 36665.952891 # average overall mshr miss latency @@ -454,6 +466,8 @@ system.cpu3.dcache.demand_mshr_misses 276 # nu system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.dcache.occ_%::0 0.051885 # Average percentage of cache occupancy +system.cpu3.dcache.occ_blocks::0 26.564950 # Average occupied blocks per context system.cpu3.dcache.overall_accesses 46826 # number of overall (read+write) accesses system.cpu3.dcache.overall_avg_miss_latency 19681.159420 # average overall miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency 16681.159420 # average overall mshr miss latency @@ -507,6 +521,8 @@ system.cpu3.icache.demand_mshr_misses 358 # nu system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.icache.occ_%::0 0.136289 # Average percentage of cache occupancy +system.cpu3.icache.occ_blocks::0 69.779720 # Average occupied blocks per context system.cpu3.icache.overall_accesses 168396 # number of overall (read+write) accesses system.cpu3.icache.overall_avg_miss_latency 21104.748603 # average overall miss latency system.cpu3.icache.overall_avg_mshr_miss_latency 18103.351955 # average overall mshr miss latency @@ -533,37 +549,103 @@ system.cpu3.not_idle_fraction 0.865927 # Pe system.cpu3.numCycles 515096 # number of cpu cycles simulated system.cpu3.num_insts 168364 # Number of instructions executed system.cpu3.num_refs 46919 # Number of memory references -system.l2c.ReadExReq_accesses 136 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::2 99 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::3 13 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 589333.333333 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 589333.333333 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::2 71434.343434 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::3 544000 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 1794101.010101 # average ReadExReq miss latency system.l2c.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency system.l2c.ReadExReq_miss_latency 7072000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 136 # number of ReadExReq misses +system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::2 99 # number of ReadExReq misses +system.l2c.ReadExReq_misses::3 13 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses system.l2c.ReadExReq_mshr_miss_latency 5440000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 11.333333 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 11.333333 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::2 1.373737 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::3 10.461538 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 34.501943 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_misses 136 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 1649 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 51941.724942 # average ReadReq miss latency +system.l2c.ReadReq_accesses::0 370 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 371 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::2 538 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::3 370 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1649 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 3183285.714286 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 5570750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::2 63484.330484 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::3 332582.089552 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 9150102.134322 # average ReadReq miss latency system.l2c.ReadReq_avg_mshr_miss_latency 40007.092199 # average ReadReq mshr miss latency -system.l2c.ReadReq_hits 1220 # number of ReadReq hits +system.l2c.ReadReq_hits::0 363 # number of ReadReq hits +system.l2c.ReadReq_hits::1 367 # number of ReadReq hits +system.l2c.ReadReq_hits::2 187 # number of ReadReq hits +system.l2c.ReadReq_hits::3 303 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits system.l2c.ReadReq_miss_latency 22283000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.260158 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 429 # number of ReadReq misses +system.l2c.ReadReq_miss_rate::0 0.018919 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.010782 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::2 0.652416 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::3 0.181081 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.863198 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 7 # number of ReadReq misses +system.l2c.ReadReq_misses::1 4 # number of ReadReq misses +system.l2c.ReadReq_misses::2 351 # number of ReadReq misses +system.l2c.ReadReq_misses::3 67 # number of ReadReq misses +system.l2c.ReadReq_misses::total 429 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_miss_latency 16923000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.256519 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::0 1.143243 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 1.140162 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::2 0.786245 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::3 1.143243 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 4.212894 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_misses 423 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_accesses 91 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 11428.571429 # average UpgradeReq miss latency +system.l2c.UpgradeReq_accesses::0 16 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 16 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::2 47 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::3 12 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 91 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 65000 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 65000 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::2 22127.659574 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::3 86666.666667 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 238794.326241 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_miss_latency 1040000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 91 # number of UpgradeReq misses +system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 4 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 16 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 16 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::2 47 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::3 12 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 91 # number of UpgradeReq misses system.l2c.UpgradeReq_mshr_miss_latency 3640000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 5.687500 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 5.687500 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::2 1.936170 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::3 7.583333 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 20.894504 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_misses 91 # number of UpgradeReq MSHR misses -system.l2c.Writeback_accesses 9 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 9 # number of Writeback hits +system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 9 # number of Writeback hits +system.l2c.Writeback_hits::total 9 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.avg_refs 2.953883 # Average number of references to valid blocks. @@ -572,31 +654,89 @@ system.l2c.blocked::no_targets 0 # nu system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 1785 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 51955.752212 # average overall miss latency +system.l2c.demand_accesses::0 382 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 383 # number of demand (read+write) accesses +system.l2c.demand_accesses::2 637 # number of demand (read+write) accesses +system.l2c.demand_accesses::3 383 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1785 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 1545000 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 1834687.500000 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 65233.333333 # average overall miss latency +system.l2c.demand_avg_miss_latency::3 366937.500000 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 3811858.333333 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency 40005.366726 # average overall mshr miss latency -system.l2c.demand_hits 1220 # number of demand (read+write) hits +system.l2c.demand_hits::0 363 # number of demand (read+write) hits +system.l2c.demand_hits::1 367 # number of demand (read+write) hits +system.l2c.demand_hits::2 187 # number of demand (read+write) hits +system.l2c.demand_hits::3 303 # number of demand (read+write) hits +system.l2c.demand_hits::total 1220 # number of demand (read+write) hits system.l2c.demand_miss_latency 29355000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.316527 # miss rate for demand accesses -system.l2c.demand_misses 565 # number of demand (read+write) misses +system.l2c.demand_miss_rate::0 0.049738 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.041775 # miss rate for demand accesses +system.l2c.demand_miss_rate::2 0.706436 # miss rate for demand accesses +system.l2c.demand_miss_rate::3 0.208877 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 1.006827 # miss rate for demand accesses +system.l2c.demand_misses::0 19 # number of demand (read+write) misses +system.l2c.demand_misses::1 16 # number of demand (read+write) misses +system.l2c.demand_misses::2 450 # number of demand (read+write) misses +system.l2c.demand_misses::3 80 # number of demand (read+write) misses +system.l2c.demand_misses::total 565 # number of demand (read+write) misses system.l2c.demand_mshr_hits 6 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 22363000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.313165 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 1.463351 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.459530 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::2 0.877551 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::3 1.459530 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 5.259962 # mshr miss rate for demand accesses system.l2c.demand_mshr_misses 559 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 1785 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 51955.752212 # average overall miss latency +system.l2c.occ_%::0 0.000040 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.000026 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.004171 # Average percentage of cache occupancy +system.l2c.occ_%::3 0.000879 # Average percentage of cache occupancy +system.l2c.occ_%::4 0.000085 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 2.602775 # Average occupied blocks per context +system.l2c.occ_blocks::1 1.727475 # Average occupied blocks per context +system.l2c.occ_blocks::2 273.330650 # Average occupied blocks per context +system.l2c.occ_blocks::3 57.582989 # Average occupied blocks per context +system.l2c.occ_blocks::4 5.583152 # Average occupied blocks per context +system.l2c.overall_accesses::0 382 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 383 # number of overall (read+write) accesses +system.l2c.overall_accesses::2 637 # number of overall (read+write) accesses +system.l2c.overall_accesses::3 383 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1785 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 1545000 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 1834687.500000 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 65233.333333 # average overall miss latency +system.l2c.overall_avg_miss_latency::3 366937.500000 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 3811858.333333 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency 40005.366726 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.overall_hits 1220 # number of overall hits +system.l2c.overall_hits::0 363 # number of overall hits +system.l2c.overall_hits::1 367 # number of overall hits +system.l2c.overall_hits::2 187 # number of overall hits +system.l2c.overall_hits::3 303 # number of overall hits +system.l2c.overall_hits::total 1220 # number of overall hits system.l2c.overall_miss_latency 29355000 # number of overall miss cycles -system.l2c.overall_miss_rate 0.316527 # miss rate for overall accesses -system.l2c.overall_misses 565 # number of overall misses +system.l2c.overall_miss_rate::0 0.049738 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.041775 # miss rate for overall accesses +system.l2c.overall_miss_rate::2 0.706436 # miss rate for overall accesses +system.l2c.overall_miss_rate::3 0.208877 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 1.006827 # miss rate for overall accesses +system.l2c.overall_misses::0 19 # number of overall misses +system.l2c.overall_misses::1 16 # number of overall misses +system.l2c.overall_misses::2 450 # number of overall misses +system.l2c.overall_misses::3 80 # number of overall misses +system.l2c.overall_misses::total 565 # number of overall misses system.l2c.overall_mshr_hits 6 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 22363000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.313165 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 1.463351 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.459530 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::2 0.877551 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::3 1.459530 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 5.259962 # mshr miss rate for overall accesses system.l2c.overall_mshr_misses 559 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini index bb5089d27..bebc4169c 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini @@ -35,7 +35,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=12 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -82,7 +82,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=12 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -129,7 +129,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=12 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -176,7 +176,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=12 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -223,7 +223,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=12 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -270,7 +270,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=12 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -317,7 +317,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=12 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -364,7 +364,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=12 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -405,7 +405,7 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=92 -prefetch_cache_check_push=true +num_cpus=8 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout index eb87c125b..ae0afe01d 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2009 06:58:26 -M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff -M5 started Apr 22 2009 07:17:27 -M5 executing on maize +M5 compiled Feb 24 2010 23:12:40 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 02:22:18 +M5 executing on SC2B0619 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt index 0be961e27..7eeff6062 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -1,8 +1,8 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 328320 # Number of bytes of host memory used -host_seconds 137.46 # Real time elapsed on the host -host_tick_rate 1956295 # Simulator tick rate (ticks/s) +host_mem_usage 316880 # Number of bytes of host memory used +host_seconds 287.16 # Real time elapsed on the host +host_tick_rate 936456 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_seconds 0.000269 # Number of seconds simulated sim_ticks 268915439 # Number of ticks simulated @@ -52,6 +52,10 @@ system.cpu0.l1c.demand_mshr_misses 60767 # nu system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.l1c.occ_%::0 0.679849 # Average percentage of cache occupancy +system.cpu0.l1c.occ_%::1 -0.004028 # Average percentage of cache occupancy +system.cpu0.l1c.occ_blocks::0 348.082504 # Average occupied blocks per context +system.cpu0.l1c.occ_blocks::1 -2.062462 # Average occupied blocks per context system.cpu0.l1c.overall_accesses 69441 # number of overall (read+write) accesses system.cpu0.l1c.overall_avg_miss_latency 40312.026198 # average overall miss latency system.cpu0.l1c.overall_avg_mshr_miss_latency 39308.156285 # average overall mshr miss latency @@ -122,6 +126,10 @@ system.cpu1.l1c.demand_mshr_misses 60450 # nu system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.l1c.occ_%::0 0.675435 # Average percentage of cache occupancy +system.cpu1.l1c.occ_%::1 -0.006011 # Average percentage of cache occupancy +system.cpu1.l1c.occ_blocks::0 345.822577 # Average occupied blocks per context +system.cpu1.l1c.occ_blocks::1 -3.077398 # Average occupied blocks per context system.cpu1.l1c.overall_accesses 69001 # number of overall (read+write) accesses system.cpu1.l1c.overall_avg_miss_latency 40493.835004 # average overall miss latency system.cpu1.l1c.overall_avg_mshr_miss_latency 39489.965492 # average overall mshr miss latency @@ -192,6 +200,10 @@ system.cpu2.l1c.demand_mshr_misses 60562 # nu system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.l1c.occ_%::0 0.678453 # Average percentage of cache occupancy +system.cpu2.l1c.occ_%::1 -0.001793 # Average percentage of cache occupancy +system.cpu2.l1c.occ_blocks::0 347.368052 # Average occupied blocks per context +system.cpu2.l1c.occ_blocks::1 -0.918043 # Average occupied blocks per context system.cpu2.l1c.overall_accesses 68999 # number of overall (read+write) accesses system.cpu2.l1c.overall_avg_miss_latency 40589.092748 # average overall miss latency system.cpu2.l1c.overall_avg_mshr_miss_latency 39585.239540 # average overall mshr miss latency @@ -262,6 +274,10 @@ system.cpu3.l1c.demand_mshr_misses 60533 # nu system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.l1c.occ_%::0 0.676337 # Average percentage of cache occupancy +system.cpu3.l1c.occ_%::1 -0.001850 # Average percentage of cache occupancy +system.cpu3.l1c.occ_blocks::0 346.284781 # Average occupied blocks per context +system.cpu3.l1c.occ_blocks::1 -0.947285 # Average occupied blocks per context system.cpu3.l1c.overall_accesses 69068 # number of overall (read+write) accesses system.cpu3.l1c.overall_avg_miss_latency 40627.332546 # average overall miss latency system.cpu3.l1c.overall_avg_mshr_miss_latency 39623.396594 # average overall mshr miss latency @@ -332,6 +348,10 @@ system.cpu4.l1c.demand_mshr_misses 60418 # nu system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu4.l1c.occ_%::0 0.676775 # Average percentage of cache occupancy +system.cpu4.l1c.occ_%::1 -0.003496 # Average percentage of cache occupancy +system.cpu4.l1c.occ_blocks::0 346.508789 # Average occupied blocks per context +system.cpu4.l1c.occ_blocks::1 -1.790088 # Average occupied blocks per context system.cpu4.l1c.overall_accesses 68853 # number of overall (read+write) accesses system.cpu4.l1c.overall_avg_miss_latency 40544.624979 # average overall miss latency system.cpu4.l1c.overall_avg_mshr_miss_latency 39540.822139 # average overall mshr miss latency @@ -402,6 +422,10 @@ system.cpu5.l1c.demand_mshr_misses 60470 # nu system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu5.l1c.occ_%::0 0.676296 # Average percentage of cache occupancy +system.cpu5.l1c.occ_%::1 -0.006346 # Average percentage of cache occupancy +system.cpu5.l1c.occ_blocks::0 346.263302 # Average occupied blocks per context +system.cpu5.l1c.occ_blocks::1 -3.249085 # Average occupied blocks per context system.cpu5.l1c.overall_accesses 68832 # number of overall (read+write) accesses system.cpu5.l1c.overall_avg_miss_latency 40557.685431 # average overall miss latency system.cpu5.l1c.overall_avg_mshr_miss_latency 39553.832148 # average overall mshr miss latency @@ -472,6 +496,10 @@ system.cpu6.l1c.demand_mshr_misses 60973 # nu system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu6.l1c.occ_%::0 0.675041 # Average percentage of cache occupancy +system.cpu6.l1c.occ_%::1 -0.003803 # Average percentage of cache occupancy +system.cpu6.l1c.occ_blocks::0 345.621031 # Average occupied blocks per context +system.cpu6.l1c.occ_blocks::1 -1.947349 # Average occupied blocks per context system.cpu6.l1c.overall_accesses 69369 # number of overall (read+write) accesses system.cpu6.l1c.overall_avg_miss_latency 40232.426927 # average overall miss latency system.cpu6.l1c.overall_avg_mshr_miss_latency 39228.572713 # average overall mshr miss latency @@ -542,6 +570,10 @@ system.cpu7.l1c.demand_mshr_misses 60440 # nu system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu7.l1c.occ_%::0 0.676947 # Average percentage of cache occupancy +system.cpu7.l1c.occ_%::1 -0.001736 # Average percentage of cache occupancy +system.cpu7.l1c.occ_blocks::0 346.596700 # Average occupied blocks per context +system.cpu7.l1c.occ_blocks::1 -0.888916 # Average occupied blocks per context system.cpu7.l1c.overall_accesses 68921 # number of overall (read+write) accesses system.cpu7.l1c.overall_avg_miss_latency 40632.412244 # average overall miss latency system.cpu7.l1c.overall_avg_mshr_miss_latency 39628.493084 # average overall mshr miss latency @@ -566,43 +598,173 @@ system.cpu7.l1c.writebacks 10984 # nu system.cpu7.num_copies 0 # number of copy accesses completed system.cpu7.num_reads 99634 # number of read accesses completed system.cpu7.num_writes 53744 # number of write accesses completed -system.l2c.ReadExReq_accesses 75142 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 49861.980677 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 9360 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 9426 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::2 9454 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::3 9421 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::4 9377 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::5 9282 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::6 9385 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::7 9437 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 75142 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 400291.554701 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 397488.749417 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::2 396311.503279 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::3 397699.708311 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::4 399565.847499 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::5 403655.349278 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::6 399225.247949 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::7 397025.426725 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 3191263.387158 # average ReadExReq miss latency system.l2c.ReadExReq_avg_mshr_miss_latency 39995.605218 # average ReadExReq mshr miss latency system.l2c.ReadExReq_miss_latency 3746728952 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 75142 # number of ReadExReq misses +system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::4 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::5 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::6 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::7 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 8 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 9360 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 9426 # number of ReadExReq misses +system.l2c.ReadExReq_misses::2 9454 # number of ReadExReq misses +system.l2c.ReadExReq_misses::3 9421 # number of ReadExReq misses +system.l2c.ReadExReq_misses::4 9377 # number of ReadExReq misses +system.l2c.ReadExReq_misses::5 9282 # number of ReadExReq misses +system.l2c.ReadExReq_misses::6 9385 # number of ReadExReq misses +system.l2c.ReadExReq_misses::7 9437 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 75142 # number of ReadExReq misses system.l2c.ReadExReq_mshr_hits 587 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_miss_latency 2981872347 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate 0.992188 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 7.965278 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 7.909506 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::2 7.886080 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::3 7.913703 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::4 7.950837 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::5 8.032213 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::6 7.944060 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::7 7.900286 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 63.501963 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_misses 74555 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 137922 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 49640.109276 # average ReadReq miss latency +system.l2c.ReadReq_accesses::0 17364 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 17185 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::2 17073 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::3 17340 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::4 17244 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::5 17349 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::6 17201 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::7 17166 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 137922 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 396394.393314 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 396328.481377 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::2 399048.968190 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::3 396065.052675 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::4 402281.769958 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::5 398581.854013 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::6 391254.019534 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::7 397187.049992 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 3177141.589053 # average ReadReq miss latency system.l2c.ReadReq_avg_mshr_miss_latency 39996.564362 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits 89906 # number of ReadReq hits +system.l2c.ReadReq_hits::0 11351 # number of ReadReq hits +system.l2c.ReadReq_hits::1 11171 # number of ReadReq hits +system.l2c.ReadReq_hits::2 11100 # number of ReadReq hits +system.l2c.ReadReq_hits::3 11322 # number of ReadReq hits +system.l2c.ReadReq_hits::4 11319 # number of ReadReq hits +system.l2c.ReadReq_hits::5 11369 # number of ReadReq hits +system.l2c.ReadReq_hits::6 11109 # number of ReadReq hits +system.l2c.ReadReq_hits::7 11165 # number of ReadReq hits +system.l2c.ReadReq_hits::total 89906 # number of ReadReq hits system.l2c.ReadReq_miss_latency 2383519487 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.348139 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 48016 # number of ReadReq misses +system.l2c.ReadReq_miss_rate::0 0.346291 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.349956 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::2 0.349851 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::3 0.347059 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::4 0.343598 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::5 0.344688 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::6 0.354165 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::7 0.349586 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 2.785195 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 6013 # number of ReadReq misses +system.l2c.ReadReq_misses::1 6014 # number of ReadReq misses +system.l2c.ReadReq_misses::2 5973 # number of ReadReq misses +system.l2c.ReadReq_misses::3 6018 # number of ReadReq misses +system.l2c.ReadReq_misses::4 5925 # number of ReadReq misses +system.l2c.ReadReq_misses::5 5980 # number of ReadReq misses +system.l2c.ReadReq_misses::6 6092 # number of ReadReq misses +system.l2c.ReadReq_misses::7 6001 # number of ReadReq misses +system.l2c.ReadReq_misses::total 48016 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 1016 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_miss_latency 1879838525 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.340772 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::0 2.706750 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 2.734943 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::2 2.752885 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::3 2.710496 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::4 2.725586 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::5 2.709090 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::6 2.732399 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::7 2.737970 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 21.810119 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_misses 47000 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_uncacheable_latency 3163753169 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses 18428 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 27998.751357 # average UpgradeReq miss latency +system.l2c.UpgradeReq_accesses::0 2273 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 2288 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::2 2314 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::3 2311 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::4 2383 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::5 2289 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::6 2257 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::7 2313 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18428 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 226995.596128 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 225507.425699 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::2 222973.634399 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::3 223263.085244 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::4 216517.410827 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::5 225408.907820 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::6 228604.780682 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::7 223070.034587 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1792340.875388 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency 39992.012512 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_miss_latency 515960990 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 18428 # number of UpgradeReq misses +system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::4 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::5 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::6 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::7 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 8 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 2273 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 2288 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::2 2314 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::3 2311 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::4 2383 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::5 2289 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::6 2257 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::7 2313 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 18428 # number of UpgradeReq misses system.l2c.UpgradeReq_mshr_hits 45 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_miss_latency 735173166 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate 0.997558 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 8.087549 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 8.034528 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::2 7.944252 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::3 7.954565 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::4 7.714226 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::5 8.031018 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::6 8.144883 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::7 7.947687 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 63.858708 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_misses 18383 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_mshr_uncacheable_latency 1717039696 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses 86929 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 86929 # number of Writeback hits +system.l2c.Writeback_accesses::0 86929 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 86929 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 86929 # number of Writeback hits +system.l2c.Writeback_hits::total 86929 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs 7154.090909 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.avg_refs 2.005630 # Average number of references to valid blocks. @@ -611,31 +773,145 @@ system.l2c.blocked::no_targets 0 # nu system.l2c.blocked_cycles::no_mshrs 78695 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 213064 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 49775.478970 # average overall miss latency +system.l2c.demand_accesses::0 26724 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 26611 # number of demand (read+write) accesses +system.l2c.demand_accesses::2 26527 # number of demand (read+write) accesses +system.l2c.demand_accesses::3 26761 # number of demand (read+write) accesses +system.l2c.demand_accesses::4 26621 # number of demand (read+write) accesses +system.l2c.demand_accesses::5 26631 # number of demand (read+write) accesses +system.l2c.demand_accesses::6 26586 # number of demand (read+write) accesses +system.l2c.demand_accesses::7 26603 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 213064 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 398767.217784 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 397036.815997 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 397371.390355 # average overall miss latency +system.l2c.demand_avg_miss_latency::3 397062.532483 # average overall miss latency +system.l2c.demand_avg_miss_latency::4 400617.464318 # average overall miss latency +system.l2c.demand_avg_miss_latency::5 401667.438016 # average overall miss latency +system.l2c.demand_avg_miss_latency::6 396087.642243 # average overall miss latency +system.l2c.demand_avg_miss_latency::7 397088.252300 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 3185698.753496 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency 39995.976077 # average overall mshr miss latency -system.l2c.demand_hits 89906 # number of demand (read+write) hits +system.l2c.demand_hits::0 11351 # number of demand (read+write) hits +system.l2c.demand_hits::1 11171 # number of demand (read+write) hits +system.l2c.demand_hits::2 11100 # number of demand (read+write) hits +system.l2c.demand_hits::3 11322 # number of demand (read+write) hits +system.l2c.demand_hits::4 11319 # number of demand (read+write) hits +system.l2c.demand_hits::5 11369 # number of demand (read+write) hits +system.l2c.demand_hits::6 11109 # number of demand (read+write) hits +system.l2c.demand_hits::7 11165 # number of demand (read+write) hits +system.l2c.demand_hits::total 89906 # number of demand (read+write) hits system.l2c.demand_miss_latency 6130248439 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.578033 # miss rate for demand accesses -system.l2c.demand_misses 123158 # number of demand (read+write) misses +system.l2c.demand_miss_rate::0 0.575251 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.580211 # miss rate for demand accesses +system.l2c.demand_miss_rate::2 0.581558 # miss rate for demand accesses +system.l2c.demand_miss_rate::3 0.576922 # miss rate for demand accesses +system.l2c.demand_miss_rate::4 0.574809 # miss rate for demand accesses +system.l2c.demand_miss_rate::5 0.573092 # miss rate for demand accesses +system.l2c.demand_miss_rate::6 0.582148 # miss rate for demand accesses +system.l2c.demand_miss_rate::7 0.580310 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 4.624302 # miss rate for demand accesses +system.l2c.demand_misses::0 15373 # number of demand (read+write) misses +system.l2c.demand_misses::1 15440 # number of demand (read+write) misses +system.l2c.demand_misses::2 15427 # number of demand (read+write) misses +system.l2c.demand_misses::3 15439 # number of demand (read+write) misses +system.l2c.demand_misses::4 15302 # number of demand (read+write) misses +system.l2c.demand_misses::5 15262 # number of demand (read+write) misses +system.l2c.demand_misses::6 15477 # number of demand (read+write) misses +system.l2c.demand_misses::7 15438 # number of demand (read+write) misses +system.l2c.demand_misses::total 123158 # number of demand (read+write) misses system.l2c.demand_mshr_hits 1603 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 4861710872 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.570509 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 4.548533 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 4.567848 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::2 4.582312 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::3 4.542244 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::4 4.566132 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::5 4.564417 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::6 4.572143 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::7 4.569222 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 36.512852 # mshr miss rate for demand accesses system.l2c.demand_mshr_misses 121555 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 213064 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 49775.478970 # average overall miss latency +system.l2c.occ_%::0 0.025896 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.025716 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.025892 # Average percentage of cache occupancy +system.l2c.occ_%::3 0.026232 # Average percentage of cache occupancy +system.l2c.occ_%::4 0.025792 # Average percentage of cache occupancy +system.l2c.occ_%::5 0.026195 # Average percentage of cache occupancy +system.l2c.occ_%::6 0.026471 # Average percentage of cache occupancy +system.l2c.occ_%::7 0.026663 # Average percentage of cache occupancy +system.l2c.occ_%::8 0.410030 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 26.517416 # Average occupied blocks per context +system.l2c.occ_blocks::1 26.332816 # Average occupied blocks per context +system.l2c.occ_blocks::2 26.512954 # Average occupied blocks per context +system.l2c.occ_blocks::3 26.861209 # Average occupied blocks per context +system.l2c.occ_blocks::4 26.410697 # Average occupied blocks per context +system.l2c.occ_blocks::5 26.823356 # Average occupied blocks per context +system.l2c.occ_blocks::6 27.106140 # Average occupied blocks per context +system.l2c.occ_blocks::7 27.302482 # Average occupied blocks per context +system.l2c.occ_blocks::8 419.870758 # Average occupied blocks per context +system.l2c.overall_accesses::0 26724 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 26611 # number of overall (read+write) accesses +system.l2c.overall_accesses::2 26527 # number of overall (read+write) accesses +system.l2c.overall_accesses::3 26761 # number of overall (read+write) accesses +system.l2c.overall_accesses::4 26621 # number of overall (read+write) accesses +system.l2c.overall_accesses::5 26631 # number of overall (read+write) accesses +system.l2c.overall_accesses::6 26586 # number of overall (read+write) accesses +system.l2c.overall_accesses::7 26603 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 213064 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 398767.217784 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 397036.815997 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 397371.390355 # average overall miss latency +system.l2c.overall_avg_miss_latency::3 397062.532483 # average overall miss latency +system.l2c.overall_avg_miss_latency::4 400617.464318 # average overall miss latency +system.l2c.overall_avg_miss_latency::5 401667.438016 # average overall miss latency +system.l2c.overall_avg_miss_latency::6 396087.642243 # average overall miss latency +system.l2c.overall_avg_miss_latency::7 397088.252300 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 3185698.753496 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency 39995.976077 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits 89906 # number of overall hits +system.l2c.overall_hits::0 11351 # number of overall hits +system.l2c.overall_hits::1 11171 # number of overall hits +system.l2c.overall_hits::2 11100 # number of overall hits +system.l2c.overall_hits::3 11322 # number of overall hits +system.l2c.overall_hits::4 11319 # number of overall hits +system.l2c.overall_hits::5 11369 # number of overall hits +system.l2c.overall_hits::6 11109 # number of overall hits +system.l2c.overall_hits::7 11165 # number of overall hits +system.l2c.overall_hits::total 89906 # number of overall hits system.l2c.overall_miss_latency 6130248439 # number of overall miss cycles -system.l2c.overall_miss_rate 0.578033 # miss rate for overall accesses -system.l2c.overall_misses 123158 # number of overall misses +system.l2c.overall_miss_rate::0 0.575251 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.580211 # miss rate for overall accesses +system.l2c.overall_miss_rate::2 0.581558 # miss rate for overall accesses +system.l2c.overall_miss_rate::3 0.576922 # miss rate for overall accesses +system.l2c.overall_miss_rate::4 0.574809 # miss rate for overall accesses +system.l2c.overall_miss_rate::5 0.573092 # miss rate for overall accesses +system.l2c.overall_miss_rate::6 0.582148 # miss rate for overall accesses +system.l2c.overall_miss_rate::7 0.580310 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 4.624302 # miss rate for overall accesses +system.l2c.overall_misses::0 15373 # number of overall misses +system.l2c.overall_misses::1 15440 # number of overall misses +system.l2c.overall_misses::2 15427 # number of overall misses +system.l2c.overall_misses::3 15439 # number of overall misses +system.l2c.overall_misses::4 15302 # number of overall misses +system.l2c.overall_misses::5 15262 # number of overall misses +system.l2c.overall_misses::6 15477 # number of overall misses +system.l2c.overall_misses::7 15438 # number of overall misses +system.l2c.overall_misses::total 123158 # number of overall misses system.l2c.overall_mshr_hits 1603 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 4861710872 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.570509 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 4.548533 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 4.567848 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::2 4.582312 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::3 4.542244 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::4 4.566132 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::5 4.564417 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::6 4.572143 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::7 4.569222 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 36.512852 # mshr miss rate for overall accesses system.l2c.overall_mshr_misses 121555 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 4880792865 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini index 6c3647fa4..83f000f15 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini @@ -8,13 +8,13 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus membus physmem simple_disk terminal tsunami boot_cpu_frequency=1 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux mem_mode=atomic -pal=/dist/m5/system/binaries/ts_osfpal +pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal physmem=drivesys.physmem -readfile=/z/stever/hg/m5/configs/boot/netperf-server.rcS +readfile=/proj/aatl_perfmod_arch/users/lihsu/m5/m5/configs/boot/netperf-server.rcS symbolfile= system_rev=1024 system_type=34 @@ -95,7 +95,7 @@ table_size=65536 [drivesys.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img read_only=true [drivesys.disk2] @@ -115,7 +115,7 @@ table_size=65536 [drivesys.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img read_only=true [drivesys.intrctrl] @@ -179,7 +179,7 @@ system=drivesys [drivesys.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img read_only=true [drivesys.terminal] @@ -712,13 +712,13 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus membus physmem simple_disk terminal tsunami boot_cpu_frequency=1 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux mem_mode=atomic -pal=/dist/m5/system/binaries/ts_osfpal +pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal physmem=testsys.physmem -readfile=/z/stever/hg/m5/configs/boot/netperf-stream-client.rcS +readfile=/proj/aatl_perfmod_arch/users/lihsu/m5/m5/configs/boot/netperf-stream-client.rcS symbolfile= system_rev=1024 system_type=34 @@ -799,7 +799,7 @@ table_size=65536 [testsys.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img read_only=true [testsys.disk2] @@ -819,7 +819,7 @@ table_size=65536 [testsys.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img read_only=true [testsys.intrctrl] @@ -883,7 +883,7 @@ system=testsys [testsys.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img read_only=true [testsys.terminal] diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout index b398102fe..3d53e8197 100755 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 6 2009 11:02:48 -M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip -M5 started Jul 6 2009 11:10:47 -M5 executing on maize +M5 compiled Feb 24 2010 23:13:04 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 24 2010 23:13:12 +M5 executing on SC2B0619 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux +info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... Exiting @ tick 4300236804024 because checkpoint diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt index 29058cdda..72190af46 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt @@ -16,7 +16,7 @@ drivesys.cpu.dtb.write_accesses 133245 # DT drivesys.cpu.dtb.write_acv 10 # DTB write access violations drivesys.cpu.dtb.write_hits 230735 # DTB write hits drivesys.cpu.dtb.write_misses 82 # DTB write misses -drivesys.cpu.idle_fraction 1.000000 # Percentage of idle cycles +drivesys.cpu.idle_fraction 0.999990 # Percentage of idle cycles drivesys.cpu.itb.data_accesses 0 # DTB accesses drivesys.cpu.itb.data_acv 0 # DTB access violations drivesys.cpu.itb.data_hits 0 # DTB hits @@ -91,7 +91,7 @@ drivesys.cpu.kern.syscall::106 1 4.55% 86.36% # nu drivesys.cpu.kern.syscall::118 2 9.09% 95.45% # number of syscalls executed drivesys.cpu.kern.syscall::150 1 4.55% 100.00% # number of syscalls executed drivesys.cpu.kern.syscall::total 22 # number of syscalls executed -drivesys.cpu.not_idle_fraction 0.000000 # Percentage of non-idle cycles +drivesys.cpu.not_idle_fraction 0.000010 # Percentage of non-idle cycles drivesys.cpu.numCycles 199571362884 # number of cpu cycles simulated drivesys.cpu.num_insts 1958129 # Number of instructions executed drivesys.cpu.num_refs 626223 # Number of memory references @@ -155,10 +155,10 @@ drivesys.tsunami.ethernet.txPPS 25 # Pa drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -host_inst_rate 214917322 # Simulator instruction rate (inst/s) -host_mem_usage 463572 # Number of bytes of host memory used -host_seconds 1.27 # Real time elapsed on the host -host_tick_rate 157210213175 # Simulator tick rate (ticks/s) +host_inst_rate 70382622 # Simulator instruction rate (inst/s) +host_mem_usage 464660 # Number of bytes of host memory used +host_seconds 3.88 # Real time elapsed on the host +host_tick_rate 51489346502 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 273374833 # Number of instructions simulated sim_seconds 0.200001 # Number of seconds simulated @@ -179,7 +179,7 @@ testsys.cpu.dtb.write_accesses 109988 # DT testsys.cpu.dtb.write_acv 81 # DTB write access violations testsys.cpu.dtb.write_hits 504853 # DTB write hits testsys.cpu.dtb.write_misses 528 # DTB write misses -testsys.cpu.idle_fraction 0.999999 # Percentage of idle cycles +testsys.cpu.idle_fraction 0.999982 # Percentage of idle cycles testsys.cpu.itb.data_accesses 0 # DTB accesses testsys.cpu.itb.data_acv 0 # DTB access violations testsys.cpu.itb.data_hits 0 # DTB hits @@ -264,7 +264,7 @@ testsys.cpu.kern.syscall::104 1 1.20% 93.98% # nu testsys.cpu.kern.syscall::105 3 3.61% 97.59% # number of syscalls executed testsys.cpu.kern.syscall::118 2 2.41% 100.00% # number of syscalls executed testsys.cpu.kern.syscall::total 83 # number of syscalls executed -testsys.cpu.not_idle_fraction 0.000001 # Percentage of non-idle cycles +testsys.cpu.not_idle_fraction 0.000018 # Percentage of non-idle cycles testsys.cpu.numCycles 199569460393 # number of cpu cycles simulated testsys.cpu.num_insts 3560411 # Number of instructions executed testsys.cpu.num_refs 1173571 # Number of memory references @@ -429,10 +429,10 @@ drivesys.tsunami.ethernet.totalSwi 0 # to drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -host_inst_rate 134733776737 # Simulator instruction rate (inst/s) -host_mem_usage 463572 # Number of bytes of host memory used +host_inst_rate 166997454490 # Simulator instruction rate (inst/s) +host_mem_usage 464660 # Number of bytes of host memory used host_seconds 0.00 # Real time elapsed on the host -host_tick_rate 366594216 # Simulator tick rate (ticks/s) +host_tick_rate 453274510 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 273374833 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated |