diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2011-02-07 19:23:13 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2011-02-07 19:23:13 -0800 |
| commit | 0851580aada37c8e1b1d2b695100fbcfaf4e0946 (patch) | |
| tree | 96eea53d6309ddb9f4bfac61767e53bfcdb44037 /tests/quick | |
| parent | 1b64bfa933745294667158d0ce22180780b2a22e (diff) | |
| download | gem5-0851580aada37c8e1b1d2b695100fbcfaf4e0946.tar.xz | |
Stats: Re update stats.
Diffstat (limited to 'tests/quick')
158 files changed, 3291 insertions, 1781 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini index 0558e754e..92b040488 100644 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=InOrderCPU @@ -192,7 +201,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout index 98307cd85..254c4b8b1 100755 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 24 2011 18:18:02 -M5 revision 09e8ac96522d+ 7823+ default regression_updates qtip tip -M5 started Jan 24 2011 18:18:03 -M5 executing on zooks +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:37 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt index be248d562..246665e32 100644 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 36108 # Simulator instruction rate (inst/s) -host_mem_usage 155860 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host -host_tick_rate 125462283 # Simulator tick rate (ticks/s) +host_inst_rate 37548 # Simulator instruction rate (inst/s) +host_mem_usage 223436 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host +host_tick_rate 130476959 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000022 # Number of seconds simulated @@ -267,6 +267,8 @@ system.cpu.l2cache.total_refs 1 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.numCycles 44578 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.runCycles 7154 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index da67d287f..6d12585e0 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout index 7b6a1125b..517aaa9a6 100755 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 17 2011 16:24:53 -M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase -M5 started Jan 17 2011 16:24:57 -M5 executing on zizzer +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:37 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt index 72be64488..eda10e1bd 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 10121 # Simulator instruction rate (inst/s) -host_mem_usage 203516 # Number of bytes of host memory used -host_seconds 0.63 # Real time elapsed on the host -host_tick_rate 19665204 # Simulator tick rate (ticks/s) +host_inst_rate 34686 # Simulator instruction rate (inst/s) +host_mem_usage 223912 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host +host_tick_rate 67319594 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6386 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 12265 # Number of insts commited each cycle system.cpu.commit.COM:count 6403 # Number of instructions committed +system.cpu.commit.COM:fp_insts 10 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 127 # Number of function calls committed. +system.cpu.commit.COM:int_insts 6321 # Number of committed integer instructions. system.cpu.commit.COM:loads 1185 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 2050 # Number of memory references committed @@ -169,6 +172,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 13149 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 8 # number of floating regfile reads +system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.icache.ReadReq_accesses 1774 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 35292.253521 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35283.387622 # average ReadReq mshr miss latency @@ -268,6 +273,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 394 # system.cpu.iew.memOrderViolationEvents 63 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 303 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 11489 # number of integer regfile reads +system.cpu.int_regfile_writes 6462 # number of integer regfile writes system.cpu.ipc 0.257230 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.257230 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued @@ -359,6 +366,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 13149 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 0.373520 # Inst issue rate +system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 9351 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 31807 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 8672 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 14983 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 10848 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 9273 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ @@ -450,7 +465,11 @@ system.cpu.memDep0.conflictingLoads 34 # Nu system.cpu.memDep0.conflictingStores 26 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 2242 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1259 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1 # number of misc regfile reads +system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.numCycles 24826 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 346 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4583 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 8 # Number of times rename has blocked due to IQ full @@ -463,10 +482,14 @@ system.cpu.rename.RENAME:RunCycles 2180 # Nu system.cpu.rename.RENAME:SquashCycles 884 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 270 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 4300 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 17 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 15016 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 406 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 28 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 694 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 22718 # The number of ROB reads +system.cpu.rob.rob_writes 22732 # The number of ROB writes system.cpu.timesIdled 239 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini index d867b793e..14af20ce8 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -57,7 +66,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout index 0053084d5..b6cabe98f 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:01:37 -M5 executing on SC2B0619 +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:39 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt index 301281a5e..29c354685 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1228467 # Simulator instruction rate (inst/s) -host_mem_usage 182556 # Number of bytes of host memory used +host_inst_rate 474100 # Simulator instruction rate (inst/s) +host_mem_usage 215244 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 587751371 # Simulator tick rate (ticks/s) +host_tick_rate 233713954 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated @@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 6431 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 6431 # Number of busy cycles +system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses +system.cpu.num_fp_insts 10 # number of float instructions +system.cpu.num_fp_register_reads 8 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2 # number of times the floating registers were written +system.cpu.num_func_calls 251 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 6404 # Number of instructions executed -system.cpu.num_refs 2060 # Number of memory references +system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses +system.cpu.num_int_insts 6331 # number of integer instructions +system.cpu.num_int_register_reads 8304 # number of times the integer registers were read +system.cpu.num_int_register_writes 4581 # number of times the integer registers were written +system.cpu.num_load_insts 1192 # Number of load instructions +system.cpu.num_mem_refs 2060 # number of memory refs +system.cpu.num_store_insts 868 # Number of store instructions system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini index 3438ec60f..5053e806a 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 [system] type=System -children=cpu physmem ruby +children=cpu dir_cntrl0 l1_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -32,8 +41,8 @@ progress_interval=0 system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1] -icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] +dcache_port=system.ruby.cpu_ruby_ports.port[1] +icache_port=system.ruby.cpu_ruby_ports.port[0] [system.cpu.dtb] type=AlphaTLB @@ -54,7 +63,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -65,6 +74,59 @@ simpoint=0 system=system uid=100 +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +directory=system.dir_cntrl0.directory +directory_latency=12 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.l1_cntrl0] +type=L1Cache_Controller +buffer_size=0 +cacheMemory=system.ruby.cpu_ruby_ports.dcache +cache_response_latency=12 +issue_latency=2 +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.ruby.cpu_ruby_ports +transitions_per_cycle=32 +version=0 + [system.physmem] type=PhysicalMemory file= @@ -73,34 +135,48 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort +port=system.ruby.cpu_ruby_ports.physMemPort [system.ruby] type=RubySystem -children=debug network profiler tracer +children=cpu_ruby_ports network profiler tracer block_size_bytes=64 clock=1 -debug=system.ruby.debug mem_size=134217728 network=system.ruby.network +no_mem_vec=false profiler=system.ruby.profiler random_seed=1234 randomization=false stats_filename=ruby.stats tracer=system.ruby.tracer -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none +[system.ruby.cpu_ruby_ports] +type=RubySequencer +children=dcache +access_phys_mem=true +dcache=system.ruby.cpu_ruby_ports.dcache +deadlock_threshold=500000 +icache=system.ruby.cpu_ruby_ports.dcache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + +[system.ruby.cpu_ruby_ports.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 [system.ruby.network] type=SimpleNetwork children=topology -adaptive_routing=true +adaptive_routing=false buffer_size=0 control_msg_size=8 endpoint_bandwidth=10000 @@ -111,6 +187,7 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology children=ext_links0 ext_links1 int_links0 int_links1 +description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 num_int_nodes=3 @@ -118,93 +195,20 @@ print_config=false [system.ruby.network.topology.ext_links0] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node +ext_node=system.l1_cntrl0 int_node=0 latency=1 weight=1 -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=sequencer -buffer_size=0 -cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -cache_response_latency=12 -issue_latency=2 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links1] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node +ext_node=system.dir_cntrl0 int_node=1 latency=1 weight=1 -[system.ruby.network.topology.ext_links1.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links1.ext_node.directory -directory_latency=12 -memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.directory] -type=RubyDirectoryMemory -size=134217728 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats index d9b6ae533..a6219b7a9 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats @@ -18,9 +18,9 @@ topology: virtual_net_0: active, ordered virtual_net_1: active, ordered virtual_net_2: active, ordered -virtual_net_3: inactive +virtual_net_3: active, ordered virtual_net_4: active, ordered -virtual_net_5: active, ordered +virtual_net_5: inactive virtual_net_6: inactive virtual_net_7: inactive virtual_net_8: inactive @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jan/28/2010 10:15:29 +Real time: Feb/07/2011 01:47:49 Profiler Stats -------------- @@ -43,31 +43,20 @@ Elapsed_time_in_minutes: 0.0166667 Elapsed_time_in_hours: 0.000277778 Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.5 -Virtual_time_in_minutes: 0.00833333 -Virtual_time_in_hours: 0.000138889 -Virtual_time_in_days: 5.78704e-06 +Virtual_time_in_seconds: 0.35 +Virtual_time_in_minutes: 0.00583333 +Virtual_time_in_hours: 9.72222e-05 +Virtual_time_in_days: 4.05093e-06 Ruby_current_time: 342698 Ruby_start_time: 0 Ruby_cycles: 342698 -mbytes_resident: 34.2148 -mbytes_total: 34.2227 -resident_ratio: 1 - -Total_misses: 0 -total_misses: 0 [ 0 ] -user_misses: 0 [ 0 ] -supervisor_misses: 0 [ 0 ] - -ruby_cycles_executed: 342699 [ 342699 ] - -transactions_started: 0 [ 0 ] -transactions_ended: 0 [ 0 ] -cycles_per_transaction: 0 [ 0 ] -misses_per_transaction: 0 [ 0 ] +mbytes_resident: 37.7383 +mbytes_total: 227.77 +resident_ratio: 0.165703 +ruby_cycles_executed: [ 342699 ] Busy Controller Counts: L1Cache-0:0 @@ -81,9 +70,27 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- miss_latency: [binsize: 2 max: 377 count: 8464 average: 39.4889 | standard deviation: 72.9776 | 0 6734 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 6 1 3 6 0 334 211 182 529 243 4 4 0 5 2 15 9 4 14 10 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 30 18 15 24 37 2 3 0 0 2 2 1 1 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 ] -miss_latency_1: [binsize: 2 max: 285 count: 6414 average: 23.2806 | standard deviation: 57.2661 | 0 5684 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 2 max: 375 count: 1185 average: 110.608 | standard deviation: 87.0282 | 0 458 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 0 1 2 0 147 90 74 255 81 2 1 0 3 0 12 3 1 9 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 4 2 11 4 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 2 max: 377 count: 865 average: 62.2439 | standard deviation: 89.6671 | 0 592 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 30 31 54 70 0 0 0 1 0 1 0 2 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 8 3 21 0 0 0 0 0 0 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 2 max: 285 count: 6414 average: 23.2806 | standard deviation: 57.2661 | 0 5684 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 2 max: 375 count: 1185 average: 110.608 | standard deviation: 87.0282 | 0 458 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 0 1 2 0 147 90 74 255 81 2 1 0 3 0 12 3 1 9 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 4 2 11 4 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 377 count: 865 average: 62.2439 | standard deviation: 89.6671 | 0 592 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 30 31 54 70 0 0 0 1 0 1 0 2 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 8 3 21 0 0 0 0 0 0 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ] +miss_latency_L1Cache: [binsize: 1 max: 3 count: 6734 average: 3 | standard deviation: 0 | 0 0 0 6734 ] +miss_latency_Directory: [binsize: 2 max: 377 count: 1730 average: 181.521 | standard deviation: 26.4115 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 6 1 3 6 0 334 211 182 529 243 4 4 0 5 2 15 9 4 14 10 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 30 18 15 24 37 2 3 0 0 2 2 1 1 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average: 159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +imcomplete_dir_Times: 1729 +miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 5684 average: 3 | standard deviation: 0 | 0 0 0 5684 ] +miss_latency_IFETCH_Directory: [binsize: 2 max: 285 count: 730 average: 181.192 | standard deviation: 25.9199 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 458 average: 3 | standard deviation: 0 | 0 0 0 458 ] +miss_latency_LD_Directory: [binsize: 2 max: 375 count: 727 average: 178.4 | standard deviation: 21.0913 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 0 1 2 0 147 90 74 255 81 2 1 0 3 0 12 3 1 9 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 4 2 11 4 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 592 average: 3 | standard deviation: 0 | 0 0 0 592 ] +miss_latency_ST_Directory: [binsize: 2 max: 377 count: 273 average: 190.714 | standard deviation: 36.5384 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 30 31 54 70 0 0 0 1 0 1 0 2 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 8 3 21 0 0 0 0 0 0 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -115,25 +122,31 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 7357 -page_faults: 2195 +page_reclaims: 10742 +page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 0 +block_outputs: 64 Network Stats ------------- +total_msg_count_Control: 5190 41520 +total_msg_count_Data: 5178 372816 +total_msg_count_Response_Data: 5190 373680 +total_msg_count_Writeback_Control: 5178 41424 +total_msgs: 20736 total_bytes: 829440 + switch_0_inlinks: 2 switch_0_outlinks: 2 links_utilized_percent_switch_0: 0.157486 links_utilized_percent_switch_0_link_0: 0.0630876 bw: 640000 base_latency: 1 links_utilized_percent_switch_0_link_1: 0.251884 bw: 160000 base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 1730 124560 [ 0 1730 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 1726 13808 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Control: 1730 13840 [ 1730 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Data: 1726 124272 [ 1726 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 1730 124560 [ 0 0 0 0 1730 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 1726 13808 [ 0 0 0 1726 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 1730 13840 [ 0 0 1730 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Data: 1726 124272 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 @@ -141,10 +154,10 @@ links_utilized_percent_switch_1: 0.157661 links_utilized_percent_switch_1_link_0: 0.0629709 bw: 640000 base_latency: 1 links_utilized_percent_switch_1_link_1: 0.25235 bw: 160000 base_latency: 1 - outgoing_messages_switch_1_link_0_Control: 1730 13840 [ 1730 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Data: 1726 124272 [ 1726 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 1730 124560 [ 0 1730 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 1726 13808 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Control: 1730 13840 [ 0 0 1730 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Data: 1726 124272 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 1730 124560 [ 0 0 0 0 1730 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 1726 13808 [ 0 0 0 1726 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 @@ -152,66 +165,64 @@ links_utilized_percent_switch_2: 0.252117 links_utilized_percent_switch_2_link_0: 0.25235 bw: 160000 base_latency: 1 links_utilized_percent_switch_2_link_1: 0.251884 bw: 160000 base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 1730 124560 [ 0 1730 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 1726 13808 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Control: 1730 13840 [ 1730 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Data: 1726 124272 [ 1726 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 1730 124560 [ 0 0 0 0 1730 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 1726 13808 [ 0 0 0 1726 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Control: 1730 13840 [ 0 0 1730 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Data: 1726 124272 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 1730 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 1730 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf +Cache Stats: system.ruby.cpu_ruby_ports.dcache + system.ruby.cpu_ruby_ports.dcache_total_misses: 1730 + system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 1730 + system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0 + system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0 + system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD: 42.0231% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST: 15.7803% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH: 42.1965% + system.ruby.cpu_ruby_ports.dcache_request_type_LD: 42.0231% + system.ruby.cpu_ruby_ports.dcache_request_type_ST: 15.7803% + system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH: 42.1965% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 1730 100% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 8 count: 1730 average: 6.00925 | standard deviation: 2.00058 | 0 0 0 0 861 0 0 0 869 ] + system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 1730 100% - --- L1Cache 0 --- + --- L1Cache --- - Event Counts - -Load 1185 -Ifetch 6414 -Store 865 -Data 1730 -Fwd_GETX 0 -Inv 0 -Replacement 1726 -Writeback_Ack 1726 -Writeback_Nack 0 +Load [1185 ] 1185 +Ifetch [6414 ] 6414 +Store [865 ] 865 +Data [1730 ] 1730 +Fwd_GETX [0 ] 0 +Inv [0 ] 0 +Replacement [1726 ] 1726 +Writeback_Ack [1726 ] 1726 +Writeback_Nack [0 ] 0 - Transitions - -I Load 727 -I Ifetch 730 -I Store 273 -I Inv 0 <-- -I Replacement 0 <-- +I Load [727 ] 727 +I Ifetch [730 ] 730 +I Store [273 ] 273 +I Inv [0 ] 0 +I Replacement [0 ] 0 -II Writeback_Nack 0 <-- +II Writeback_Nack [0 ] 0 -M Load 458 -M Ifetch 5684 -M Store 592 -M Fwd_GETX 0 <-- -M Inv 0 <-- -M Replacement 1726 +M Load [458 ] 458 +M Ifetch [5684 ] 5684 +M Store [592 ] 592 +M Fwd_GETX [0 ] 0 +M Inv [0 ] 0 +M Replacement [1726 ] 1726 -MI Fwd_GETX 0 <-- -MI Inv 0 <-- -MI Writeback_Ack 1726 -MI Writeback_Nack 0 <-- +MI Fwd_GETX [0 ] 0 +MI Inv [0 ] 0 +MI Writeback_Ack [1726 ] 1726 +MI Writeback_Nack [0 ] 0 -MII Fwd_GETX 0 <-- +MII Fwd_GETX [0 ] 0 -IS Data 1457 +IS Data [1457 ] 1457 -IM Data 273 +IM Data [273 ] 273 -Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer: +Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 3456 memory_reads: 1730 memory_writes: 1726 @@ -231,70 +242,69 @@ Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer: memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 162 36 92 110 106 362 98 36 32 34 83 92 110 104 84 86 83 53 50 58 64 124 212 72 66 50 122 190 220 325 42 98 - --- Directory 0 --- + --- Directory --- - Event Counts - -GETX 1730 -GETS 0 -PUTX 1726 -PUTX_NotOwner 0 -DMA_READ 0 -DMA_WRITE 0 -Memory_Data 1730 -Memory_Ack 1726 +GETX [1730 ] 1730 +GETS [0 ] 0 +PUTX [1726 ] 1726 +PUTX_NotOwner [0 ] 0 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +Memory_Data [1730 ] 1730 +Memory_Ack [1726 ] 1726 - Transitions - -I GETX 1730 -I PUTX_NotOwner 0 <-- -I DMA_READ 0 <-- -I DMA_WRITE 0 <-- - -M GETX 0 <-- -M PUTX 1726 -M PUTX_NotOwner 0 <-- -M DMA_READ 0 <-- -M DMA_WRITE 0 <-- - -M_DRD GETX 0 <-- -M_DRD PUTX 0 <-- - -M_DWR GETX 0 <-- -M_DWR PUTX 0 <-- - -M_DWRI GETX 0 <-- -M_DWRI Memory_Ack 0 <-- - -M_DRDI GETX 0 <-- -M_DRDI Memory_Ack 0 <-- - -IM GETX 0 <-- -IM GETS 0 <-- -IM PUTX 0 <-- -IM PUTX_NotOwner 0 <-- -IM DMA_READ 0 <-- -IM DMA_WRITE 0 <-- -IM Memory_Data 1730 - -MI GETX 0 <-- -MI GETS 0 <-- -MI PUTX 0 <-- -MI PUTX_NotOwner 0 <-- -MI DMA_READ 0 <-- -MI DMA_WRITE 0 <-- -MI Memory_Ack 1726 - -ID GETX 0 <-- -ID GETS 0 <-- -ID PUTX 0 <-- -ID PUTX_NotOwner 0 <-- -ID DMA_READ 0 <-- -ID DMA_WRITE 0 <-- -ID Memory_Data 0 <-- - -ID_W GETX 0 <-- -ID_W GETS 0 <-- -ID_W PUTX 0 <-- -ID_W PUTX_NotOwner 0 <-- -ID_W DMA_READ 0 <-- -ID_W DMA_WRITE 0 <-- -ID_W Memory_Ack 0 <-- - +I GETX [1730 ] 1730 +I PUTX_NotOwner [0 ] 0 +I DMA_READ [0 ] 0 +I DMA_WRITE [0 ] 0 + +M GETX [0 ] 0 +M PUTX [1726 ] 1726 +M PUTX_NotOwner [0 ] 0 +M DMA_READ [0 ] 0 +M DMA_WRITE [0 ] 0 + +M_DRD GETX [0 ] 0 +M_DRD PUTX [0 ] 0 + +M_DWR GETX [0 ] 0 +M_DWR PUTX [0 ] 0 + +M_DWRI GETX [0 ] 0 +M_DWRI Memory_Ack [0 ] 0 + +M_DRDI GETX [0 ] 0 +M_DRDI Memory_Ack [0 ] 0 + +IM GETX [0 ] 0 +IM GETS [0 ] 0 +IM PUTX [0 ] 0 +IM PUTX_NotOwner [0 ] 0 +IM DMA_READ [0 ] 0 +IM DMA_WRITE [0 ] 0 +IM Memory_Data [1730 ] 1730 + +MI GETX [0 ] 0 +MI GETS [0 ] 0 +MI PUTX [0 ] 0 +MI PUTX_NotOwner [0 ] 0 +MI DMA_READ [0 ] 0 +MI DMA_WRITE [0 ] 0 +MI Memory_Ack [1726 ] 1726 + +ID GETX [0 ] 0 +ID GETS [0 ] 0 +ID PUTX [0 ] 0 +ID PUTX_NotOwner [0 ] 0 +ID DMA_READ [0 ] 0 +ID DMA_WRITE [0 ] 0 +ID Memory_Data [0 ] 0 + +ID_W GETX [0 ] 0 +ID_W GETS [0 ] 0 +ID_W PUTX [0 ] 0 +ID_W PUTX_NotOwner [0 ] 0 +ID_W DMA_READ [0 ] 0 +ID_W DMA_WRITE [0 ] 0 +ID_W Memory_Ack
\ No newline at end of file diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout index b8009485a..6867d8c8b 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 27 2010 22:23:20 -M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate -M5 started Jan 28 2010 10:15:28 -M5 executing on svvint07 +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:48 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt index d59a173b9..a6f61bb79 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 19405 # Simulator instruction rate (inst/s) -host_mem_usage 215700 # Number of bytes of host memory used -host_seconds 0.33 # Real time elapsed on the host -host_tick_rate 1038428 # Simulator tick rate (ticks/s) +host_inst_rate 16267 # Simulator instruction rate (inst/s) +host_mem_usage 233240 # Number of bytes of host memory used +host_seconds 0.39 # Real time elapsed on the host +host_tick_rate 870027 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000343 # Number of seconds simulated @@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 342698 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 342698 # Number of busy cycles +system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses +system.cpu.num_fp_insts 10 # number of float instructions +system.cpu.num_fp_register_reads 8 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2 # number of times the floating registers were written +system.cpu.num_func_calls 251 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 6404 # Number of instructions executed -system.cpu.num_refs 2060 # Number of memory references +system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses +system.cpu.num_int_insts 6331 # number of integer instructions +system.cpu.num_int_register_reads 8304 # number of times the integer registers were read +system.cpu.num_int_register_writes 4581 # number of times the integer registers were written +system.cpu.num_load_insts 1192 # Number of load instructions +system.cpu.num_mem_refs 2060 # number of memory refs +system.cpu.num_store_insts 868 # Number of store instructions system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index 17f796bc5..8ac220e1e 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout index 2df06d2e2..6e929844e 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 11:51:59 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 11:59:22 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:37 +M5 executing on burrito +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt index 0a6e1d861..710a7cdd2 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 332796 # Simulator instruction rate (inst/s) -host_mem_usage 204128 # Number of bytes of host memory used +host_inst_rate 267933 # Simulator instruction rate (inst/s) +host_mem_usage 222956 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 1691799077 # Simulator tick rate (ticks/s) +host_tick_rate 1366456557 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000033 # Number of seconds simulated @@ -227,8 +227,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 66014 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 66014 # Number of busy cycles +system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses +system.cpu.num_fp_insts 10 # number of float instructions +system.cpu.num_fp_register_reads 8 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2 # number of times the floating registers were written +system.cpu.num_func_calls 251 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 6404 # Number of instructions executed -system.cpu.num_refs 2060 # Number of memory references +system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses +system.cpu.num_int_insts 6331 # number of integer instructions +system.cpu.num_int_register_reads 8304 # number of times the integer registers were read +system.cpu.num_int_register_writes 4581 # number of times the integer registers were written +system.cpu.num_load_insts 1192 # Number of load instructions +system.cpu.num_mem_refs 2060 # number of memory refs +system.cpu.num_store_insts 868 # Number of store instructions system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index 2ddfc3365..e99d2d594 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout index fe2af5e09..8339eb49f 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 17 2011 16:24:53 -M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase -M5 started Jan 17 2011 16:48:46 -M5 executing on zizzer +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:49 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 2363f1511..c17e16760 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 61982 # Simulator instruction rate (inst/s) -host_mem_usage 202420 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 188319059 # Simulator tick rate (ticks/s) +host_inst_rate 33498 # Simulator instruction rate (inst/s) +host_mem_usage 222808 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 102057061 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated sim_seconds 0.000007 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 6328 # Number of insts commited each cycle system.cpu.commit.COM:count 2576 # Number of instructions committed +system.cpu.commit.COM:fp_insts 6 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 71 # Number of function calls committed. +system.cpu.commit.COM:int_insts 2367 # Number of committed integer instructions. system.cpu.commit.COM:loads 415 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 709 # Number of memory references committed @@ -169,6 +172,7 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 6701 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.icache.ReadReq_accesses 782 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 36074.786325 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35303.867403 # average ReadReq mshr miss latency @@ -268,6 +272,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 141 # system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 109 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 55 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 4283 # number of integer regfile reads +system.cpu.int_regfile_writes 2601 # number of integer regfile writes system.cpu.ipc 0.163482 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.163482 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -359,6 +365,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 6701 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 0.248682 # Inst issue rate +system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 3659 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 14008 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 3396 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 5997 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 4276 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 3631 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ @@ -449,7 +463,11 @@ system.cpu.memDep0.conflictingLoads 16 # Nu system.cpu.memDep0.conflictingStores 16 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 793 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 435 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1 # number of misc regfile reads +system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.numCycles 14601 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 63 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 3 # Number of times rename has blocked due to IQ full @@ -462,10 +480,14 @@ system.cpu.rename.RENAME:RunCycles 901 # Nu system.cpu.rename.RENAME:SquashCycles 373 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 15 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 1713 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 12 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 5502 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 146 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 78 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 10620 # The number of ROB reads +system.cpu.rob.rob_writes 9524 # The number of ROB writes system.cpu.timesIdled 152 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini index ac9cc91a1..43e841230 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -57,7 +66,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/test-progs/hello/bin/alpha/tru64/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout index 532375cf9..800e2e284 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 2 2010 21:30:55 -M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip -M5 started Nov 2 2010 21:32:40 -M5 executing on aus-bc2-b15 +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:37 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt index d0028e484..835697644 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 759729 # Simulator instruction rate (inst/s) -host_mem_usage 228516 # Number of bytes of host memory used -host_seconds 0.00 # Real time elapsed on the host -host_tick_rate 362937063 # Simulator tick rate (ticks/s) +host_inst_rate 290762 # Simulator instruction rate (inst/s) +host_mem_usage 214352 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 142079814 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated @@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 2596 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 2596 # Number of busy cycles +system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses +system.cpu.num_fp_insts 6 # number of float instructions +system.cpu.num_fp_register_reads 6 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 140 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 2577 # Number of instructions executed -system.cpu.num_refs 717 # Number of memory references +system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses +system.cpu.num_int_insts 2375 # number of integer instructions +system.cpu.num_int_register_reads 2998 # number of times the integer registers were read +system.cpu.num_int_register_writes 1768 # number of times the integer registers were written +system.cpu.num_load_insts 419 # Number of load instructions +system.cpu.num_mem_refs 717 # number of memory refs +system.cpu.num_store_insts 298 # Number of store instructions system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini index 4c150fde0..71495ec84 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 [system] type=System -children=cpu physmem ruby +children=cpu dir_cntrl0 l1_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -32,8 +41,8 @@ progress_interval=0 system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1] -icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] +dcache_port=system.ruby.cpu_ruby_ports.port[1] +icache_port=system.ruby.cpu_ruby_ports.port[0] [system.cpu.dtb] type=AlphaTLB @@ -54,7 +63,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/tru64/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -65,6 +74,59 @@ simpoint=0 system=system uid=100 +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +directory=system.dir_cntrl0.directory +directory_latency=12 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.l1_cntrl0] +type=L1Cache_Controller +buffer_size=0 +cacheMemory=system.ruby.cpu_ruby_ports.dcache +cache_response_latency=12 +issue_latency=2 +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.ruby.cpu_ruby_ports +transitions_per_cycle=32 +version=0 + [system.physmem] type=PhysicalMemory file= @@ -73,34 +135,48 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort +port=system.ruby.cpu_ruby_ports.physMemPort [system.ruby] type=RubySystem -children=debug network profiler tracer +children=cpu_ruby_ports network profiler tracer block_size_bytes=64 clock=1 -debug=system.ruby.debug mem_size=134217728 network=system.ruby.network +no_mem_vec=false profiler=system.ruby.profiler random_seed=1234 randomization=false stats_filename=ruby.stats tracer=system.ruby.tracer -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none +[system.ruby.cpu_ruby_ports] +type=RubySequencer +children=dcache +access_phys_mem=true +dcache=system.ruby.cpu_ruby_ports.dcache +deadlock_threshold=500000 +icache=system.ruby.cpu_ruby_ports.dcache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + +[system.ruby.cpu_ruby_ports.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 [system.ruby.network] type=SimpleNetwork children=topology -adaptive_routing=true +adaptive_routing=false buffer_size=0 control_msg_size=8 endpoint_bandwidth=10000 @@ -111,6 +187,7 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology children=ext_links0 ext_links1 int_links0 int_links1 +description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 num_int_nodes=3 @@ -118,93 +195,20 @@ print_config=false [system.ruby.network.topology.ext_links0] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node +ext_node=system.l1_cntrl0 int_node=0 latency=1 weight=1 -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=sequencer -buffer_size=0 -cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -cache_response_latency=12 -issue_latency=2 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links1] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node +ext_node=system.dir_cntrl0 int_node=1 latency=1 weight=1 -[system.ruby.network.topology.ext_links1.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links1.ext_node.directory -directory_latency=12 -memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.directory] -type=RubyDirectoryMemory -size=134217728 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats index edd5bdfcc..c43ead0e8 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats @@ -18,9 +18,9 @@ topology: virtual_net_0: active, ordered virtual_net_1: active, ordered virtual_net_2: active, ordered -virtual_net_3: inactive +virtual_net_3: active, ordered virtual_net_4: active, ordered -virtual_net_5: active, ordered +virtual_net_5: inactive virtual_net_6: inactive virtual_net_7: inactive virtual_net_8: inactive @@ -34,40 +34,29 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jan/28/2010 10:26:06 +Real time: Feb/07/2011 01:47:37 Profiler Stats -------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.25 -Virtual_time_in_minutes: 0.00416667 -Virtual_time_in_hours: 6.94444e-05 -Virtual_time_in_days: 2.89352e-06 +Virtual_time_in_seconds: 0.26 +Virtual_time_in_minutes: 0.00433333 +Virtual_time_in_hours: 7.22222e-05 +Virtual_time_in_days: 3.00926e-06 Ruby_current_time: 123378 Ruby_start_time: 0 Ruby_cycles: 123378 -mbytes_resident: 32.8828 -mbytes_total: 32.8906 -resident_ratio: 1 - -Total_misses: 0 -total_misses: 0 [ 0 ] -user_misses: 0 [ 0 ] -supervisor_misses: 0 [ 0 ] - -ruby_cycles_executed: 123379 [ 123379 ] - -transactions_started: 0 [ 0 ] -transactions_ended: 0 [ 0 ] -cycles_per_transaction: 0 [ 0 ] -misses_per_transaction: 0 [ 0 ] +mbytes_resident: 36.4062 +mbytes_total: 226.781 +resident_ratio: 0.160552 +ruby_cycles_executed: [ 123379 ] Busy Controller Counts: L1Cache-0:0 @@ -81,9 +70,27 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- miss_latency: [binsize: 2 max: 375 count: 3294 average: 36.4554 | standard deviation: 69.7725 | 0 2668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 0 0 3 1 1 4 2 101 88 63 177 126 0 1 1 8 0 2 1 1 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 4 5 13 2 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 ] -miss_latency_1: [binsize: 2 max: 375 count: 2585 average: 23.1702 | standard deviation: 56.4841 | 0 2288 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 2 2 31 53 29 71 82 0 1 0 5 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 3 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_2: [binsize: 2 max: 281 count: 415 average: 107.304 | standard deviation: 88.8453 | 0 170 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 2 0 56 24 27 75 32 0 0 1 3 0 1 0 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 4 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 2 max: 265 count: 294 average: 53.2585 | standard deviation: 80.456 | 0 210 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 14 11 7 31 12 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 2 max: 375 count: 2585 average: 23.1702 | standard deviation: 56.4841 | 0 2288 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 2 2 31 53 29 71 82 0 1 0 5 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 3 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_LD: [binsize: 2 max: 281 count: 415 average: 107.304 | standard deviation: 88.8453 | 0 170 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 2 0 56 24 27 75 32 0 0 1 3 0 1 0 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 4 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 265 count: 294 average: 53.2585 | standard deviation: 80.456 | 0 210 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 14 11 7 31 12 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache: [binsize: 1 max: 3 count: 2668 average: 3 | standard deviation: 0 | 0 0 0 2668 ] +miss_latency_Directory: [binsize: 2 max: 375 count: 626 average: 179.042 | standard deviation: 22.5462 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 0 0 3 1 1 4 2 101 88 63 177 126 0 1 1 8 0 2 1 1 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 4 5 13 2 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average: 159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +imcomplete_dir_Times: 625 +miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 2288 average: 3 | standard deviation: 0 | 0 0 0 2288 ] +miss_latency_IFETCH_Directory: [binsize: 2 max: 375 count: 297 average: 178.556 | standard deviation: 21.9279 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 2 2 31 53 29 71 82 0 1 0 5 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 3 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 170 average: 3 | standard deviation: 0 | 0 0 0 170 ] +miss_latency_LD_Directory: [binsize: 2 max: 281 count: 245 average: 179.678 | standard deviation: 23.5327 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 2 0 56 24 27 75 32 0 0 1 3 0 1 0 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 4 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 210 average: 3 | standard deviation: 0 | 0 0 0 210 ] +miss_latency_ST_Directory: [binsize: 2 max: 265 count: 84 average: 178.905 | standard deviation: 21.977 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 14 11 7 31 12 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -115,25 +122,31 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 7118 -page_faults: 2103 +page_reclaims: 10395 +page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 0 +block_outputs: 64 Network Stats ------------- +total_msg_count_Control: 1878 15024 +total_msg_count_Data: 1866 134352 +total_msg_count_Response_Data: 1878 135216 +total_msg_count_Writeback_Control: 1866 14928 +total_msgs: 7488 total_bytes: 299520 + switch_0_inlinks: 2 switch_0_outlinks: 2 links_utilized_percent_switch_0: 0.157808 links_utilized_percent_switch_0_link_0: 0.0633825 bw: 640000 base_latency: 1 links_utilized_percent_switch_0_link_1: 0.252233 bw: 160000 base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 626 45072 [ 0 626 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 622 4976 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Control: 626 5008 [ 626 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Data: 622 44784 [ 622 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 626 45072 [ 0 0 0 0 626 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 622 4976 [ 0 0 0 622 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 626 5008 [ 0 0 626 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Data: 622 44784 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 @@ -141,10 +154,10 @@ links_utilized_percent_switch_1: 0.158294 links_utilized_percent_switch_1_link_0: 0.0630582 bw: 640000 base_latency: 1 links_utilized_percent_switch_1_link_1: 0.25353 bw: 160000 base_latency: 1 - outgoing_messages_switch_1_link_0_Control: 626 5008 [ 626 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Data: 622 44784 [ 622 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 626 45072 [ 0 626 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 622 4976 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Control: 626 5008 [ 0 0 626 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Data: 622 44784 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 626 45072 [ 0 0 0 0 626 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 622 4976 [ 0 0 0 622 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 @@ -152,66 +165,64 @@ links_utilized_percent_switch_2: 0.252881 links_utilized_percent_switch_2_link_0: 0.25353 bw: 160000 base_latency: 1 links_utilized_percent_switch_2_link_1: 0.252233 bw: 160000 base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 626 45072 [ 0 626 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 622 4976 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Control: 626 5008 [ 626 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Data: 622 44784 [ 622 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 626 45072 [ 0 0 0 0 626 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 622 4976 [ 0 0 0 622 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Control: 626 5008 [ 0 0 626 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Data: 622 44784 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 626 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 626 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf +Cache Stats: system.ruby.cpu_ruby_ports.dcache + system.ruby.cpu_ruby_ports.dcache_total_misses: 626 + system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 626 + system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0 + system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0 + system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD: 39.1374% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST: 13.4185% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH: 47.4441% + system.ruby.cpu_ruby_ports.dcache_request_type_LD: 39.1374% + system.ruby.cpu_ruby_ports.dcache_request_type_ST: 13.4185% + system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH: 47.4441% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 626 100% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 8 count: 626 average: 5.71885 | standard deviation: 1.98192 | 0 0 0 0 357 0 0 0 269 ] + system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 626 100% - --- L1Cache 0 --- + --- L1Cache --- - Event Counts - -Load 415 -Ifetch 2585 -Store 294 -Data 626 -Fwd_GETX 0 -Inv 0 -Replacement 622 -Writeback_Ack 622 -Writeback_Nack 0 +Load [415 ] 415 +Ifetch [2585 ] 2585 +Store [294 ] 294 +Data [626 ] 626 +Fwd_GETX [0 ] 0 +Inv [0 ] 0 +Replacement [622 ] 622 +Writeback_Ack [622 ] 622 +Writeback_Nack [0 ] 0 - Transitions - -I Load 245 -I Ifetch 297 -I Store 84 -I Inv 0 <-- -I Replacement 0 <-- +I Load [245 ] 245 +I Ifetch [297 ] 297 +I Store [84 ] 84 +I Inv [0 ] 0 +I Replacement [0 ] 0 -II Writeback_Nack 0 <-- +II Writeback_Nack [0 ] 0 -M Load 170 -M Ifetch 2288 -M Store 210 -M Fwd_GETX 0 <-- -M Inv 0 <-- -M Replacement 622 +M Load [170 ] 170 +M Ifetch [2288 ] 2288 +M Store [210 ] 210 +M Fwd_GETX [0 ] 0 +M Inv [0 ] 0 +M Replacement [622 ] 622 -MI Fwd_GETX 0 <-- -MI Inv 0 <-- -MI Writeback_Ack 622 -MI Writeback_Nack 0 <-- +MI Fwd_GETX [0 ] 0 +MI Inv [0 ] 0 +MI Writeback_Ack [622 ] 622 +MI Writeback_Nack [0 ] 0 -MII Fwd_GETX 0 <-- +MII Fwd_GETX [0 ] 0 -IS Data 542 +IS Data [542 ] 542 -IM Data 84 +IM Data [84 ] 84 -Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer: +Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 1248 memory_reads: 626 memory_writes: 622 @@ -231,70 +242,69 @@ Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer: memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 55 40 0 100 42 42 88 45 14 10 14 10 46 82 38 6 22 14 14 48 20 52 26 92 34 10 12 24 28 44 38 138 - --- Directory 0 --- + --- Directory --- - Event Counts - -GETX 626 -GETS 0 -PUTX 622 -PUTX_NotOwner 0 -DMA_READ 0 -DMA_WRITE 0 -Memory_Data 626 -Memory_Ack 622 +GETX [626 ] 626 +GETS [0 ] 0 +PUTX [622 ] 622 +PUTX_NotOwner [0 ] 0 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +Memory_Data [626 ] 626 +Memory_Ack [622 ] 622 - Transitions - -I GETX 626 -I PUTX_NotOwner 0 <-- -I DMA_READ 0 <-- -I DMA_WRITE 0 <-- - -M GETX 0 <-- -M PUTX 622 -M PUTX_NotOwner 0 <-- -M DMA_READ 0 <-- -M DMA_WRITE 0 <-- - -M_DRD GETX 0 <-- -M_DRD PUTX 0 <-- - -M_DWR GETX 0 <-- -M_DWR PUTX 0 <-- - -M_DWRI GETX 0 <-- -M_DWRI Memory_Ack 0 <-- - -M_DRDI GETX 0 <-- -M_DRDI Memory_Ack 0 <-- - -IM GETX 0 <-- -IM GETS 0 <-- -IM PUTX 0 <-- -IM PUTX_NotOwner 0 <-- -IM DMA_READ 0 <-- -IM DMA_WRITE 0 <-- -IM Memory_Data 626 - -MI GETX 0 <-- -MI GETS 0 <-- -MI PUTX 0 <-- -MI PUTX_NotOwner 0 <-- -MI DMA_READ 0 <-- -MI DMA_WRITE 0 <-- -MI Memory_Ack 622 - -ID GETX 0 <-- -ID GETS 0 <-- -ID PUTX 0 <-- -ID PUTX_NotOwner 0 <-- -ID DMA_READ 0 <-- -ID DMA_WRITE 0 <-- -ID Memory_Data 0 <-- - -ID_W GETX 0 <-- -ID_W GETS 0 <-- -ID_W PUTX 0 <-- -ID_W PUTX_NotOwner 0 <-- -ID_W DMA_READ 0 <-- -ID_W DMA_WRITE 0 <-- -ID_W Memory_Ack 0 <-- - +I GETX [626 ] 626 +I PUTX_NotOwner [0 ] 0 +I DMA_READ [0 ] 0 +I DMA_WRITE [0 ] 0 + +M GETX [0 ] 0 +M PUTX [622 ] 622 +M PUTX_NotOwner [0 ] 0 +M DMA_READ [0 ] 0 +M DMA_WRITE [0 ] 0 + +M_DRD GETX [0 ] 0 +M_DRD PUTX [0 ] 0 + +M_DWR GETX [0 ] 0 +M_DWR PUTX [0 ] 0 + +M_DWRI GETX [0 ] 0 +M_DWRI Memory_Ack [0 ] 0 + +M_DRDI GETX [0 ] 0 +M_DRDI Memory_Ack [0 ] 0 + +IM GETX [0 ] 0 +IM GETS [0 ] 0 +IM PUTX [0 ] 0 +IM PUTX_NotOwner [0 ] 0 +IM DMA_READ [0 ] 0 +IM DMA_WRITE [0 ] 0 +IM Memory_Data [626 ] 626 + +MI GETX [0 ] 0 +MI GETS [0 ] 0 +MI PUTX [0 ] 0 +MI PUTX_NotOwner [0 ] 0 +MI DMA_READ [0 ] 0 +MI DMA_WRITE [0 ] 0 +MI Memory_Ack [622 ] 622 + +ID GETX [0 ] 0 +ID GETS [0 ] 0 +ID PUTX [0 ] 0 +ID PUTX_NotOwner [0 ] 0 +ID DMA_READ [0 ] 0 +ID DMA_WRITE [0 ] 0 +ID Memory_Data [0 ] 0 + +ID_W GETX [0 ] 0 +ID_W GETS [0 ] 0 +ID_W PUTX [0 ] 0 +ID_W PUTX_NotOwner [0 ] 0 +ID_W DMA_READ [0 ] 0 +ID_W DMA_WRITE [0 ] 0 +ID_W Memory_Ack
\ No newline at end of file diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout index 994f7ec2d..5f04faac1 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 27 2010 22:23:20 -M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate -M5 started Jan 28 2010 10:26:06 -M5 executing on svvint07 +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:36 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt index dd60f4239..8d615ceb9 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 51538 # Simulator instruction rate (inst/s) -host_mem_usage 214632 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 2467461 # Simulator tick rate (ticks/s) +host_inst_rate 17883 # Simulator instruction rate (inst/s) +host_mem_usage 232228 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host +host_tick_rate 854675 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000123 # Number of seconds simulated @@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 123378 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 123378 # Number of busy cycles +system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses +system.cpu.num_fp_insts 6 # number of float instructions +system.cpu.num_fp_register_reads 6 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 140 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 2577 # Number of instructions executed -system.cpu.num_refs 717 # Number of memory references +system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses +system.cpu.num_int_insts 2375 # number of integer instructions +system.cpu.num_int_register_reads 2998 # number of times the integer registers were read +system.cpu.num_int_register_writes 1768 # number of times the integer registers were written +system.cpu.num_load_insts 419 # Number of load instructions +system.cpu.num_mem_refs 717 # number of memory refs +system.cpu.num_store_insts 298 # Number of store instructions system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index c142fa659..6019fe73e 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout index 6dd6e994b..37ac69d98 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 11:51:59 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 11:52:05 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:36 +M5 executing on burrito +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt index f08ca087e..aa9ef9160 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 97740 # Simulator instruction rate (inst/s) -host_mem_usage 203308 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 629585132 # Simulator tick rate (ticks/s) +host_inst_rate 236465 # Simulator instruction rate (inst/s) +host_mem_usage 222144 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 1500776387 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000017 # Number of seconds simulated @@ -226,8 +226,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 33538 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 33538 # Number of busy cycles +system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses +system.cpu.num_fp_insts 6 # number of float instructions +system.cpu.num_fp_register_reads 6 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 140 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 2577 # Number of instructions executed -system.cpu.num_refs 717 # Number of memory references +system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses +system.cpu.num_int_insts 2375 # number of integer instructions +system.cpu.num_int_register_reads 2998 # number of times the integer registers were read +system.cpu.num_int_register_writes 1768 # number of times the integer registers were written +system.cpu.num_load_insts 419 # Number of load instructions +system.cpu.num_mem_refs 717 # number of memory refs +system.cpu.num_store_insts 298 # Number of store instructions system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini index 9981924d0..b3ae554b5 100644 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU @@ -484,7 +493,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/test-progs/hello/bin/arm/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout index 898cae0a1..8fbed30cd 100755 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 11 2011 18:16:01 -M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip -M5 started Jan 12 2011 04:32:17 -M5 executing on u200439-lin.austin.arm.com +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:58:16 +M5 executing on burrito command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt index dbec33d6c..d630e1a83 100644 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 59213 # Simulator instruction rate (inst/s) -host_mem_usage 247916 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host -host_tick_rate 108401013 # Simulator tick rate (ticks/s) +host_inst_rate 29952 # Simulator instruction rate (inst/s) +host_mem_usage 234448 # Number of bytes of host memory used +host_seconds 0.19 # Real time elapsed on the host +host_tick_rate 54904580 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5620 # Number of instructions simulated sim_seconds 0.000010 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 10656 # Number of insts commited each cycle system.cpu.commit.COM:count 5620 # Number of instructions committed +system.cpu.commit.COM:fp_insts 16 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 0 # Number of function calls committed. +system.cpu.commit.COM:int_insts 4889 # Number of committed integer instructions. system.cpu.commit.COM:loads 1207 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 2145 # Number of memory references committed @@ -171,6 +174,7 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 11818 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.icache.ReadReq_accesses 1675 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 34635.549872 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 33596.573209 # average ReadReq mshr miss latency @@ -270,6 +274,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 708 # system.cpu.iew.memOrderViolationEvents 34 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 609 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 33 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 19236 # number of integer regfile reads +system.cpu.int_regfile_writes 5710 # number of integer regfile writes system.cpu.ipc 0.272340 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.272340 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -361,6 +367,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 11818 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 0.440202 # Inst issue rate +system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 54 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 58 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 9243 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 30172 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 7972 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 17831 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 11904 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 9084 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 2 # Number of non-speculative instructions added to the IQ @@ -458,7 +472,11 @@ system.cpu.memDep0.conflictingLoads 12 # Nu system.cpu.memDep0.conflictingStores 11 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 2545 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1646 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 15396 # number of misc regfile reads +system.cpu.misc_regfile_writes 3 # number of misc regfile writes system.cpu.numCycles 20636 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 346 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4006 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 46 # Number of times rename has blocked due to IQ full @@ -471,10 +489,14 @@ system.cpu.rename.RENAME:RunCycles 2314 # Nu system.cpu.rename.RENAME:SquashCycles 1162 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 187 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 6085 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 744 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 36764 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 271 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 4 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 537 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 1 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 22070 # The number of ROB reads +system.cpu.rob.rob_writes 24470 # The number of ROB writes system.cpu.timesIdled 180 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 13 # Number of system calls diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini index 0aafa817f..327106c53 100644 --- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -57,7 +66,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/test-progs/hello/bin/arm/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout index 7deff62bb..301661eda 100755 --- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 11 2010 18:37:23 -M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip -M5 started Oct 11 2010 18:37:39 -M5 executing on aus-bc3-b4 -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-atomic +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:25 +M5 executing on burrito +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt index 415af9a3d..25bd032b8 100644 --- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 402550 # Simulator instruction rate (inst/s) -host_mem_usage 249936 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 197047093 # Simulator tick rate (ticks/s) +host_inst_rate 100802 # Simulator instruction rate (inst/s) +host_mem_usage 225720 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 50271986 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5620 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated @@ -53,8 +53,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 5633 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 5633 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses +system.cpu.num_fp_insts 16 # number of float instructions +system.cpu.num_fp_register_reads 16 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 5620 # Number of instructions executed -system.cpu.num_refs 2145 # Number of memory references +system.cpu.num_int_alu_accesses 4889 # Number of integer alu accesses +system.cpu.num_int_insts 4889 # number of integer instructions +system.cpu.num_int_register_reads 14091 # number of times the integer registers were read +system.cpu.num_int_register_writes 3689 # number of times the integer registers were written +system.cpu.num_load_insts 1207 # Number of load instructions +system.cpu.num_mem_refs 2145 # number of memory refs +system.cpu.num_store_insts 938 # Number of store instructions system.cpu.workload.PROG:num_syscalls 13 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini index d4111deef..d0bdfed8e 100644 --- a/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -157,7 +166,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/test-progs/hello/bin/arm/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/00.hello/ref/arm/linux/simple-timing/simout index a1f858063..de21768b5 100755 --- a/tests/quick/00.hello/ref/arm/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/arm/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 7 2010 18:51:32 -M5 revision 331c8c76d885 7806 default qtip tip ext/mismatched_new_delete.patch -M5 started Dec 7 2010 18:51:46 -M5 executing on u200439-lin.austin.arm.com +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:58:13 +M5 executing on burrito command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt index 3c0d4e2a6..438991f53 100644 --- a/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 315416 # Simulator instruction rate (inst/s) -host_mem_usage 248988 # Number of bytes of host memory used +host_inst_rate 265936 # Simulator instruction rate (inst/s) +host_mem_usage 233432 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 1472008046 # Simulator tick rate (ticks/s) +host_tick_rate 1242220035 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5563 # Number of instructions simulated sim_seconds 0.000026 # Number of seconds simulated @@ -237,8 +237,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 52692 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 52692 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses +system.cpu.num_fp_insts 16 # number of float instructions +system.cpu.num_fp_register_reads 16 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 5563 # Number of instructions executed -system.cpu.num_refs 2145 # Number of memory references +system.cpu.num_int_alu_accesses 4889 # Number of integer alu accesses +system.cpu.num_int_insts 4889 # number of integer instructions +system.cpu.num_int_register_reads 15212 # number of times the integer registers were read +system.cpu.num_int_register_writes 3689 # number of times the integer registers were written +system.cpu.num_load_insts 1207 # Number of load instructions +system.cpu.num_mem_refs 2145 # number of memory refs +system.cpu.num_store_insts 938 # Number of store instructions system.cpu.workload.PROG:num_syscalls 13 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini index d479ef8bf..5ba5eb09f 100644 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=InOrderCPU @@ -246,7 +255,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/mips/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout index dc388ddae..2ad70ea48 100755 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 24 2011 18:37:16 -M5 revision 09e8ac96522d+ 7823+ default regression_updates qtip tip -M5 started Jan 24 2011 18:37:18 -M5 executing on zooks +M5 compiled Feb 7 2011 01:55:51 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:02 +M5 executing on burrito command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt index 170c01854..1e86aa862 100644 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 32637 # Simulator instruction rate (inst/s) -host_mem_usage 156860 # Number of bytes of host memory used +host_inst_rate 32668 # Simulator instruction rate (inst/s) +host_mem_usage 224608 # Number of bytes of host memory used host_seconds 0.18 # Real time elapsed on the host -host_tick_rate 120410651 # Simulator tick rate (ticks/s) +host_tick_rate 120542676 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5827 # Number of instructions simulated sim_seconds 0.000022 # Number of seconds simulated @@ -253,6 +253,8 @@ system.cpu.l2cache.total_refs 2 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.numCycles 43069 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.runCycles 6002 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini index a9c72ed3e..a58be5b4d 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout index 6b2281542..5ff276ac0 100755 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 17 2011 21:17:36 -M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase -M5 started Jan 17 2011 21:17:39 -M5 executing on zizzer +M5 compiled Feb 7 2011 01:55:51 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:01 +M5 executing on burrito command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt index a5f35787b..7a8012ce7 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 35741 # Simulator instruction rate (inst/s) -host_mem_usage 204488 # Number of bytes of host memory used +host_inst_rate 37179 # Simulator instruction rate (inst/s) +host_mem_usage 224748 # Number of bytes of host memory used host_seconds 0.14 # Real time elapsed on the host -host_tick_rate 88262097 # Simulator tick rate (ticks/s) +host_tick_rate 91756799 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5169 # Number of instructions simulated sim_seconds 0.000013 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 12273 # Number of insts commited each cycle system.cpu.commit.COM:count 5826 # Number of instructions committed +system.cpu.commit.COM:fp_insts 2 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 87 # Number of function calls committed. +system.cpu.commit.COM:int_insts 5124 # Number of committed integer instructions. system.cpu.commit.COM:loads 1164 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 2089 # Number of memory references committed @@ -162,6 +165,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 12922 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 3 # number of floating regfile reads +system.cpu.fp_regfile_writes 1 # number of floating regfile writes system.cpu.icache.ReadReq_accesses 1555 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 36274.074074 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35024.316109 # average ReadReq mshr miss latency @@ -261,6 +266,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 210 # system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 259 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 118 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 9780 # number of integer regfile reads +system.cpu.int_regfile_writes 4751 # number of integer regfile writes system.cpu.ipc 0.202151 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.202151 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -352,6 +359,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 12922 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 0.288346 # Inst issue rate +system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 7513 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 27837 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 6791 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 10538 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 8058 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 7373 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ @@ -436,7 +451,10 @@ system.cpu.memDep0.conflictingLoads 5 # Nu system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 2139 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1135 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 136 # number of misc regfile reads system.cpu.numCycles 25570 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 238 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 3410 # Number of HB maps that are committed system.cpu.rename.RENAME:IdleCycles 8931 # Number of cycles rename is idle @@ -448,10 +466,14 @@ system.cpu.rename.RENAME:RunCycles 2609 # Nu system.cpu.rename.RENAME:SquashCycles 649 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 81 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 2709 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 5 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 12083 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 414 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 16 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 196 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 11 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 21491 # The number of ROB reads +system.cpu.rob.rob_writes 19268 # The number of ROB writes system.cpu.timesIdled 259 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 8 # Number of system calls diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini index 6242699da..8a615b31d 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -111,7 +120,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/mips/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout index 5dbd10419..931c89646 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:13:04 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:11:22 -M5 executing on SC2B0619 +M5 compiled Feb 7 2011 01:55:51 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:01 +M5 executing on burrito command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt index a6694501e..d5304c4b4 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1101929 # Simulator instruction rate (inst/s) -host_mem_usage 183300 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 525428314 # Simulator tick rate (ticks/s) +host_inst_rate 106820 # Simulator instruction rate (inst/s) +host_mem_usage 216064 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host +host_tick_rate 53148750 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5827 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated @@ -29,8 +29,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 5828 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 5828 # Number of busy cycles +system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses +system.cpu.num_fp_insts 2 # number of float instructions +system.cpu.num_fp_register_reads 3 # number of times the floating registers were read +system.cpu.num_fp_register_writes 1 # number of times the floating registers were written +system.cpu.num_func_calls 194 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 5827 # Number of instructions executed -system.cpu.num_refs 2090 # Number of memory references +system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses +system.cpu.num_int_insts 5126 # number of integer instructions +system.cpu.num_int_register_reads 7301 # number of times the integer registers were read +system.cpu.num_int_register_writes 3409 # number of times the integer registers were written +system.cpu.num_load_insts 1164 # Number of load instructions +system.cpu.num_mem_refs 2090 # number of memory refs +system.cpu.num_store_insts 926 # Number of store instructions system.cpu.workload.PROG:num_syscalls 8 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini index b37edc581..15d83d7b2 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 [system] type=System -children=cpu physmem ruby -mem_mode=atomic +children=cpu dir_cntrl0 l1_cntrl0 physmem ruby +mem_mode=timing physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -86,8 +95,8 @@ progress_interval=0 system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1] -icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] +dcache_port=system.ruby.cpu_ruby_ports.port[1] +icache_port=system.ruby.cpu_ruby_ports.port[0] [system.cpu.dtb] type=MipsTLB @@ -108,7 +117,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/mips/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -119,6 +128,59 @@ simpoint=0 system=system uid=100 +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +directory=system.dir_cntrl0.directory +directory_latency=12 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.l1_cntrl0] +type=L1Cache_Controller +buffer_size=0 +cacheMemory=system.ruby.cpu_ruby_ports.dcache +cache_response_latency=12 +issue_latency=2 +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.ruby.cpu_ruby_ports +transitions_per_cycle=32 +version=0 + [system.physmem] type=PhysicalMemory file= @@ -127,35 +189,48 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort +port=system.ruby.cpu_ruby_ports.physMemPort [system.ruby] type=RubySystem -children=debug network profiler tracer +children=cpu_ruby_ports network profiler tracer block_size_bytes=64 clock=1 -debug=system.ruby.debug mem_size=134217728 network=system.ruby.network +no_mem_vec=false profiler=system.ruby.profiler random_seed=1234 randomization=false stats_filename=ruby.stats -tech_nm=45 tracer=system.ruby.tracer -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none +[system.ruby.cpu_ruby_ports] +type=RubySequencer +children=dcache +access_phys_mem=true +dcache=system.ruby.cpu_ruby_ports.dcache +deadlock_threshold=500000 +icache=system.ruby.cpu_ruby_ports.dcache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + +[system.ruby.cpu_ruby_ports.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 [system.ruby.network] type=SimpleNetwork children=topology -adaptive_routing=true +adaptive_routing=false buffer_size=0 control_msg_size=8 endpoint_bandwidth=10000 @@ -166,6 +241,7 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology children=ext_links0 ext_links1 int_links0 int_links1 +description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 num_int_nodes=3 @@ -173,93 +249,20 @@ print_config=false [system.ruby.network.topology.ext_links0] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node +ext_node=system.l1_cntrl0 int_node=0 latency=1 weight=1 -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=sequencer -buffer_size=0 -cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -cache_response_latency=12 -issue_latency=2 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links1] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node +ext_node=system.dir_cntrl0 int_node=1 latency=1 weight=1 -[system.ruby.network.topology.ext_links1.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links1.ext_node.directory -directory_latency=12 -memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.directory] -type=RubyDirectoryMemory -size=134217728 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout index 87d5c1036..4a1640a47 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 21 2010 11:12:15 -M5 revision a2fac757fb31+ 6860+ default qtip brad/rubycfg_orion_update tip -M5 started Jan 21 2010 11:12:51 -M5 executing on svvint07 +M5 compiled Feb 7 2011 01:55:51 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:00 +M5 executing on burrito command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index c0deed77b..0a46cd560 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 24278 # Simulator instruction rate (inst/s) -host_mem_usage 347460 # Number of bytes of host memory used +host_inst_rate 24226 # Simulator instruction rate (inst/s) +host_mem_usage 234168 # Number of bytes of host memory used host_seconds 0.24 # Real time elapsed on the host -host_tick_rate 1220626 # Simulator tick rate (ticks/s) +host_tick_rate 1216878 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 5827 # Number of instructions simulated sim_seconds 0.000293 # Number of seconds simulated @@ -29,8 +29,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 292960 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 292960 # Number of busy cycles +system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses +system.cpu.num_fp_insts 2 # number of float instructions +system.cpu.num_fp_register_reads 3 # number of times the floating registers were read +system.cpu.num_fp_register_writes 1 # number of times the floating registers were written +system.cpu.num_func_calls 194 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 5827 # Number of instructions executed -system.cpu.num_refs 2090 # Number of memory references +system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses +system.cpu.num_int_insts 5126 # number of integer instructions +system.cpu.num_int_register_reads 7301 # number of times the integer registers were read +system.cpu.num_int_register_writes 3409 # number of times the integer registers were written +system.cpu.num_load_insts 1164 # Number of load instructions +system.cpu.num_mem_refs 2090 # number of memory refs +system.cpu.num_store_insts 926 # Number of store instructions system.cpu.workload.PROG:num_syscalls 8 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini index e2f4de6ac..01d13de53 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout index bfd8a31fc..4a897b2a2 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing/simout -Redirecting stderr to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 12:56:28 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 12:56:30 -M5 executing on zizzer -command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing +M5 compiled Feb 7 2011 01:55:51 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:00 +M5 executing on burrito +command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt index f4ea21892..27b53a7ab 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 5098 # Simulator instruction rate (inst/s) -host_mem_usage 204896 # Number of bytes of host memory used -host_seconds 1.14 # Real time elapsed on the host -host_tick_rate 28066026 # Simulator tick rate (ticks/s) +host_inst_rate 344481 # Simulator instruction rate (inst/s) +host_mem_usage 223780 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 1868884758 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5827 # Number of instructions simulated sim_seconds 0.000032 # Number of seconds simulated @@ -213,8 +213,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 64176 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 64176 # Number of busy cycles +system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses +system.cpu.num_fp_insts 2 # number of float instructions +system.cpu.num_fp_register_reads 3 # number of times the floating registers were read +system.cpu.num_fp_register_writes 1 # number of times the floating registers were written +system.cpu.num_func_calls 194 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 5827 # Number of instructions executed -system.cpu.num_refs 2090 # Number of memory references +system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses +system.cpu.num_int_insts 5126 # number of integer instructions +system.cpu.num_int_register_reads 7301 # number of times the integer registers were read +system.cpu.num_int_register_writes 3409 # number of times the integer registers were written +system.cpu.num_load_insts 1164 # Number of load instructions +system.cpu.num_mem_refs 2090 # number of memory refs +system.cpu.num_store_insts 926 # Number of store instructions system.cpu.workload.PROG:num_syscalls 8 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini index 3d11c96e4..195dd9e9c 100644 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr index 29a71f392..799831583 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr @@ -1,5 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: allowing mmap of file @ fd 16206088. This will break if not /dev/zero. +warn: allowing mmap of file @ fd 42898616. This will break if not /dev/zero. For more information see: http://www.m5sim.org/warn/3a2134f6 hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/00.hello/ref/power/linux/o3-timing/simout index 6bd581433..9ed661104 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 17 2011 17:18:01 -M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase -M5 started Jan 17 2011 17:18:03 -M5 executing on zizzer +M5 compiled Feb 7 2011 02:06:34 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:06:41 +M5 executing on burrito command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt index 8b311d8d3..eed636458 100644 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 12762 # Simulator instruction rate (inst/s) -host_mem_usage 202140 # Number of bytes of host memory used -host_seconds 0.45 # Real time elapsed on the host -host_tick_rate 25804848 # Simulator tick rate (ticks/s) +host_inst_rate 32835 # Simulator instruction rate (inst/s) +host_mem_usage 222408 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host +host_tick_rate 66311402 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5800 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 10473 # Number of insts commited each cycle system.cpu.commit.COM:count 5800 # Number of instructions committed +system.cpu.commit.COM:fp_insts 22 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 103 # Number of function calls committed. +system.cpu.commit.COM:int_insts 5706 # Number of committed integer instructions. system.cpu.commit.COM:loads 962 # Number of loads committed system.cpu.commit.COM:membars 7 # Number of memory barriers committed system.cpu.commit.COM:refs 2008 # Number of memory references committed @@ -162,6 +165,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 11043 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 25 # number of floating regfile reads +system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.icache.ReadReq_accesses 1490 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 36422.279793 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 34777.108434 # average ReadReq mshr miss latency @@ -261,6 +266,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 404 # system.cpu.iew.memOrderViolationEvents 42 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 201 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 76 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 12419 # number of integer regfile reads +system.cpu.int_regfile_writes 6594 # number of integer regfile writes system.cpu.ipc 0.247156 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.247156 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -352,6 +359,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 11043 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 0.344697 # Inst issue rate +system.cpu.iq.fp_alu_accesses 31 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 59 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 8211 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 27329 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 7555 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 12158 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 9163 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 8089 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ @@ -437,6 +452,8 @@ system.cpu.memDep0.conflictingStores 29 # Nu system.cpu.memDep0.insertedLoads 1681 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1450 # Number of stores inserted to the mem dependence unit. system.cpu.numCycles 23467 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 312 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 5007 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 7 # Number of times rename has blocked due to IQ full @@ -449,10 +466,14 @@ system.cpu.rename.RENAME:RunCycles 1825 # Nu system.cpu.rename.RENAME:SquashCycles 570 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 243 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 3701 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 55 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 16177 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 337 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 22 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 473 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 19611 # The number of ROB reads +system.cpu.rob.rob_writes 18950 # The number of ROB writes system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 9 # Number of system calls diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini index 1ef6f51da..c4bee2b32 100644 --- a/tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -58,7 +67,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/power/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/power/linux/simple-atomic/simerr index a2a4d88c2..4e7b25b97 100755 --- a/tests/quick/00.hello/ref/power/linux/simple-atomic/simerr +++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/simerr @@ -1,5 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: allowing mmap of file @ fd 13074680. This will break if not /dev/zero. +warn: allowing mmap of file @ fd 39589752. This will break if not /dev/zero. For more information see: http://www.m5sim.org/warn/3a2134f6 hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/simout b/tests/quick/00.hello/ref/power/linux/simple-atomic/simout index 23b972156..dea57bc4d 100755 --- a/tests/quick/00.hello/ref/power/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:13:07 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 24 2010 23:13:11 -M5 executing on SC2B0619 +M5 compiled Feb 7 2011 02:06:34 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:06:40 +M5 executing on burrito command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt index 8c0754d0c..1731c3473 100644 --- a/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 277162 # Simulator instruction rate (inst/s) -host_mem_usage 181156 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 136566988 # Simulator tick rate (ticks/s) +host_inst_rate 628022 # Simulator instruction rate (inst/s) +host_mem_usage 214048 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 304927994 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5801 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated @@ -29,8 +29,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 5801 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 5801 # Number of busy cycles +system.cpu.num_conditional_control_insts 896 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 22 # Number of float alu accesses +system.cpu.num_fp_insts 22 # number of float instructions +system.cpu.num_fp_register_reads 20 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2 # number of times the floating registers were written +system.cpu.num_func_calls 200 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 5801 # Number of instructions executed -system.cpu.num_refs 2008 # Number of memory references +system.cpu.num_int_alu_accesses 5706 # Number of integer alu accesses +system.cpu.num_int_insts 5706 # number of integer instructions +system.cpu.num_int_register_reads 9541 # number of times the integer registers were read +system.cpu.num_int_register_writes 5005 # number of times the integer registers were written +system.cpu.num_load_insts 962 # Number of load instructions +system.cpu.num_mem_refs 2008 # number of memory refs +system.cpu.num_store_insts 1046 # Number of store instructions system.cpu.workload.PROG:num_syscalls 9 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini index de14f79c7..fe9f8a548 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -57,7 +66,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/sparc/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout index ec097652e..38db96c18 100755 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 25 2010 03:11:27 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:37:59 -M5 executing on SC2B0619 +M5 compiled Feb 7 2011 02:13:30 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:14:08 +M5 executing on burrito command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt index 01cd0d37d..2caa46c35 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 897027 # Simulator instruction rate (inst/s) -host_mem_usage 182692 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 434663663 # Simulator tick rate (ticks/s) +host_inst_rate 96674 # Simulator instruction rate (inst/s) +host_mem_usage 215848 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 48656953 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5340 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated @@ -11,8 +11,24 @@ sim_ticks 2701000 # Nu system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 5403 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 5403 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 5340 # Number of instructions executed -system.cpu.num_refs 1402 # Number of memory references +system.cpu.num_int_alu_accesses 4517 # Number of integer alu accesses +system.cpu.num_int_insts 4517 # number of integer instructions +system.cpu.num_int_register_reads 10620 # number of times the integer registers were read +system.cpu.num_int_register_writes 4859 # number of times the integer registers were written +system.cpu.num_load_insts 724 # Number of load instructions +system.cpu.num_mem_refs 1402 # number of memory refs +system.cpu.num_store_insts 678 # Number of store instructions system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini index eb5199f6d..6590fce9b 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 [system] type=System -children=cpu physmem ruby -mem_mode=atomic +children=cpu dir_cntrl0 l1_cntrl0 physmem ruby +mem_mode=timing physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -32,8 +41,8 @@ progress_interval=0 system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1] -icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] +dcache_port=system.ruby.cpu_ruby_ports.port[1] +icache_port=system.ruby.cpu_ruby_ports.port[0] [system.cpu.dtb] type=SparcTLB @@ -54,7 +63,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/sparc/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -65,6 +74,59 @@ simpoint=0 system=system uid=100 +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +directory=system.dir_cntrl0.directory +directory_latency=12 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.l1_cntrl0] +type=L1Cache_Controller +buffer_size=0 +cacheMemory=system.ruby.cpu_ruby_ports.dcache +cache_response_latency=12 +issue_latency=2 +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.ruby.cpu_ruby_ports +transitions_per_cycle=32 +version=0 + [system.physmem] type=PhysicalMemory file= @@ -73,35 +135,48 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort +port=system.ruby.cpu_ruby_ports.physMemPort [system.ruby] type=RubySystem -children=debug network profiler tracer +children=cpu_ruby_ports network profiler tracer block_size_bytes=64 clock=1 -debug=system.ruby.debug mem_size=134217728 network=system.ruby.network +no_mem_vec=false profiler=system.ruby.profiler random_seed=1234 randomization=false stats_filename=ruby.stats -tech_nm=45 tracer=system.ruby.tracer -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none +[system.ruby.cpu_ruby_ports] +type=RubySequencer +children=dcache +access_phys_mem=true +dcache=system.ruby.cpu_ruby_ports.dcache +deadlock_threshold=500000 +icache=system.ruby.cpu_ruby_ports.dcache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + +[system.ruby.cpu_ruby_ports.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 [system.ruby.network] type=SimpleNetwork children=topology -adaptive_routing=true +adaptive_routing=false buffer_size=0 control_msg_size=8 endpoint_bandwidth=10000 @@ -112,6 +187,7 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology children=ext_links0 ext_links1 int_links0 int_links1 +description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 num_int_nodes=3 @@ -119,93 +195,20 @@ print_config=false [system.ruby.network.topology.ext_links0] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node +ext_node=system.l1_cntrl0 int_node=0 latency=1 weight=1 -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=sequencer -buffer_size=0 -cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -cache_response_latency=12 -issue_latency=2 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links1] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node +ext_node=system.dir_cntrl0 int_node=1 latency=1 weight=1 -[system.ruby.network.topology.ext_links1.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links1.ext_node.directory -directory_latency=12 -memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.directory] -type=RubyDirectoryMemory -size=134217728 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats index 2464ac2ec..b11f8c789 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats @@ -4,16 +4,11 @@ RubySystem config: random_seed: 1234 randomization: 0 - tech_nm: 45 cycle_period: 1 block_size_bytes: 64 block_size_bits: 6 memory_size_bytes: 134217728 memory_size_bits: 27 -DirectoryMemory Global Config: - number of directory memories: 1 - total memory size bytes: 134217728 - total memory size bits: 27 Network Configuration --------------------- @@ -23,9 +18,9 @@ topology: virtual_net_0: active, ordered virtual_net_1: active, ordered virtual_net_2: active, ordered -virtual_net_3: inactive +virtual_net_3: active, ordered virtual_net_4: active, ordered -virtual_net_5: active, ordered +virtual_net_5: inactive virtual_net_6: inactive virtual_net_7: inactive virtual_net_8: inactive @@ -39,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jan/21/2010 11:30:49 +Real time: Feb/07/2011 02:13:39 Profiler Stats -------------- @@ -48,31 +43,20 @@ Elapsed_time_in_minutes: 0.0166667 Elapsed_time_in_hours: 0.000277778 Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.28 -Virtual_time_in_minutes: 0.00466667 -Virtual_time_in_hours: 7.77778e-05 -Virtual_time_in_days: 3.24074e-06 +Virtual_time_in_seconds: 0.34 +Virtual_time_in_minutes: 0.00566667 +Virtual_time_in_hours: 9.44444e-05 +Virtual_time_in_days: 3.93519e-06 Ruby_current_time: 253364 Ruby_start_time: 0 Ruby_cycles: 253364 -mbytes_resident: 34.3555 -mbytes_total: 34.5312 -resident_ratio: 0.995136 - -Total_misses: 0 -total_misses: 0 [ 0 ] -user_misses: 0 [ 0 ] -supervisor_misses: 0 [ 0 ] - -ruby_cycles_executed: 253365 [ 253365 ] - -transactions_started: 0 [ 0 ] -transactions_ended: 0 [ 0 ] -cycles_per_transaction: 0 [ 0 ] -misses_per_transaction: 0 [ 0 ] +mbytes_resident: 37.8555 +mbytes_total: 228.355 +resident_ratio: 0.165791 +ruby_cycles_executed: [ 253365 ] Busy Controller Counts: L1Cache-0:0 @@ -86,9 +70,27 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 6773 average: 1 | All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- miss_latency: [binsize: 2 max: 371 count: 6772 average: 36.4135 | standard deviation: 69.5949 | 0 5483 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 4 2 2 10 2 309 224 133 323 144 9 3 1 0 0 11 11 1 16 4 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 25 14 6 15 3 1 1 1 0 0 1 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_1: [binsize: 2 max: 285 count: 5383 average: 26.3539 | standard deviation: 60.2129 | 0 4668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 5 2 172 118 76 168 91 3 1 1 0 0 8 9 0 10 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 18 3 4 10 1 0 0 1 0 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 2 max: 285 count: 716 average: 98.7235 | standard deviation: 87.4535 | 0 321 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 3 0 110 62 31 116 36 4 1 0 0 0 1 0 1 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 2 2 3 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 2 max: 371 count: 673 average: 50.584 | standard deviation: 80.4924 | 0 494 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 27 44 26 39 17 2 1 0 0 0 2 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 9 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_IFETCH: [binsize: 2 max: 285 count: 5383 average: 26.3539 | standard deviation: 60.2129 | 0 4668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 5 2 172 118 76 168 91 3 1 1 0 0 8 9 0 10 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 18 3 4 10 1 0 0 1 0 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 2 max: 285 count: 716 average: 98.7235 | standard deviation: 87.4535 | 0 321 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 3 0 110 62 31 116 36 4 1 0 0 0 1 0 1 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 2 2 3 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 371 count: 673 average: 50.584 | standard deviation: 80.4924 | 0 494 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 27 44 26 39 17 2 1 0 0 0 2 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 9 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_L1Cache: [binsize: 1 max: 3 count: 5483 average: 3 | standard deviation: 0 | 0 0 0 5483 ] +miss_latency_Directory: [binsize: 2 max: 371 count: 1289 average: 178.544 | standard deviation: 22.1923 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 4 2 2 10 2 309 224 133 323 144 9 3 1 0 0 11 11 1 16 4 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 25 14 6 15 3 1 1 1 0 0 1 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average: 159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +imcomplete_dir_Times: 1288 +miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 4668 average: 3 | standard deviation: 0 | 0 0 0 4668 ] +miss_latency_IFETCH_Directory: [binsize: 2 max: 285 count: 715 average: 178.824 | standard deviation: 21.9931 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 5 2 172 118 76 168 91 3 1 1 0 0 8 9 0 10 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 18 3 4 10 1 0 0 1 0 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 321 average: 3 | standard deviation: 0 | 0 0 0 321 ] +miss_latency_LD_Directory: [binsize: 2 max: 285 count: 395 average: 176.514 | standard deviation: 18.6332 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 3 0 110 62 31 116 36 4 1 0 0 0 1 0 1 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 2 2 3 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 494 average: 3 | standard deviation: 0 | 0 0 0 494 ] +miss_latency_ST_Directory: [binsize: 2 max: 371 count: 179 average: 181.905 | standard deviation: 28.882 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 27 44 26 39 17 2 1 0 0 0 2 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 9 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -120,25 +122,31 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 7494 -page_faults: 2200 +page_reclaims: 11225 +page_faults: 3 swaps: 0 -block_inputs: 0 -block_outputs: 0 +block_inputs: 1280 +block_outputs: 64 Network Stats ------------- +total_msg_count_Control: 3867 30936 +total_msg_count_Data: 3855 277560 +total_msg_count_Response_Data: 3867 278424 +total_msg_count_Writeback_Control: 3855 30840 +total_msgs: 15444 total_bytes: 617760 + switch_0_inlinks: 2 switch_0_outlinks: 2 links_utilized_percent_switch_0: 0.158621 links_utilized_percent_switch_0_link_0: 0.0635745 bw: 640000 base_latency: 1 links_utilized_percent_switch_0_link_1: 0.253667 bw: 160000 base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 1289 92808 [ 0 1289 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 1285 10280 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Control: 1289 10312 [ 1289 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Data: 1285 92520 [ 1285 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 1289 92808 [ 0 0 0 0 1289 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 1285 10280 [ 0 0 0 1285 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 1289 10312 [ 0 0 1289 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Data: 1285 92520 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 @@ -146,10 +154,10 @@ links_utilized_percent_switch_1: 0.158857 links_utilized_percent_switch_1_link_0: 0.0634167 bw: 640000 base_latency: 1 links_utilized_percent_switch_1_link_1: 0.254298 bw: 160000 base_latency: 1 - outgoing_messages_switch_1_link_0_Control: 1289 10312 [ 1289 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Data: 1285 92520 [ 1285 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 1289 92808 [ 0 1289 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 1285 10280 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Control: 1289 10312 [ 0 0 1289 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Data: 1285 92520 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 1289 92808 [ 0 0 0 0 1289 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 1285 10280 [ 0 0 0 1285 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 @@ -157,63 +165,64 @@ links_utilized_percent_switch_2: 0.253982 links_utilized_percent_switch_2_link_0: 0.254298 bw: 160000 base_latency: 1 links_utilized_percent_switch_2_link_1: 0.253667 bw: 160000 base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 1289 92808 [ 0 1289 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 1285 10280 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Control: 1289 10312 [ 1289 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Data: 1285 92520 [ 1285 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 1289 92808 [ 0 0 0 0 1289 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 1285 10280 [ 0 0 0 1285 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Control: 1289 10312 [ 0 0 1289 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Data: 1285 92520 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 1289 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 1289 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf +Cache Stats: system.ruby.cpu_ruby_ports.dcache + system.ruby.cpu_ruby_ports.dcache_total_misses: 1289 + system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 1289 + system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0 + system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0 + system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD: 30.6439% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST: 13.8867% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH: 55.4694% + system.ruby.cpu_ruby_ports.dcache_request_type_LD: 30.6439% + system.ruby.cpu_ruby_ports.dcache_request_type_ST: 13.8867% + system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH: 55.4694% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 1289 100% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 8 count: 1289 average: 5.1249 | standard deviation: 2.01759 | 0 50 2 0 836 0 0 0 401 ] + system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 1289 100% - --- L1Cache 0 --- + --- L1Cache --- - Event Counts - -Load 716 -Ifetch 5383 -Store 673 -Data 1289 -Fwd_GETX 0 -Inv 0 -Replacement 1285 -Writeback_Ack 1285 -Writeback_Nack 0 +Load [716 ] 716 +Ifetch [5383 ] 5383 +Store [673 ] 673 +Data [1289 ] 1289 +Fwd_GETX [0 ] 0 +Inv [0 ] 0 +Replacement [1285 ] 1285 +Writeback_Ack [1285 ] 1285 +Writeback_Nack [0 ] 0 - Transitions - -I Load 395 -I Ifetch 715 -I Store 179 -I Inv 0 <-- -I Replacement 0 <-- +I Load [395 ] 395 +I Ifetch [715 ] 715 +I Store [179 ] 179 +I Inv [0 ] 0 +I Replacement [0 ] 0 + +II Writeback_Nack [0 ] 0 -II Writeback_Nack 0 <-- +M Load [321 ] 321 +M Ifetch [4668 ] 4668 +M Store [494 ] 494 +M Fwd_GETX [0 ] 0 +M Inv [0 ] 0 +M Replacement [1285 ] 1285 -M Load 321 -M Ifetch 4668 -M Store 494 -M Fwd_GETX 0 <-- -M Inv 0 <-- -M Replacement 1285 +MI Fwd_GETX [0 ] 0 +MI Inv [0 ] 0 +MI Writeback_Ack [1285 ] 1285 +MI Writeback_Nack [0 ] 0 -MI Fwd_GETX 0 <-- -MI Inv 0 <-- -MI Writeback_Ack 1285 +MII Fwd_GETX [0 ] 0 -IS Data 1110 +IS Data [1110 ] 1110 -IM Data 179 +IM Data [179 ] 179 -Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer: +Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 2574 memory_reads: 1289 memory_writes: 1285 @@ -233,70 +242,69 @@ Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer: memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 166 40 36 48 109 42 63 241 50 34 16 26 60 64 38 46 30 88 202 144 40 58 22 20 60 120 136 125 84 134 166 66 - --- Directory 0 --- + --- Directory --- - Event Counts - -GETX 1289 -GETS 0 -PUTX 1285 -PUTX_NotOwner 0 -DMA_READ 0 -DMA_WRITE 0 -Memory_Data 1289 -Memory_Ack 1285 +GETX [1289 ] 1289 +GETS [0 ] 0 +PUTX [1285 ] 1285 +PUTX_NotOwner [0 ] 0 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +Memory_Data [1289 ] 1289 +Memory_Ack [1285 ] 1285 - Transitions - -I GETX 1289 -I PUTX_NotOwner 0 <-- -I DMA_READ 0 <-- -I DMA_WRITE 0 <-- - -M GETX 0 <-- -M PUTX 1285 -M PUTX_NotOwner 0 <-- -M DMA_READ 0 <-- -M DMA_WRITE 0 <-- - -M_DRD GETX 0 <-- -M_DRD PUTX 0 <-- - -M_DWR GETX 0 <-- -M_DWR PUTX 0 <-- - -M_DWRI GETX 0 <-- -M_DWRI Memory_Ack 0 <-- - -M_DRDI GETX 0 <-- -M_DRDI Memory_Ack 0 <-- - -IM GETX 0 <-- -IM GETS 0 <-- -IM PUTX 0 <-- -IM PUTX_NotOwner 0 <-- -IM DMA_READ 0 <-- -IM DMA_WRITE 0 <-- -IM Memory_Data 1289 - -MI GETX 0 <-- -MI GETS 0 <-- -MI PUTX 0 <-- -MI PUTX_NotOwner 0 <-- -MI DMA_READ 0 <-- -MI DMA_WRITE 0 <-- -MI Memory_Ack 1285 - -ID GETX 0 <-- -ID GETS 0 <-- -ID PUTX 0 <-- -ID PUTX_NotOwner 0 <-- -ID DMA_READ 0 <-- -ID DMA_WRITE 0 <-- -ID Memory_Data 0 <-- - -ID_W GETX 0 <-- -ID_W GETS 0 <-- -ID_W PUTX 0 <-- -ID_W PUTX_NotOwner 0 <-- -ID_W DMA_READ 0 <-- -ID_W DMA_WRITE 0 <-- -ID_W Memory_Ack 0 <-- - +I GETX [1289 ] 1289 +I PUTX_NotOwner [0 ] 0 +I DMA_READ [0 ] 0 +I DMA_WRITE [0 ] 0 + +M GETX [0 ] 0 +M PUTX [1285 ] 1285 +M PUTX_NotOwner [0 ] 0 +M DMA_READ [0 ] 0 +M DMA_WRITE [0 ] 0 + +M_DRD GETX [0 ] 0 +M_DRD PUTX [0 ] 0 + +M_DWR GETX [0 ] 0 +M_DWR PUTX [0 ] 0 + +M_DWRI GETX [0 ] 0 +M_DWRI Memory_Ack [0 ] 0 + +M_DRDI GETX [0 ] 0 +M_DRDI Memory_Ack [0 ] 0 + +IM GETX [0 ] 0 +IM GETS [0 ] 0 +IM PUTX [0 ] 0 +IM PUTX_NotOwner [0 ] 0 +IM DMA_READ [0 ] 0 +IM DMA_WRITE [0 ] 0 +IM Memory_Data [1289 ] 1289 + +MI GETX [0 ] 0 +MI GETS [0 ] 0 +MI PUTX [0 ] 0 +MI PUTX_NotOwner [0 ] 0 +MI DMA_READ [0 ] 0 +MI DMA_WRITE [0 ] 0 +MI Memory_Ack [1285 ] 1285 + +ID GETX [0 ] 0 +ID GETS [0 ] 0 +ID PUTX [0 ] 0 +ID PUTX_NotOwner [0 ] 0 +ID DMA_READ [0 ] 0 +ID DMA_WRITE [0 ] 0 +ID Memory_Data [0 ] 0 + +ID_W GETX [0 ] 0 +ID_W GETS [0 ] 0 +ID_W PUTX [0 ] 0 +ID_W PUTX_NotOwner [0 ] 0 +ID_W DMA_READ [0 ] 0 +ID_W DMA_WRITE [0 ] 0 +ID_W Memory_Ack
\ No newline at end of file diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout index e4e5995ba..c97aaa4c9 100755 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 21 2010 11:29:25 -M5 revision a2fac757fb31+ 6860+ default qtip brad/rubycfg_orion_update tip -M5 started Jan 21 2010 11:30:48 -M5 executing on svvint07 +M5 compiled Feb 7 2011 02:13:30 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:13:38 +M5 executing on burrito command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt index aa77d6897..5961a0ac8 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 59331 # Simulator instruction rate (inst/s) -host_mem_usage 347024 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -host_tick_rate 2815062 # Simulator tick rate (ticks/s) +host_inst_rate 26190 # Simulator instruction rate (inst/s) +host_mem_usage 233840 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host +host_tick_rate 1241276 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 5340 # Number of instructions simulated sim_seconds 0.000253 # Number of seconds simulated @@ -11,8 +11,24 @@ sim_ticks 253364 # Nu system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 253364 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 253364 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 5340 # Number of instructions executed -system.cpu.num_refs 1402 # Number of memory references +system.cpu.num_int_alu_accesses 4517 # Number of integer alu accesses +system.cpu.num_int_insts 4517 # number of integer instructions +system.cpu.num_int_register_reads 10620 # number of times the integer registers were read +system.cpu.num_int_register_writes 4858 # number of times the integer registers were written +system.cpu.num_load_insts 724 # Number of load instructions +system.cpu.num_mem_refs 1402 # number of memory refs +system.cpu.num_store_insts 678 # Number of store instructions system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini index 35f8386c3..d416eae87 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout index 9b5f99faf..1b1015662 100755 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing/simout -Redirecting stderr to build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 13:03:41 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 13:05:08 -M5 executing on zizzer -command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing +M5 compiled Feb 7 2011 02:13:30 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:14:00 +M5 executing on burrito +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello World!Exiting @ tick 28206000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt index 49d0076df..d21947f29 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 369934 # Simulator instruction rate (inst/s) -host_mem_usage 207380 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 1923223783 # Simulator tick rate (ticks/s) +host_inst_rate 87383 # Simulator instruction rate (inst/s) +host_mem_usage 223480 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 459485360 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5340 # Number of instructions simulated sim_seconds 0.000028 # Number of seconds simulated @@ -195,8 +195,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 56412 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 56412 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 5340 # Number of instructions executed -system.cpu.num_refs 1402 # Number of memory references +system.cpu.num_int_alu_accesses 4517 # Number of integer alu accesses +system.cpu.num_int_insts 4517 # number of integer instructions +system.cpu.num_int_register_reads 10620 # number of times the integer registers were read +system.cpu.num_int_register_writes 4858 # number of times the integer registers were written +system.cpu.num_load_insts 724 # Number of load instructions +system.cpu.num_mem_refs 1402 # number of memory refs +system.cpu.num_store_insts 678 # Number of store instructions system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini index 202d0b795..1fab00bfb 100644 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini @@ -10,6 +10,13 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout index 12f04436f..0767b9777 100755 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 31 2011 16:34:44 -M5 revision 1b98eea40540 7883 default qtip tip x86o3regressions.patch -M5 started Jan 31 2011 16:34:46 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:32:13 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt index 0a112c922..182e72d25 100644 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 48300 # Simulator instruction rate (inst/s) -host_mem_usage 226820 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host -host_tick_rate 67673766 # Simulator tick rate (ticks/s) +host_inst_rate 47133 # Simulator instruction rate (inst/s) +host_mem_usage 227692 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host +host_tick_rate 66053082 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9809 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 15124 # Number of insts commited each cycle system.cpu.commit.COM:count 9809 # Number of instructions committed +system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 0 # Number of function calls committed. +system.cpu.commit.COM:int_insts 9714 # Number of committed integer instructions. system.cpu.commit.COM:loads 1056 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 1990 # Number of memory references committed @@ -150,6 +153,7 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 15845 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 2 # number of floating regfile reads system.cpu.icache.ReadReq_accesses 1255 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 37417.543860 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35040.697674 # average ReadReq mshr miss latency @@ -249,6 +253,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 304 # system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 390 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 25083 # number of integer regfile reads +system.cpu.int_regfile_writes 11189 # number of integer regfile writes system.cpu.ipc 0.356263 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.356263 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued @@ -340,6 +346,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 6 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 15845 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 0.454146 # Inst issue rate +system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 12501 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 40849 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 11816 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 16975 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 13618 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 12504 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 17 # Number of non-speculative instructions added to the IQ @@ -414,7 +428,10 @@ system.cpu.memDep0.conflictingLoads 4 # Nu system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 1535 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1238 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 5334 # number of misc regfile reads system.cpu.numCycles 27533 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 105 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 9368 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full @@ -427,10 +444,14 @@ system.cpu.rename.RENAME:RunCycles 8027 # Nu system.cpu.rename.RENAME:SquashCycles 721 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 108 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 4419 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 16 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 38648 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 281 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 20 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 169 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 17 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 28728 # The number of ROB reads +system.cpu.rob.rob_writes 28005 # The number of ROB writes system.cpu.timesIdled 208 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 11 # Number of system calls diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini index f4bc2655d..ee37f754f 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini @@ -10,6 +10,13 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout index 0a2d88a32..09f4d0b50 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 31 2011 14:03:49 -M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip -M5 started Jan 31 2011 14:03:51 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:32:13 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt index 7219cd6a7..1dca11ec5 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 137874 # Simulator instruction rate (inst/s) -host_mem_usage 215488 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host -host_tick_rate 79078853 # Simulator tick rate (ticks/s) +host_inst_rate 180423 # Simulator instruction rate (inst/s) +host_mem_usage 219128 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host +host_tick_rate 103433649 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9810 # Number of instructions simulated sim_seconds 0.000006 # Number of seconds simulated @@ -11,8 +11,24 @@ sim_ticks 5651000 # Nu system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 11303 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 11303 # Number of busy cycles +system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 9810 # Number of instructions executed -system.cpu.num_refs 1990 # Number of memory references +system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses +system.cpu.num_int_insts 9715 # number of integer instructions +system.cpu.num_int_register_reads 26194 # number of times the integer registers were read +system.cpu.num_int_register_writes 9368 # number of times the integer registers were written +system.cpu.num_load_insts 1056 # Number of load instructions +system.cpu.num_mem_refs 1990 # number of memory refs +system.cpu.num_store_insts 934 # Number of store instructions system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini index 5985e429a..a51884b7a 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini @@ -10,6 +10,13 @@ type=System children=cpu dir_cntrl0 l1_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -147,6 +154,7 @@ tracer=system.ruby.tracer [system.ruby.cpu_ruby_ports] type=RubySequencer children=dcache +access_phys_mem=true dcache=system.ruby.cpu_ruby_ports.dcache deadlock_threshold=500000 icache=system.ruby.cpu_ruby_ports.dcache diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats index adfa92f7c..a12716c02 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Feb/04/2011 03:47:05 +Real time: Feb/07/2011 02:32:13 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.19 -Virtual_time_in_minutes: 0.00316667 -Virtual_time_in_hours: 5.27778e-05 -Virtual_time_in_days: 2.19907e-06 +Virtual_time_in_seconds: 0.35 +Virtual_time_in_minutes: 0.00583333 +Virtual_time_in_hours: 9.72222e-05 +Virtual_time_in_days: 4.05093e-06 Ruby_current_time: 276484 Ruby_start_time: 0 Ruby_cycles: 276484 -mbytes_resident: 38.8594 -mbytes_total: 233.992 -resident_ratio: 0.166088 +mbytes_resident: 38.6094 +mbytes_total: 231.508 +resident_ratio: 0.16679 ruby_cycles_executed: [ 276485 ] @@ -71,8 +71,9 @@ All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- miss_latency: [binsize: 2 max: 371 count: 8900 average: 30.0656 | standard deviation: 63.8436 | 0 7523 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 9 4 1 3 2 328 243 178 299 187 7 4 1 3 0 8 6 4 9 5 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 6 11 19 16 9 0 1 0 1 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ] miss_latency_IFETCH: [binsize: 2 max: 369 count: 6910 average: 18.6938 | standard deviation: 50.1996 | 0 6287 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 2 2 0 1 0 158 125 57 116 102 5 3 0 2 0 8 5 3 4 4 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 2 3 8 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_LD: [binsize: 2 max: 293 count: 1056 average: 86.3144 | standard deviation: 89.2896 | 0 556 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 1 1 1 1 104 47 87 151 61 1 0 0 1 0 0 1 0 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 14 8 2 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 2 max: 293 count: 1048 average: 86.792 | standard deviation: 89.333 | 0 549 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 1 1 1 1 103 47 87 151 61 1 0 0 1 0 0 1 0 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 14 8 2 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST: [binsize: 2 max: 371 count: 934 average: 50.6017 | standard deviation: 78.9939 | 0 680 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 0 1 1 66 71 34 32 24 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 8 2 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_RMW_Read: [binsize: 1 max: 169 count: 8 average: 23.75 | standard deviation: 58.6905 | 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_L1Cache: [binsize: 1 max: 3 count: 7523 average: 3 | standard deviation: 0 | 0 0 0 7523 ] miss_latency_Directory: [binsize: 2 max: 371 count: 1377 average: 177.934 | standard deviation: 21.7881 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 9 4 1 3 2 328 243 178 299 187 7 4 1 3 0 8 6 4 9 5 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 6 11 19 16 9 0 1 0 1 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -87,10 +88,12 @@ miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 ave imcomplete_dir_Times: 1376 miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 6287 average: 3 | standard deviation: 0 | 0 0 0 6287 ] miss_latency_IFETCH_Directory: [binsize: 2 max: 369 count: 623 average: 177.067 | standard deviation: 19.4782 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 2 2 0 1 0 158 125 57 116 102 5 3 0 2 0 8 5 3 4 4 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 2 3 8 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 556 average: 3 | standard deviation: 0 | 0 0 0 556 ] -miss_latency_LD_Directory: [binsize: 2 max: 293 count: 500 average: 178.96 | standard deviation: 22.8334 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 1 1 1 1 104 47 87 151 61 1 0 0 1 0 0 1 0 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 14 8 2 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 549 average: 3 | standard deviation: 0 | 0 0 0 549 ] +miss_latency_LD_Directory: [binsize: 2 max: 293 count: 499 average: 178.98 | standard deviation: 22.8519 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 1 1 1 1 103 47 87 151 61 1 0 0 1 0 0 1 0 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 14 8 2 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 680 average: 3 | standard deviation: 0 | 0 0 0 680 ] miss_latency_ST_Directory: [binsize: 2 max: 371 count: 254 average: 178.039 | standard deviation: 24.8377 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 0 1 1 66 71 34 32 24 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 8 2 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_RMW_Read_L1Cache: [binsize: 1 max: 3 count: 7 average: 3 | standard deviation: 0 | 0 0 0 7 ] +miss_latency_RMW_Read_Directory: [binsize: 1 max: 169 count: 1 average: 169 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -122,7 +125,7 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 11021 +page_reclaims: 10950 page_faults: 0 swaps: 0 block_inputs: 0 @@ -177,17 +180,17 @@ Cache Stats: system.ruby.cpu_ruby_ports.dcache system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0 system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0 - system.ruby.cpu_ruby_ports.dcache_request_type_LD: 36.3108% - system.ruby.cpu_ruby_ports.dcache_request_type_ST: 18.4459% + system.ruby.cpu_ruby_ports.dcache_request_type_LD: 36.2382% + system.ruby.cpu_ruby_ports.dcache_request_type_ST: 18.5185% system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH: 45.2433% system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 1377 100% --- L1Cache --- - Event Counts - -Load [1056 ] 1056 +Load [1048 ] 1048 Ifetch [6910 ] 6910 -Store [934 ] 934 +Store [942 ] 942 Data [1377 ] 1377 Fwd_GETX [0 ] 0 Inv [0 ] 0 @@ -196,17 +199,17 @@ Writeback_Ack [1373 ] 1373 Writeback_Nack [0 ] 0 - Transitions - -I Load [500 ] 500 +I Load [499 ] 499 I Ifetch [623 ] 623 -I Store [254 ] 254 +I Store [255 ] 255 I Inv [0 ] 0 I Replacement [0 ] 0 II Writeback_Nack [0 ] 0 -M Load [556 ] 556 +M Load [549 ] 549 M Ifetch [6287 ] 6287 -M Store [680 ] 680 +M Store [687 ] 687 M Fwd_GETX [0 ] 0 M Inv [0 ] 0 M Replacement [1373 ] 1373 @@ -218,9 +221,9 @@ MI Writeback_Nack [0 ] 0 MII Fwd_GETX [0 ] 0 -IS Data [1123 ] 1123 +IS Data [1122 ] 1122 -IM Data [254 ] 254 +IM Data [255 ] 255 Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 2750 diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout index 4e5806bd6..877c8d9b9 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 4 2011 03:47:02 -M5 revision afcc4492291f 7892 default qbase qtip rubystatupdate.patch tip -M5 started Feb 4 2011 03:47:05 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:32:13 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index 806c6c56a..b88df01c5 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 106685 # Simulator instruction rate (inst/s) -host_mem_usage 239612 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -host_tick_rate 3002497 # Simulator tick rate (ticks/s) +host_inst_rate 32378 # Simulator instruction rate (inst/s) +host_mem_usage 237068 # Number of bytes of host memory used +host_seconds 0.30 # Real time elapsed on the host +host_tick_rate 911908 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 9810 # Number of instructions simulated sim_seconds 0.000276 # Number of seconds simulated @@ -11,8 +11,24 @@ sim_ticks 276484 # Nu system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 276484 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 276484 # Number of busy cycles +system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 9810 # Number of instructions executed -system.cpu.num_refs 1990 # Number of memory references +system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses +system.cpu.num_int_insts 9715 # number of integer instructions +system.cpu.num_int_register_reads 26194 # number of times the integer registers were read +system.cpu.num_int_register_writes 9368 # number of times the integer registers were written +system.cpu.num_load_insts 1056 # Number of load instructions +system.cpu.num_mem_refs 1990 # number of memory refs +system.cpu.num_store_insts 934 # Number of store instructions system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini index 9743aff19..ab79b8cce 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini @@ -10,6 +10,13 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout index d7b40c980..d6afbecf0 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 31 2011 14:03:49 -M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip -M5 started Jan 31 2011 14:03:51 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:32:24 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt index 519e51040..0c21882f5 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 101671 # Simulator instruction rate (inst/s) -host_mem_usage 223168 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host -host_tick_rate 297579540 # Simulator tick rate (ticks/s) +host_inst_rate 594010 # Simulator instruction rate (inst/s) +host_mem_usage 226844 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 1712507148 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9810 # Number of instructions simulated sim_seconds 0.000029 # Number of seconds simulated @@ -195,8 +195,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 57536 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 57536 # Number of busy cycles +system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 9810 # Number of instructions executed -system.cpu.num_refs 1990 # Number of memory references +system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses +system.cpu.num_int_insts 9715 # number of integer instructions +system.cpu.num_int_register_reads 26194 # number of times the integer registers were read +system.cpu.num_int_register_writes 9368 # number of times the integer registers were written +system.cpu.num_load_insts 1056 # Number of load instructions +system.cpu.num_mem_refs 1990 # number of memory refs +system.cpu.num_store_insts 934 # Number of store instructions system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index eef6bf91e..0109e92d9 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index 1d43d276a..e012c16b8 100755 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 17 2011 16:24:53 -M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase -M5 started Jan 17 2011 16:24:57 -M5 executing on zizzer +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:39 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 561bc8cb1..816b3e660 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 10660 # Simulator instruction rate (inst/s) -host_mem_usage 204092 # Number of bytes of host memory used -host_seconds 1.20 # Real time elapsed on the host -host_tick_rate 11797749 # Simulator tick rate (ticks/s) +host_inst_rate 41761 # Simulator instruction rate (inst/s) +host_mem_usage 224488 # Number of bytes of host memory used +host_seconds 0.31 # Real time elapsed on the host +host_tick_rate 46181742 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 12773 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated @@ -43,6 +43,15 @@ system.cpu.commit.COM:committed_per_cycle::total 22158 system.cpu.commit.COM:count::0 6404 # Number of instructions committed system.cpu.commit.COM:count::1 6403 # Number of instructions committed system.cpu.commit.COM:count::total 12807 # Number of instructions committed +system.cpu.commit.COM:fp_insts::0 10 # Number of committed floating point instructions. +system.cpu.commit.COM:fp_insts::1 10 # Number of committed floating point instructions. +system.cpu.commit.COM:fp_insts::total 20 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls::0 127 # Number of function calls committed. +system.cpu.commit.COM:function_calls::1 127 # Number of function calls committed. +system.cpu.commit.COM:function_calls::total 254 # Number of function calls committed. +system.cpu.commit.COM:int_insts::0 6321 # Number of committed integer instructions. +system.cpu.commit.COM:int_insts::1 6321 # Number of committed integer instructions. +system.cpu.commit.COM:int_insts::total 12642 # Number of committed integer instructions. system.cpu.commit.COM:loads::0 1185 # Number of loads committed system.cpu.commit.COM:loads::1 1185 # Number of loads committed system.cpu.commit.COM:loads::total 2370 # Number of loads committed @@ -239,6 +248,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 22205 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 16 # number of floating regfile reads +system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.icache.ReadReq_accesses 3993 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency::0 35767.942584 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 35767.942584 # average ReadReq miss latency @@ -424,6 +435,8 @@ system.cpu.iew.lsq.thread.1.squashedStores 367 # system.cpu.iew.memOrderViolationEvents 131 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 1010 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 260 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 23900 # number of integer regfile reads +system.cpu.int_regfile_writes 13586 # number of integer regfile writes system.cpu.ipc::0 0.225857 # IPC: Instructions Per Cycle system.cpu.ipc::1 0.225821 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.451678 # IPC: Total IPC of All Threads @@ -590,6 +603,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 22205 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 0.703773 # Inst issue rate +system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 20041 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 62207 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 18120 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 32069 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 22957 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 19902 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ @@ -737,7 +758,11 @@ system.cpu.memDep1.conflictingLoads 22 # Nu system.cpu.memDep1.conflictingStores 7 # Number of conflicting stores. system.cpu.memDep1.insertedLoads 2368 # Number of loads inserted to the mem dependence unit. system.cpu.memDep1.insertedStores 1232 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 2 # number of misc regfile reads +system.cpu.misc_regfile_writes 2 # number of misc regfile writes system.cpu.numCycles 28279 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 2728 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 9166 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 4 # Number of times rename has blocked due to IQ full @@ -751,10 +776,14 @@ system.cpu.rename.RENAME:RunCycles 4411 # Nu system.cpu.rename.RENAME:SquashCycles 2039 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 1326 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 9705 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 34 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 31597 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 679 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 50 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 3216 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 38 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 106394 # The number of ROB reads +system.cpu.rob.rob_writes 48170 # The number of ROB writes system.cpu.timesIdled 276 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini index 285549a9c..4c6ef2b94 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout index 7c5c285a5..a2a0eb0e5 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 17 2011 21:17:52 -M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase -M5 started Jan 17 2011 21:18:06 -M5 executing on zizzer +M5 compiled Feb 7 2011 02:13:30 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:13:49 +M5 executing on burrito command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 5aa081cb3..7ae6650a8 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 91156 # Simulator instruction rate (inst/s) -host_mem_usage 203828 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host -host_tick_rate 117504787 # Simulator tick rate (ticks/s) +host_inst_rate 30834 # Simulator instruction rate (inst/s) +host_mem_usage 224180 # Number of bytes of host memory used +host_seconds 0.47 # Real time elapsed on the host +host_tick_rate 39786625 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 14449 # Number of instructions simulated sim_seconds 0.000019 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 27579 # Number of insts commited each cycle system.cpu.commit.COM:count 15175 # Number of instructions committed +system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 0 # Number of function calls committed. +system.cpu.commit.COM:int_insts 12186 # Number of committed integer instructions. system.cpu.commit.COM:loads 2226 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 3674 # Number of memory references committed @@ -251,6 +254,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 477 # system.cpu.iew.memOrderViolationEvents 54 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 560 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 240 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 28146 # number of integer regfile reads +system.cpu.int_regfile_writes 15679 # number of integer regfile writes system.cpu.ipc 0.387238 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.387238 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -342,6 +347,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 28740 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 0.483451 # Inst issue rate +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 18164 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 65024 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 17128 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 23367 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 18671 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 18039 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 566 # Number of non-speculative instructions added to the IQ @@ -417,7 +430,11 @@ system.cpu.memDep0.conflictingLoads 13 # Nu system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 3058 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1925 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 6238 # number of misc regfile reads +system.cpu.misc_regfile_writes 569 # number of misc regfile writes system.cpu.numCycles 37313 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 254 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 13832 # Number of HB maps that are committed system.cpu.rename.RENAME:IdleCycles 13569 # Number of cycles rename is idle @@ -429,10 +446,13 @@ system.cpu.rename.RENAME:RunCycles 7042 # Nu system.cpu.rename.RENAME:SquashCycles 1178 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 421 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 5696 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:int_rename_lookups 40450 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 6276 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 617 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 2691 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 583 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 46980 # The number of ROB reads +system.cpu.rob.rob_writes 41800 # The number of ROB writes system.cpu.timesIdled 183 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 18 # Number of system calls diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini index 91a9c57a5..15ddd6551 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -57,7 +66,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/insttest/bin/sparc/linux/insttest +executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout index a758d34e6..d6e92afd2 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 25 2010 03:11:27 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:38:01 -M5 executing on SC2B0619 +M5 compiled Feb 7 2011 02:13:30 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:13:50 +M5 executing on burrito command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt index 970d208fc..1a17f9fac 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1098364 # Simulator instruction rate (inst/s) -host_mem_usage 182400 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 540894569 # Simulator tick rate (ticks/s) +host_inst_rate 73199 # Simulator instruction rate (inst/s) +host_mem_usage 215552 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host +host_tick_rate 36700023 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 15175 # Number of instructions simulated sim_seconds 0.000008 # Number of seconds simulated @@ -11,8 +11,24 @@ sim_ticks 7618500 # Nu system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 15238 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 15238 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 15175 # Number of instructions executed -system.cpu.num_refs 3684 # Number of memory references +system.cpu.num_int_alu_accesses 12231 # Number of integer alu accesses +system.cpu.num_int_insts 12231 # number of integer instructions +system.cpu.num_int_register_reads 29059 # number of times the integer registers were read +system.cpu.num_int_register_writes 13832 # number of times the integer registers were written +system.cpu.num_load_insts 2232 # Number of load instructions +system.cpu.num_mem_refs 3684 # number of memory refs +system.cpu.num_store_insts 1452 # Number of store instructions system.cpu.workload.PROG:num_syscalls 18 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini index 04665360b..d782c12d4 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout index 27524a121..7fbb77bf6 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing/simout -Redirecting stderr to build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 13:03:41 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 13:03:44 -M5 executing on zizzer -command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing +M5 compiled Feb 7 2011 02:13:30 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:13:38 +M5 executing on burrito +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt index 6c8846c5d..b8651e274 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 255958 # Simulator instruction rate (inst/s) -host_mem_usage 207264 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 701295215 # Simulator tick rate (ticks/s) +host_inst_rate 286147 # Simulator instruction rate (inst/s) +host_mem_usage 223356 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host +host_tick_rate 784088172 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 15175 # Number of instructions simulated sim_seconds 0.000042 # Number of seconds simulated @@ -197,8 +197,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 83600 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 83600 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 15175 # Number of instructions executed -system.cpu.num_refs 3684 # Number of memory references +system.cpu.num_int_alu_accesses 12231 # Number of integer alu accesses +system.cpu.num_int_insts 12231 # number of integer instructions +system.cpu.num_int_register_reads 29059 # number of times the integer registers were read +system.cpu.num_int_register_writes 13831 # number of times the integer registers were written +system.cpu.num_load_insts 2232 # Number of load instructions +system.cpu.num_mem_refs 3684 # number of memory refs +system.cpu.num_store_insts 1452 # Number of store instructions system.cpu.workload.PROG:num_syscalls 18 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index 26eb3724f..1712ae4de 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -1,24 +1,33 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/chips/pd/randd/dist/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/chips/pd/randd/dist/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=atomic -pal=/chips/pd/randd/dist/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= system_rev=1024 system_type=34 +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.bridge] type=Bridge @@ -265,7 +274,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -285,7 +294,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -411,7 +420,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] @@ -882,7 +891,9 @@ SubsystemID=0 SubsystemVendorID=0 VendorID=32902 config_latency=20000 +ctrl_offset=0 disks=system.disk0 system.disk2 +io_shift=0 max_backoff_delay=10000000 min_backoff_delay=4000 pci_bus=0 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr index 83c71fc5c..0372a3b05 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr @@ -2,4 +2,8 @@ warn: Sockets disabled, not accepting terminal connections For more information see: http://www.m5sim.org/warn/8742226b warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba hack: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout index 41c773ee0..dcb0b4c2e 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simout -Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 2 2010 23:00:12 -M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip -M5 started Nov 2 2010 23:09:56 -M5 executing on aus-bc2-b15 +M5 compiled Feb 7 2011 01:46:17 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:46:32 +M5 executing on burrito command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 97861500 Exiting @ tick 1870335522500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 8f44fff37..55bb5b9bd 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 4418519 # Simulator instruction rate (inst/s) -host_mem_usage 326752 # Number of bytes of host memory used -host_seconds 14.29 # Real time elapsed on the host -host_tick_rate 130854140423 # Simulator tick rate (ticks/s) +host_inst_rate 1669061 # Simulator instruction rate (inst/s) +host_mem_usage 312244 # Number of bytes of host memory used +host_seconds 37.84 # Real time elapsed on the host +host_tick_rate 49429698361 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 63154034 # Number of instructions simulated sim_seconds 1.870336 # Number of seconds simulated @@ -305,8 +305,24 @@ system.cpu0.kern.syscall::147 2 0.88% 100.00% # nu system.cpu0.kern.syscall::total 226 # number of syscalls executed system.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles system.cpu0.numCycles 3740670933 # number of cpu cycles simulated +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.num_busy_cycles 57233843.686322 # Number of busy cycles +system.cpu0.num_conditional_control_insts 6808233 # number of instructions that are conditional controls +system.cpu0.num_fp_alu_accesses 299810 # Number of float alu accesses +system.cpu0.num_fp_insts 299810 # number of float instructions +system.cpu0.num_fp_register_reads 147724 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 150835 # number of times the floating registers were written +system.cpu0.num_func_calls 1399585 # number of times a function call or return occured +system.cpu0.num_idle_cycles 3683437089.313678 # Number of idle cycles system.cpu0.num_insts 57222076 # Number of instructions executed -system.cpu0.num_refs 15135515 # Number of memory references +system.cpu0.num_int_alu_accesses 53249924 # Number of integer alu accesses +system.cpu0.num_int_insts 53249924 # number of integer instructions +system.cpu0.num_int_register_reads 73318596 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39827534 # number of times the integer registers were written +system.cpu0.num_load_insts 9184477 # Number of load instructions +system.cpu0.num_mem_refs 15135515 # number of memory refs +system.cpu0.num_store_insts 5951038 # Number of store instructions system.cpu1.dcache.LoadLockedReq_accesses::0 16418 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_hits::0 15129 # number of LoadLockedReq hits @@ -587,8 +603,24 @@ system.cpu1.kern.syscall::132 2 2.00% 100.00% # nu system.cpu1.kern.syscall::total 100 # number of syscalls executed system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles system.cpu1.numCycles 3740248881 # number of cpu cycles simulated +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.num_busy_cycles 5936690.922345 # Number of busy cycles +system.cpu1.num_conditional_control_insts 577190 # number of instructions that are conditional controls +system.cpu1.num_fp_alu_accesses 28590 # Number of float alu accesses +system.cpu1.num_fp_insts 28590 # number of float instructions +system.cpu1.num_fp_register_reads 17889 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 17683 # number of times the floating registers were written +system.cpu1.num_func_calls 182742 # number of times a function call or return occured +system.cpu1.num_idle_cycles 3734312190.077655 # Number of idle cycles system.cpu1.num_insts 5931958 # Number of instructions executed -system.cpu1.num_refs 1926244 # Number of memory references +system.cpu1.num_int_alu_accesses 5550578 # Number of integer alu accesses +system.cpu1.num_int_insts 5550578 # number of integer instructions +system.cpu1.num_int_register_reads 7657288 # number of times the integer registers were read +system.cpu1.num_int_register_writes 4163275 # number of times the integer registers were written +system.cpu1.num_load_insts 1170888 # Number of load instructions +system.cpu1.num_mem_refs 1926244 # number of memory refs +system.cpu1.num_store_insts 755356 # Number of store instructions system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index c5b353159..6d9c221c4 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -1,24 +1,33 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/chips/pd/randd/dist/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/chips/pd/randd/dist/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=atomic -pal=/chips/pd/randd/dist/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= system_rev=1024 system_type=34 +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.bridge] type=Bridge @@ -158,7 +167,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -178,7 +187,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -304,7 +313,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] @@ -775,7 +784,9 @@ SubsystemID=0 SubsystemVendorID=0 VendorID=32902 config_latency=20000 +ctrl_offset=0 disks=system.disk0 system.disk2 +io_shift=0 max_backoff_delay=10000000 min_backoff_delay=4000 pci_bus=0 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr index 83c71fc5c..0372a3b05 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr @@ -2,4 +2,8 @@ warn: Sockets disabled, not accepting terminal connections For more information see: http://www.m5sim.org/warn/8742226b warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba hack: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout index 85e98e7a4..644d4ca07 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic/simout -Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 2 2010 23:00:12 -M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip -M5 started Nov 2 2010 23:09:41 -M5 executing on aus-bc2-b15 +M5 compiled Feb 7 2011 01:46:17 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:46:32 +M5 executing on burrito command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1829332258000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index e2b7c8ed7..3b6776214 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 4413707 # Simulator instruction rate (inst/s) -host_mem_usage 325356 # Number of bytes of host memory used -host_seconds 13.60 # Real time elapsed on the host -host_tick_rate 134480396261 # Simulator tick rate (ticks/s) +host_inst_rate 1616180 # Simulator instruction rate (inst/s) +host_mem_usage 311108 # Number of bytes of host memory used +host_seconds 37.15 # Real time elapsed on the host +host_tick_rate 49243802130 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 60038305 # Number of instructions simulated sim_seconds 1.829332 # Number of seconds simulated @@ -297,8 +297,24 @@ system.cpu.kern.syscall::147 2 0.61% 100.00% # nu system.cpu.kern.syscall::total 326 # number of syscalls executed system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles system.cpu.numCycles 3658664408 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 60055428.819193 # Number of busy cycles +system.cpu.num_conditional_control_insts 7110746 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses +system.cpu.num_fp_insts 324460 # number of float instructions +system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written +system.cpu.num_func_calls 1484182 # number of times a function call or return occured +system.cpu.num_idle_cycles 3598608979.180807 # Number of idle cycles system.cpu.num_insts 60038305 # Number of instructions executed -system.cpu.num_refs 16115709 # Number of memory references +system.cpu.num_int_alu_accesses 55913521 # Number of integer alu accesses +system.cpu.num_int_insts 55913521 # number of integer instructions +system.cpu.num_int_register_reads 76953934 # number of times the integer registers were read +system.cpu.num_int_register_writes 41740225 # number of times the integer registers were written +system.cpu.num_load_insts 9747513 # Number of load instructions +system.cpu.num_mem_refs 16115709 # number of memory refs +system.cpu.num_store_insts 6368196 # Number of store instructions system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index ef977d929..41a7379e1 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -1,24 +1,33 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/chips/pd/randd/dist/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/chips/pd/randd/dist/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing -pal=/chips/pd/randd/dist/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= system_rev=1024 system_type=34 +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.bridge] type=Bridge @@ -259,7 +268,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -279,7 +288,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -405,7 +414,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] @@ -876,7 +885,9 @@ SubsystemID=0 SubsystemVendorID=0 VendorID=32902 config_latency=20000 +ctrl_offset=0 disks=system.disk0 system.disk2 +io_shift=0 max_backoff_delay=10000000 min_backoff_delay=4000 pci_bus=0 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr index 83c71fc5c..0372a3b05 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr @@ -2,4 +2,8 @@ warn: Sockets disabled, not accepting terminal connections For more information see: http://www.m5sim.org/warn/8742226b warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba hack: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout index 8585e8d27..8f8e92a25 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simout -Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 2 2010 23:00:12 -M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip -M5 started Nov 2 2010 23:10:42 -M5 executing on aus-bc2-b15 +M5 compiled Feb 7 2011 01:46:17 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:46:32 +M5 executing on burrito command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 562628000 Exiting @ tick 1958647095000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 0517b4d72..6e0648c43 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1781653 # Simulator instruction rate (inst/s) -host_mem_usage 323564 # Number of bytes of host memory used -host_seconds 33.32 # Real time elapsed on the host -host_tick_rate 58791386546 # Simulator tick rate (ticks/s) +host_inst_rate 901052 # Simulator instruction rate (inst/s) +host_mem_usage 309020 # Number of bytes of host memory used +host_seconds 65.87 # Real time elapsed on the host +host_tick_rate 29733229075 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 59355643 # Number of instructions simulated sim_seconds 1.958647 # Number of seconds simulated @@ -360,8 +360,24 @@ system.cpu0.kern.syscall::147 2 0.90% 100.00% # nu system.cpu0.kern.syscall::total 222 # number of syscalls executed system.cpu0.not_idle_fraction 0.060263 # Percentage of non-idle cycles system.cpu0.numCycles 3916023774 # number of cpu cycles simulated +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.num_busy_cycles 235989726.444158 # Number of busy cycles +system.cpu0.num_conditional_control_insts 6237040 # number of instructions that are conditional controls +system.cpu0.num_fp_alu_accesses 293967 # Number of float alu accesses +system.cpu0.num_fp_insts 293967 # number of float instructions +system.cpu0.num_fp_register_reads 143353 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 146452 # number of times the floating registers were written +system.cpu0.num_func_calls 1426863 # number of times a function call or return occured +system.cpu0.num_idle_cycles 3680034047.555842 # Number of idle cycles system.cpu0.num_insts 54072652 # Number of instructions executed -system.cpu0.num_refs 14724357 # Number of memory references +system.cpu0.num_int_alu_accesses 50043234 # Number of integer alu accesses +system.cpu0.num_int_insts 50043234 # number of integer instructions +system.cpu0.num_int_register_reads 68528072 # number of times the integer registers were read +system.cpu0.num_int_register_writes 37080372 # number of times the integer registers were written +system.cpu0.num_load_insts 8664914 # Number of load instructions +system.cpu0.num_mem_refs 14724357 # number of memory refs +system.cpu0.num_store_insts 6059443 # Number of store instructions system.cpu1.dcache.LoadLockedReq_accesses::0 12766 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 12766 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13318.737271 # average LoadLockedReq miss latency @@ -691,8 +707,24 @@ system.cpu1.kern.syscall::132 3 2.88% 100.00% # nu system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.not_idle_fraction 0.004865 # Percentage of non-idle cycles system.cpu1.numCycles 3917294190 # number of cpu cycles simulated +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.num_busy_cycles 19057169.001990 # Number of busy cycles +system.cpu1.num_conditional_control_insts 510974 # number of instructions that are conditional controls +system.cpu1.num_fp_alu_accesses 34031 # Number of float alu accesses +system.cpu1.num_fp_insts 34031 # number of float instructions +system.cpu1.num_fp_register_reads 22062 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 21862 # number of times the floating registers were written +system.cpu1.num_func_calls 158031 # number of times a function call or return occured +system.cpu1.num_idle_cycles 3898237020.998010 # Number of idle cycles system.cpu1.num_insts 5282991 # Number of instructions executed -system.cpu1.num_refs 1710778 # Number of memory references +system.cpu1.num_int_alu_accesses 4948310 # Number of integer alu accesses +system.cpu1.num_int_insts 4948310 # number of integer instructions +system.cpu1.num_int_register_reads 6886066 # number of times the integer registers were read +system.cpu1.num_int_register_writes 3732878 # number of times the integer registers were written +system.cpu1.num_load_insts 1056124 # Number of load instructions +system.cpu1.num_mem_refs 1710778 # number of memory refs +system.cpu1.num_store_insts 654654 # Number of store instructions system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index 14aa8c52d..f28d4e037 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -1,24 +1,33 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/chips/pd/randd/dist/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/chips/pd/randd/dist/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing -pal=/chips/pd/randd/dist/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= system_rev=1024 system_type=34 +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.bridge] type=Bridge @@ -155,7 +164,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -175,7 +184,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -301,7 +310,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] @@ -772,7 +781,9 @@ SubsystemID=0 SubsystemVendorID=0 VendorID=32902 config_latency=20000 +ctrl_offset=0 disks=system.disk0 system.disk2 +io_shift=0 max_backoff_delay=10000000 min_backoff_delay=4000 pci_bus=0 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr index 83c71fc5c..0372a3b05 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr @@ -2,4 +2,8 @@ warn: Sockets disabled, not accepting terminal connections For more information see: http://www.m5sim.org/warn/8742226b warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba hack: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout index af718c31f..be2bcef8d 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing/simout -Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 2 2010 23:00:12 -M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip -M5 started Nov 2 2010 23:10:12 -M5 executing on aus-bc2-b15 +M5 compiled Feb 7 2011 01:46:17 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:46:32 +M5 executing on burrito command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1915548867000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 37bf681b4..5f1750494 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1917155 # Simulator instruction rate (inst/s) -host_mem_usage 322176 # Number of bytes of host memory used -host_seconds 29.28 # Real time elapsed on the host -host_tick_rate 65417896896 # Simulator tick rate (ticks/s) +host_inst_rate 1077887 # Simulator instruction rate (inst/s) +host_mem_usage 307624 # Number of bytes of host memory used +host_seconds 52.08 # Real time elapsed on the host +host_tick_rate 36780244064 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 56137087 # Number of instructions simulated sim_seconds 1.915549 # Number of seconds simulated @@ -341,8 +341,24 @@ system.cpu.kern.syscall::147 2 0.61% 100.00% # nu system.cpu.kern.syscall::total 326 # number of syscalls executed system.cpu.not_idle_fraction 0.063469 # Percentage of non-idle cycles system.cpu.numCycles 3831097734 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 243154546.001873 # Number of busy cycles +system.cpu.num_conditional_control_insts 6464616 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 324192 # Number of float alu accesses +system.cpu.num_fp_insts 324192 # number of float instructions +system.cpu.num_fp_register_reads 163510 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166384 # number of times the floating registers were written +system.cpu.num_func_calls 1482242 # number of times a function call or return occured +system.cpu.num_idle_cycles 3587943187.998127 # Number of idle cycles system.cpu.num_insts 56137087 # Number of instructions executed -system.cpu.num_refs 15462519 # Number of memory references +system.cpu.num_int_alu_accesses 52011214 # Number of integer alu accesses +system.cpu.num_int_insts 52011214 # number of integer instructions +system.cpu.num_int_register_reads 71259077 # number of times the integer registers were read +system.cpu.num_int_register_writes 38485860 # number of times the integer registers were written +system.cpu.num_load_insts 9094324 # Number of load instructions +system.cpu.num_mem_refs 15462519 # number of memory refs +system.cpu.num_store_insts 6368195 # Number of store instructions system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini index 505488008..79021a958 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem @@ -9,13 +11,20 @@ children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview t boot_cpu_frequency=500 boot_osflags=earlyprintk mem=128MB console=ttyAMA0 lpj=19988480 norandmaps slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0 init_param=0 -kernel=/chips/pd/randd/dist/binaries/vmlinux.arm +kernel=/dist/m5/system/binaries/vmlinux.arm load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic physmem=system.physmem readfile=tests/halt.sh symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.bridge] type=Bridge @@ -158,7 +167,7 @@ type=ExeTracer [system.diskmem] type=PhysicalMemory -file=/chips/pd/randd/dist/disks/ael-arm.ext2 +file=/dist/m5/system/disks/ael-arm.ext2 latency=30000 latency_var=0 null=false diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout index 05fcdedb2..ba4c6742c 100755 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 15 2010 11:17:32 -M5 revision e459beb39dd0 7713 default ext/amba_kmi_pl050.patch qtip tip -M5 started Oct 15 2010 11:17:48 -M5 executing on aus-bc3-b4 -command line: build/ARM_FS/m5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic +M5 compiled Feb 7 2011 01:53:13 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:53:26 +M5 executing on burrito +command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm info: Entering event queue @ 0. Starting simulation... Exiting @ tick 25821310500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 1bfa8bc8a..0a7542a7c 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1831927 # Simulator instruction rate (inst/s) -host_mem_usage 384484 # Number of bytes of host memory used -host_seconds 27.81 # Real time elapsed on the host -host_tick_rate 928414614 # Simulator tick rate (ticks/s) +host_inst_rate 739167 # Simulator instruction rate (inst/s) +host_mem_usage 360776 # Number of bytes of host memory used +host_seconds 68.93 # Real time elapsed on the host +host_tick_rate 374609475 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 50949504 # Number of instructions simulated sim_seconds 0.025821 # Number of seconds simulated @@ -225,8 +225,24 @@ system.cpu.kern.inst.arm 0 # nu system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 51642622 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 51642622 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 6059 # Number of float alu accesses +system.cpu.num_fp_insts 6059 # number of float instructions +system.cpu.num_fp_register_reads 4227 # number of times the floating registers were read +system.cpu.num_fp_register_writes 1834 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 50949504 # Number of instructions executed -system.cpu.num_refs 16092645 # Number of memory references +system.cpu.num_int_alu_accesses 41395090 # Number of integer alu accesses +system.cpu.num_int_insts 41395090 # number of integer instructions +system.cpu.num_int_register_reads 128438705 # number of times the integer registers were read +system.cpu.num_int_register_writes 33973128 # number of times the integer registers were written +system.cpu.num_load_insts 9082722 # Number of load instructions +system.cpu.num_mem_refs 16092645 # number of memory refs +system.cpu.num_store_insts 7009923 # Number of store instructions system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs no_value # Average number of references to valid blocks. diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status index 586cb6b73..53b01d583 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status @@ -1 +1 @@ -build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic FAILED! +build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic FAILED! diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index c7f419728..4fad32362 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem @@ -16,6 +18,13 @@ mem_mode=timing physmem=system.physmem readfile=tests/halt.sh symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.bridge] type=Bridge diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index 8382cb48d..994dfb6a2 100755 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 17 2011 18:36:49 -M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase -M5 started Jan 17 2011 18:36:52 -M5 executing on zizzer +M5 compiled Feb 7 2011 01:53:13 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:53:26 +M5 executing on burrito command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 157177a6b..85fb99220 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1461109 # Simulator instruction rate (inst/s) -host_mem_usage 340352 # Number of bytes of host memory used -host_seconds 34.61 # Real time elapsed on the host -host_tick_rate 3314430509 # Simulator tick rate (ticks/s) +host_inst_rate 433208 # Simulator instruction rate (inst/s) +host_mem_usage 360908 # Number of bytes of host memory used +host_seconds 116.74 # Real time elapsed on the host +host_tick_rate 982709659 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 50572425 # Number of instructions simulated sim_seconds 0.114721 # Number of seconds simulated @@ -273,8 +273,24 @@ system.cpu.kern.inst.arm 0 # nu system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 229442148 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 229442148 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 6058 # Number of float alu accesses +system.cpu.num_fp_insts 6058 # number of float instructions +system.cpu.num_fp_register_reads 4226 # number of times the floating registers were read +system.cpu.num_fp_register_writes 1834 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 50572425 # Number of instructions executed -system.cpu.num_refs 16289993 # Number of memory references +system.cpu.num_int_alu_accesses 41827211 # Number of integer alu accesses +system.cpu.num_int_insts 41827211 # number of integer instructions +system.cpu.num_int_register_reads 137988684 # number of times the integer registers were read +system.cpu.num_int_register_writes 34313952 # number of times the integer registers were written +system.cpu.num_load_insts 9208240 # Number of load instructions +system.cpu.num_mem_refs 16289993 # number of memory refs +system.cpu.num_store_insts 7081753 # Number of store instructions system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs no_value # Average number of references to valid blocks. diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal Binary files differindex 19639b6da..f3053783c 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini index 8b31e35e7..1a56ca25e 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout index d7e9fb267..5ef0286ce 100755 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 9 2010 10:38:04 -M5 revision f4362ffd810f+ 7737+ default tip -M5 started Nov 9 2010 22:11:58 -M5 executing on zizzer +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:49 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt index 4b1bec9b7..e65e62021 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2960881 # Simulator instruction rate (inst/s) -host_mem_usage 193980 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host -host_tick_rate 1478428114 # Simulator tick rate (ticks/s) +host_inst_rate 1417565 # Simulator instruction rate (inst/s) +host_mem_usage 214360 # Number of bytes of host memory used +host_seconds 0.35 # Real time elapsed on the host +host_tick_rate 708232428 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500001 # Number of instructions simulated sim_seconds 0.000250 # Number of seconds simulated @@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 500032 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 500032 # Number of busy cycles +system.cpu.num_conditional_control_insts 38180 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 32 # Number of float alu accesses +system.cpu.num_fp_insts 32 # number of float instructions +system.cpu.num_fp_register_reads 32 # number of times the floating registers were read +system.cpu.num_fp_register_writes 16 # number of times the floating registers were written +system.cpu.num_func_calls 14357 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 500001 # Number of instructions executed -system.cpu.num_refs 180793 # Number of memory references +system.cpu.num_int_alu_accesses 474689 # Number of integer alu accesses +system.cpu.num_int_insts 474689 # number of integer instructions +system.cpu.num_int_register_reads 654286 # number of times the integer registers were read +system.cpu.num_int_register_writes 371542 # number of times the integer registers were written +system.cpu.num_load_insts 124443 # Number of load instructions +system.cpu.num_mem_refs 180793 # number of memory refs +system.cpu.num_store_insts 56350 # Number of store instructions system.cpu.workload.PROG:num_syscalls 18 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini index 380aa38da..466dd444b 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout index 35ea05083..2fab9f5ba 100755 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 9 2010 10:38:04 -M5 revision f4362ffd810f+ 7737+ default tip -M5 started Nov 9 2010 22:11:58 -M5 executing on zizzer +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:48 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt index 8d21cdbb4..3dc7b5670 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1193890 # Simulator instruction rate (inst/s) -host_mem_usage 201748 # Number of bytes of host memory used -host_seconds 0.42 # Real time elapsed on the host -host_tick_rate 1737027103 # Simulator tick rate (ticks/s) +host_inst_rate 663064 # Simulator instruction rate (inst/s) +host_mem_usage 222076 # Number of bytes of host memory used +host_seconds 0.75 # Real time elapsed on the host +host_tick_rate 964960959 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500001 # Number of instructions simulated sim_seconds 0.000728 # Number of seconds simulated @@ -226,8 +226,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1455858 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 1455858 # Number of busy cycles +system.cpu.num_conditional_control_insts 38180 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 32 # Number of float alu accesses +system.cpu.num_fp_insts 32 # number of float instructions +system.cpu.num_fp_register_reads 32 # number of times the floating registers were read +system.cpu.num_fp_register_writes 16 # number of times the floating registers were written +system.cpu.num_func_calls 14357 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 500001 # Number of instructions executed -system.cpu.num_refs 180793 # Number of memory references +system.cpu.num_int_alu_accesses 474689 # Number of integer alu accesses +system.cpu.num_int_insts 474689 # number of integer instructions +system.cpu.num_int_register_reads 654286 # number of times the integer registers were read +system.cpu.num_int_register_writes 371542 # number of times the integer registers were written +system.cpu.num_load_insts 124443 # Number of load instructions +system.cpu.num_mem_refs 180793 # number of memory refs +system.cpu.num_store_insts 56350 # Number of store instructions system.cpu.workload.PROG:num_syscalls 18 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini index f95ff0355..9f134009a 100644 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu0] type=AtomicSimpleCPU diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout index 21b8e7313..174fa89ad 100755 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 9 2010 10:38:04 -M5 revision f4362ffd810f+ 7737+ default tip -M5 started Nov 9 2010 22:11:58 -M5 executing on zizzer +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:48 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt index 81431004c..9f848a332 100644 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2770469 # Simulator instruction rate (inst/s) -host_mem_usage 1126824 # Number of bytes of host memory used -host_seconds 0.72 # Real time elapsed on the host -host_tick_rate 346193150 # Simulator tick rate (ticks/s) +host_inst_rate 1366260 # Simulator instruction rate (inst/s) +host_mem_usage 1147168 # Number of bytes of host memory used +host_seconds 1.46 # Real time elapsed on the host +host_tick_rate 170760827 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2000004 # Number of instructions simulated sim_seconds 0.000250 # Number of seconds simulated @@ -145,8 +145,24 @@ system.cpu0.itb.write_hits 0 # DT system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.numCycles 500032 # number of cpu cycles simulated +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.num_busy_cycles 500032 # Number of busy cycles +system.cpu0.num_conditional_control_insts 38180 # number of instructions that are conditional controls +system.cpu0.num_fp_alu_accesses 32 # Number of float alu accesses +system.cpu0.num_fp_insts 32 # number of float instructions +system.cpu0.num_fp_register_reads 32 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 16 # number of times the floating registers were written +system.cpu0.num_func_calls 14357 # number of times a function call or return occured +system.cpu0.num_idle_cycles 0 # Number of idle cycles system.cpu0.num_insts 500001 # Number of instructions executed -system.cpu0.num_refs 180793 # Number of memory references +system.cpu0.num_int_alu_accesses 474689 # Number of integer alu accesses +system.cpu0.num_int_insts 474689 # number of integer instructions +system.cpu0.num_int_register_reads 654286 # number of times the integer registers were read +system.cpu0.num_int_register_writes 371542 # number of times the integer registers were written +system.cpu0.num_load_insts 124443 # Number of load instructions +system.cpu0.num_mem_refs 180793 # number of memory refs +system.cpu0.num_store_insts 56350 # Number of store instructions system.cpu0.workload.PROG:num_syscalls 18 # Number of system calls system.cpu1.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_hits 124111 # number of ReadReq hits @@ -285,8 +301,24 @@ system.cpu1.itb.write_hits 0 # DT system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu1.numCycles 500032 # number of cpu cycles simulated +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.num_busy_cycles 500032 # Number of busy cycles +system.cpu1.num_conditional_control_insts 38180 # number of instructions that are conditional controls +system.cpu1.num_fp_alu_accesses 32 # Number of float alu accesses +system.cpu1.num_fp_insts 32 # number of float instructions +system.cpu1.num_fp_register_reads 32 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 16 # number of times the floating registers were written +system.cpu1.num_func_calls 14357 # number of times a function call or return occured +system.cpu1.num_idle_cycles 0 # Number of idle cycles system.cpu1.num_insts 500001 # Number of instructions executed -system.cpu1.num_refs 180793 # Number of memory references +system.cpu1.num_int_alu_accesses 474689 # Number of integer alu accesses +system.cpu1.num_int_insts 474689 # number of integer instructions +system.cpu1.num_int_register_reads 654286 # number of times the integer registers were read +system.cpu1.num_int_register_writes 371542 # number of times the integer registers were written +system.cpu1.num_load_insts 124443 # Number of load instructions +system.cpu1.num_mem_refs 180793 # number of memory refs +system.cpu1.num_store_insts 56350 # Number of store instructions system.cpu1.workload.PROG:num_syscalls 18 # Number of system calls system.cpu2.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.ReadReq_hits 124111 # number of ReadReq hits @@ -425,8 +457,24 @@ system.cpu2.itb.write_hits 0 # DT system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu2.numCycles 500032 # number of cpu cycles simulated +system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu2.num_busy_cycles 500032 # Number of busy cycles +system.cpu2.num_conditional_control_insts 38180 # number of instructions that are conditional controls +system.cpu2.num_fp_alu_accesses 32 # Number of float alu accesses +system.cpu2.num_fp_insts 32 # number of float instructions +system.cpu2.num_fp_register_reads 32 # number of times the floating registers were read +system.cpu2.num_fp_register_writes 16 # number of times the floating registers were written +system.cpu2.num_func_calls 14357 # number of times a function call or return occured +system.cpu2.num_idle_cycles 0 # Number of idle cycles system.cpu2.num_insts 500001 # Number of instructions executed -system.cpu2.num_refs 180793 # Number of memory references +system.cpu2.num_int_alu_accesses 474689 # Number of integer alu accesses +system.cpu2.num_int_insts 474689 # number of integer instructions +system.cpu2.num_int_register_reads 654286 # number of times the integer registers were read +system.cpu2.num_int_register_writes 371542 # number of times the integer registers were written +system.cpu2.num_load_insts 124443 # Number of load instructions +system.cpu2.num_mem_refs 180793 # number of memory refs +system.cpu2.num_store_insts 56350 # Number of store instructions system.cpu2.workload.PROG:num_syscalls 18 # Number of system calls system.cpu3.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) system.cpu3.dcache.ReadReq_hits 124111 # number of ReadReq hits @@ -565,8 +613,24 @@ system.cpu3.itb.write_hits 0 # DT system.cpu3.itb.write_misses 0 # DTB write misses system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu3.numCycles 500032 # number of cpu cycles simulated +system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu3.num_busy_cycles 500032 # Number of busy cycles +system.cpu3.num_conditional_control_insts 38180 # number of instructions that are conditional controls +system.cpu3.num_fp_alu_accesses 32 # Number of float alu accesses +system.cpu3.num_fp_insts 32 # number of float instructions +system.cpu3.num_fp_register_reads 32 # number of times the floating registers were read +system.cpu3.num_fp_register_writes 16 # number of times the floating registers were written +system.cpu3.num_func_calls 14357 # number of times a function call or return occured +system.cpu3.num_idle_cycles 0 # Number of idle cycles system.cpu3.num_insts 500001 # Number of instructions executed -system.cpu3.num_refs 180793 # Number of memory references +system.cpu3.num_int_alu_accesses 474689 # Number of integer alu accesses +system.cpu3.num_int_insts 474689 # number of integer instructions +system.cpu3.num_int_register_reads 654286 # number of times the integer registers were read +system.cpu3.num_int_register_writes 371542 # number of times the integer registers were written +system.cpu3.num_load_insts 124443 # Number of load instructions +system.cpu3.num_mem_refs 180793 # number of memory refs +system.cpu3.num_store_insts 56350 # Number of store instructions system.cpu3.workload.PROG:num_syscalls 18 # Number of system calls system.l2c.ReadExReq_accesses::0 139 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::1 139 # number of ReadExReq accesses(hits+misses) diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini index a23113a37..9ec264236 100644 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus mem_mode=timing physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu0] type=TimingSimpleCPU diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr index 98d9eda34..fa3024167 100755 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr @@ -8,8 +8,8 @@ hack: be nice to actually delete the event here gzip: stdout: Broken pipe +gzip: gzip: stdout: Broken pipe - -gzip: stdout: Broken pipe +stdout: Broken pipe gzip: stdout: Broken pipe diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout index 09966aa49..af5204214 100755 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 9 2010 10:38:04 -M5 revision f4362ffd810f+ 7737+ default tip -M5 started Nov 9 2010 22:11:58 -M5 executing on zizzer +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:37 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt index dbaf84851..9dfa01a0d 100644 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1961801 # Simulator instruction rate (inst/s) -host_mem_usage 209312 # Number of bytes of host memory used -host_seconds 1.02 # Real time elapsed on the host -host_tick_rate 714851017 # Simulator tick rate (ticks/s) +host_inst_rate 730494 # Simulator instruction rate (inst/s) +host_mem_usage 229664 # Number of bytes of host memory used +host_seconds 2.74 # Real time elapsed on the host +host_tick_rate 266213751 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1999954 # Number of instructions simulated sim_seconds 0.000729 # Number of seconds simulated @@ -163,8 +163,24 @@ system.cpu0.itb.write_hits 0 # DT system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.numCycles 1457840 # number of cpu cycles simulated +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.num_busy_cycles 1457840 # Number of busy cycles +system.cpu0.num_conditional_control_insts 38180 # number of instructions that are conditional controls +system.cpu0.num_fp_alu_accesses 32 # Number of float alu accesses +system.cpu0.num_fp_insts 32 # number of float instructions +system.cpu0.num_fp_register_reads 32 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 16 # number of times the floating registers were written +system.cpu0.num_func_calls 14357 # number of times a function call or return occured +system.cpu0.num_idle_cycles 0 # Number of idle cycles system.cpu0.num_insts 500001 # Number of instructions executed -system.cpu0.num_refs 180793 # Number of memory references +system.cpu0.num_int_alu_accesses 474689 # Number of integer alu accesses +system.cpu0.num_int_insts 474689 # number of integer instructions +system.cpu0.num_int_register_reads 654286 # number of times the integer registers were read +system.cpu0.num_int_register_writes 371542 # number of times the integer registers were written +system.cpu0.num_load_insts 124443 # Number of load instructions +system.cpu0.num_mem_refs 180793 # number of memory refs +system.cpu0.num_store_insts 56350 # Number of store instructions system.cpu0.workload.PROG:num_syscalls 18 # Number of system calls system.cpu1.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_avg_miss_latency 54891.975309 # average ReadReq miss latency @@ -321,8 +337,24 @@ system.cpu1.itb.write_hits 0 # DT system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu1.numCycles 1457840 # number of cpu cycles simulated +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.num_busy_cycles 1457840 # Number of busy cycles +system.cpu1.num_conditional_control_insts 38179 # number of instructions that are conditional controls +system.cpu1.num_fp_alu_accesses 32 # Number of float alu accesses +system.cpu1.num_fp_insts 32 # number of float instructions +system.cpu1.num_fp_register_reads 32 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 16 # number of times the floating registers were written +system.cpu1.num_func_calls 14357 # number of times a function call or return occured +system.cpu1.num_idle_cycles 0 # Number of idle cycles system.cpu1.num_insts 499993 # Number of instructions executed -system.cpu1.num_refs 180792 # Number of memory references +system.cpu1.num_int_alu_accesses 474681 # Number of integer alu accesses +system.cpu1.num_int_insts 474681 # number of integer instructions +system.cpu1.num_int_register_reads 654273 # number of times the integer registers were read +system.cpu1.num_int_register_writes 371536 # number of times the integer registers were written +system.cpu1.num_load_insts 124443 # Number of load instructions +system.cpu1.num_mem_refs 180792 # number of memory refs +system.cpu1.num_store_insts 56349 # Number of store instructions system.cpu1.workload.PROG:num_syscalls 18 # Number of system calls system.cpu2.dcache.ReadReq_accesses 124433 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.ReadReq_avg_miss_latency 54919.753086 # average ReadReq miss latency @@ -479,8 +511,24 @@ system.cpu2.itb.write_hits 0 # DT system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu2.numCycles 1457840 # number of cpu cycles simulated +system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu2.num_busy_cycles 1457840 # Number of busy cycles +system.cpu2.num_conditional_control_insts 38179 # number of instructions that are conditional controls +system.cpu2.num_fp_alu_accesses 32 # Number of float alu accesses +system.cpu2.num_fp_insts 32 # number of float instructions +system.cpu2.num_fp_register_reads 32 # number of times the floating registers were read +system.cpu2.num_fp_register_writes 16 # number of times the floating registers were written +system.cpu2.num_func_calls 14357 # number of times a function call or return occured +system.cpu2.num_idle_cycles 0 # Number of idle cycles system.cpu2.num_insts 499982 # Number of instructions executed -system.cpu2.num_refs 180789 # Number of memory references +system.cpu2.num_int_alu_accesses 474671 # Number of integer alu accesses +system.cpu2.num_int_insts 474671 # number of integer instructions +system.cpu2.num_int_register_reads 654261 # number of times the integer registers were read +system.cpu2.num_int_register_writes 371526 # number of times the integer registers were written +system.cpu2.num_load_insts 124440 # Number of load instructions +system.cpu2.num_mem_refs 180789 # number of memory refs +system.cpu2.num_store_insts 56349 # Number of store instructions system.cpu2.workload.PROG:num_syscalls 18 # Number of system calls system.cpu3.dcache.ReadReq_accesses 124431 # number of ReadReq accesses(hits+misses) system.cpu3.dcache.ReadReq_avg_miss_latency 54910.493827 # average ReadReq miss latency @@ -637,8 +685,24 @@ system.cpu3.itb.write_hits 0 # DT system.cpu3.itb.write_misses 0 # DTB write misses system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu3.numCycles 1457840 # number of cpu cycles simulated +system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu3.num_busy_cycles 1457840 # Number of busy cycles +system.cpu3.num_conditional_control_insts 38178 # number of instructions that are conditional controls +system.cpu3.num_fp_alu_accesses 32 # Number of float alu accesses +system.cpu3.num_fp_insts 32 # number of float instructions +system.cpu3.num_fp_register_reads 32 # number of times the floating registers were read +system.cpu3.num_fp_register_writes 16 # number of times the floating registers were written +system.cpu3.num_func_calls 14357 # number of times a function call or return occured +system.cpu3.num_idle_cycles 0 # Number of idle cycles system.cpu3.num_insts 499978 # Number of instructions executed -system.cpu3.num_refs 180787 # Number of memory references +system.cpu3.num_int_alu_accesses 474667 # Number of integer alu accesses +system.cpu3.num_int_insts 474667 # number of integer instructions +system.cpu3.num_int_register_reads 654256 # number of times the integer registers were read +system.cpu3.num_int_register_writes 371523 # number of times the integer registers were written +system.cpu3.num_load_insts 124438 # Number of load instructions +system.cpu3.num_mem_refs 180787 # number of memory refs +system.cpu3.num_store_insts 56349 # Number of store instructions system.cpu3.workload.PROG:num_syscalls 18 # Number of system calls system.l2c.ReadExReq_accesses::0 139 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::1 139 # number of ReadExReq accesses(hits+misses) diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini index 17847f641..08b40bb1a 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus mem_mode=timing physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu0] type=DerivO3CPU diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index ac49cfc17..d3d241630 100755 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 17 2011 21:17:52 -M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase -M5 started Jan 17 2011 21:19:18 -M5 executing on zizzer +M5 compiled Feb 7 2011 02:13:30 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:13:39 +M5 executing on burrito command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 1034fcecd..acba85fd7 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 133732 # Simulator instruction rate (inst/s) -host_mem_usage 214280 # Number of bytes of host memory used -host_seconds 8.62 # Real time elapsed on the host -host_tick_rate 13623692 # Simulator tick rate (ticks/s) +host_inst_rate 67069 # Simulator instruction rate (inst/s) +host_mem_usage 234672 # Number of bytes of host memory used +host_seconds 17.20 # Real time elapsed on the host +host_tick_rate 6832636 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1153323 # Number of instructions simulated sim_seconds 0.000117 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu0.commit.COM:committed_per_cycle::min_value 0 system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::total 214839 # Number of insts commited each cycle system.cpu0.commit.COM:count 534547 # Number of instructions committed +system.cpu0.commit.COM:fp_insts 0 # Number of committed floating point instructions. +system.cpu0.commit.COM:function_calls 0 # Number of function calls committed. +system.cpu0.commit.COM:int_insts 359798 # Number of committed integer instructions. system.cpu0.commit.COM:loads 174318 # Number of loads committed system.cpu0.commit.COM:membars 84 # Number of memory barriers committed system.cpu0.commit.COM:refs 261983 # Number of memory references committed @@ -162,6 +165,7 @@ system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::total 216884 # Number of instructions fetched each cycle (Total) +system.cpu0.fp_regfile_reads 192 # number of floating regfile reads system.cpu0.icache.ReadReq_accesses 5264 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_avg_miss_latency 39056.216931 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_mshr_miss_latency 37012.315271 # average ReadReq mshr miss latency @@ -261,6 +265,8 @@ system.cpu0.iew.lsq.thread.0.squashedStores 1081 # system.cpu0.iew.memOrderViolationEvents 74 # Number of memory order violations system.cpu0.iew.predictedNotTakenIncorrect 821 # Number of branches that were predicted not taken incorrectly system.cpu0.iew.predictedTakenIncorrect 425 # Number of branches that were predicted taken incorrectly +system.cpu0.int_regfile_reads 812944 # number of integer regfile reads +system.cpu0.int_regfile_writes 365773 # number of integer regfile writes system.cpu0.ipc 1.907193 # IPC: Instructions Per Cycle system.cpu0.ipc_total 1.907193 # IPC: Total IPC of All Threads system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -352,6 +358,14 @@ system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::total 216884 # Number of insts issued each cycle system.cpu0.iq.ISSUE:rate 1.936032 # Inst issue rate +system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu0.iq.int_alu_accesses 455183 # Number of integer alu accesses +system.cpu0.iq.int_inst_queue_reads 1127113 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_wakeup_accesses 453412 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.int_inst_queue_writes 465644 # Number of integer instruction queue writes system.cpu0.iq.iqInstsAdded 456518 # Number of instructions added to the IQ (excludes non-spec) system.cpu0.iq.iqInstsIssued 454956 # Number of instructions issued system.cpu0.iq.iqNonSpecInstsAdded 825 # Number of non-speculative instructions added to the IQ @@ -363,7 +377,11 @@ system.cpu0.memDep0.conflictingLoads 86252 # Nu system.cpu0.memDep0.conflictingStores 86102 # Number of conflicting stores. system.cpu0.memDep0.insertedLoads 176000 # Number of loads inserted to the mem dependence unit. system.cpu0.memDep0.insertedStores 88746 # Number of stores inserted to the mem dependence unit. +system.cpu0.misc_regfile_reads 265411 # number of misc regfile reads +system.cpu0.misc_regfile_writes 564 # number of misc regfile writes system.cpu0.numCycles 234994 # number of cpu cycles simulated +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.rename.RENAME:BlockCycles 1211 # Number of cycles rename is blocking system.cpu0.rename.RENAME:CommittedMaps 361468 # Number of HB maps that are committed system.cpu0.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full @@ -376,10 +394,13 @@ system.cpu0.rename.RENAME:RunCycles 180641 # Nu system.cpu0.rename.RENAME:SquashCycles 2062 # Number of cycles rename is squashing system.cpu0.rename.RENAME:UnblockCycles 697 # Number of cycles rename is unblocking system.cpu0.rename.RENAME:UndoneMaps 10322 # Number of HB maps that are undone due to squashing +system.cpu0.rename.RENAME:int_rename_lookups 1089130 # Number of integer rename lookups system.cpu0.rename.RENAME:serializeStallCycles 11540 # count of cycles rename stalled for serializing inst system.cpu0.rename.RENAME:serializingInsts 809 # count of serializing insts renamed system.cpu0.rename.RENAME:skidInsts 4202 # count of insts added to the skid buffer system.cpu0.rename.RENAME:tempSerializingInsts 812 # count of temporary serializing insts renamed +system.cpu0.rob.rob_reads 757548 # The number of ROB reads +system.cpu0.rob.rob_writes 1090250 # The number of ROB writes system.cpu0.timesIdled 337 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu0.workload.PROG:num_syscalls 89 # Number of system calls system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. @@ -411,6 +432,9 @@ system.cpu1.commit.COM:committed_per_cycle::min_value 0 system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::total 187667 # Number of insts commited each cycle system.cpu1.commit.COM:count 221435 # Number of instructions committed +system.cpu1.commit.COM:fp_insts 0 # Number of committed floating point instructions. +system.cpu1.commit.COM:function_calls 0 # Number of function calls committed. +system.cpu1.commit.COM:int_insts 150322 # Number of committed integer instructions. system.cpu1.commit.COM:loads 60856 # Number of loads committed system.cpu1.commit.COM:membars 9088 # Number of memory barriers committed system.cpu1.commit.COM:refs 87006 # Number of memory references committed @@ -536,6 +560,7 @@ system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::total 196087 # Number of instructions fetched each cycle (Total) +system.cpu1.fp_regfile_writes 64 # number of floating regfile writes system.cpu1.icache.ReadReq_accesses 27242 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_avg_miss_latency 15144.329897 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12327.702703 # average ReadReq mshr miss latency @@ -635,6 +660,8 @@ system.cpu1.iew.lsq.thread.0.squashedStores 732 # system.cpu1.iew.memOrderViolationEvents 35 # Number of memory order violations system.cpu1.iew.predictedNotTakenIncorrect 189 # Number of branches that were predicted not taken incorrectly system.cpu1.iew.predictedTakenIncorrect 1010 # Number of branches that were predicted taken incorrectly +system.cpu1.int_regfile_reads 321648 # number of integer regfile reads +system.cpu1.int_regfile_writes 150288 # number of integer regfile writes system.cpu1.ipc 0.902137 # IPC: Instructions Per Cycle system.cpu1.ipc_total 0.902137 # IPC: Total IPC of All Threads system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -726,6 +753,14 @@ system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::total 196087 # Number of insts issued each cycle system.cpu1.iq.ISSUE:rate 0.970635 # Inst issue rate +system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu1.iq.int_alu_accesses 194246 # Number of integer alu accesses +system.cpu1.iq.int_inst_queue_reads 584396 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_wakeup_accesses 192754 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.int_inst_queue_writes 203505 # Number of integer instruction queue writes system.cpu1.iq.iqInstsAdded 186439 # Number of instructions added to the IQ (excludes non-spec) system.cpu1.iq.iqInstsIssued 194061 # Number of instructions issued system.cpu1.iq.iqNonSpecInstsAdded 10484 # Number of non-speculative instructions added to the IQ @@ -737,7 +772,11 @@ system.cpu1.memDep0.conflictingLoads 31889 # Nu system.cpu1.memDep0.conflictingStores 22377 # Number of conflicting stores. system.cpu1.memDep0.insertedLoads 62331 # Number of loads inserted to the mem dependence unit. system.cpu1.memDep0.insertedStores 26882 # Number of stores inserted to the mem dependence unit. +system.cpu1.misc_regfile_reads 89554 # number of misc regfile reads +system.cpu1.misc_regfile_writes 646 # number of misc regfile writes system.cpu1.numCycles 199932 # number of cpu cycles simulated +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.rename.RENAME:BlockCycles 9891 # Number of cycles rename is blocking system.cpu1.rename.RENAME:CommittedMaps 147748 # Number of HB maps that are committed system.cpu1.rename.RENAME:IQFullEvents 48 # Number of times rename has blocked due to IQ full @@ -750,10 +789,13 @@ system.cpu1.rename.RENAME:RunCycles 92302 # Nu system.cpu1.rename.RENAME:SquashCycles 1784 # Number of cycles rename is squashing system.cpu1.rename.RENAME:UnblockCycles 562 # Number of cycles rename is unblocking system.cpu1.rename.RENAME:UndoneMaps 8137 # Number of HB maps that are undone due to squashing +system.cpu1.rename.RENAME:int_rename_lookups 422855 # Number of integer rename lookups system.cpu1.rename.RENAME:serializeStallCycles 13360 # count of cycles rename stalled for serializing inst system.cpu1.rename.RENAME:serializingInsts 970 # count of serializing insts renamed system.cpu1.rename.RENAME:skidInsts 2743 # count of insts added to the skid buffer system.cpu1.rename.RENAME:tempSerializingInsts 1022 # count of temporary serializing insts renamed +system.cpu1.rob.rob_reads 416274 # The number of ROB reads +system.cpu1.rob.rob_writes 461144 # The number of ROB writes system.cpu1.timesIdled 297 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu2.BPredUnit.BTBHits 58194 # Number of BTB hits @@ -784,6 +826,9 @@ system.cpu2.commit.COM:committed_per_cycle::min_value 0 system.cpu2.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu2.commit.COM:committed_per_cycle::total 185916 # Number of insts commited each cycle system.cpu2.commit.COM:count 330777 # Number of instructions committed +system.cpu2.commit.COM:fp_insts 0 # Number of committed floating point instructions. +system.cpu2.commit.COM:function_calls 0 # Number of function calls committed. +system.cpu2.commit.COM:int_insts 226484 # Number of committed integer instructions. system.cpu2.commit.COM:loads 98945 # Number of loads committed system.cpu2.commit.COM:membars 4183 # Number of memory barriers committed system.cpu2.commit.COM:refs 146579 # Number of memory references committed @@ -909,6 +954,7 @@ system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::total 194280 # Number of instructions fetched each cycle (Total) +system.cpu2.fp_regfile_writes 64 # number of floating regfile writes system.cpu2.icache.ReadReq_accesses 17027 # number of ReadReq accesses(hits+misses) system.cpu2.icache.ReadReq_avg_miss_latency 21608.921162 # average ReadReq miss latency system.cpu2.icache.ReadReq_avg_mshr_miss_latency 18272.935780 # average ReadReq mshr miss latency @@ -1008,6 +1054,8 @@ system.cpu2.iew.lsq.thread.0.squashedStores 766 # system.cpu2.iew.memOrderViolationEvents 35 # Number of memory order violations system.cpu2.iew.predictedNotTakenIncorrect 199 # Number of branches that were predicted not taken incorrectly system.cpu2.iew.predictedTakenIncorrect 991 # Number of branches that were predicted taken incorrectly +system.cpu2.int_regfile_reads 500577 # number of integer regfile reads +system.cpu2.int_regfile_writes 231428 # number of integer regfile writes system.cpu2.ipc 1.392607 # IPC: Instructions Per Cycle system.cpu2.ipc_total 1.392607 # IPC: Total IPC of All Threads system.cpu2.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -1099,6 +1147,14 @@ system.cpu2.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu2.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::total 194280 # Number of insts issued each cycle system.cpu2.iq.ISSUE:rate 1.437167 # Inst issue rate +system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu2.iq.int_alu_accesses 287114 # Number of integer alu accesses +system.cpu2.iq.int_inst_queue_reads 768311 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_wakeup_accesses 285574 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.int_inst_queue_writes 296099 # Number of integer instruction queue writes system.cpu2.iq.iqInstsAdded 284164 # Number of instructions added to the IQ (excludes non-spec) system.cpu2.iq.iqInstsIssued 286916 # Number of instructions issued system.cpu2.iq.iqNonSpecInstsAdded 5428 # Number of non-speculative instructions added to the IQ @@ -1110,7 +1166,11 @@ system.cpu2.memDep0.conflictingLoads 48437 # Nu system.cpu2.memDep0.conflictingStores 43927 # Number of conflicting stores. system.cpu2.memDep0.insertedLoads 100435 # Number of loads inserted to the mem dependence unit. system.cpu2.memDep0.insertedStores 48400 # Number of stores inserted to the mem dependence unit. +system.cpu2.misc_regfile_reads 149234 # number of misc regfile reads +system.cpu2.misc_regfile_writes 646 # number of misc regfile writes system.cpu2.numCycles 199640 # number of cpu cycles simulated +system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.rename.RENAME:BlockCycles 5634 # Number of cycles rename is blocking system.cpu2.rename.RENAME:CommittedMaps 228819 # Number of HB maps that are committed system.cpu2.rename.RENAME:IQFullEvents 67 # Number of times rename has blocked due to IQ full @@ -1123,10 +1183,13 @@ system.cpu2.rename.RENAME:RunCycles 120203 # Nu system.cpu2.rename.RENAME:SquashCycles 1740 # Number of cycles rename is squashing system.cpu2.rename.RENAME:UnblockCycles 620 # Number of cycles rename is unblocking system.cpu2.rename.RENAME:UndoneMaps 8187 # Number of HB maps that are undone due to squashing +system.cpu2.rename.RENAME:int_rename_lookups 661216 # Number of integer rename lookups system.cpu2.rename.RENAME:serializeStallCycles 12791 # count of cycles rename stalled for serializing inst system.cpu2.rename.RENAME:serializingInsts 940 # count of serializing insts renamed system.cpu2.rename.RENAME:skidInsts 2775 # count of insts added to the skid buffer system.cpu2.rename.RENAME:tempSerializingInsts 995 # count of temporary serializing insts renamed +system.cpu2.rob.rob_reads 523697 # The number of ROB reads +system.cpu2.rob.rob_writes 679481 # The number of ROB writes system.cpu2.timesIdled 296 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu3.BPredUnit.BTBHits 53101 # Number of BTB hits @@ -1157,6 +1220,9 @@ system.cpu3.commit.COM:committed_per_cycle::min_value 0 system.cpu3.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu3.commit.COM:committed_per_cycle::total 187872 # Number of insts commited each cycle system.cpu3.commit.COM:count 296008 # Number of instructions committed +system.cpu3.commit.COM:fp_insts 0 # Number of committed floating point instructions. +system.cpu3.commit.COM:function_calls 0 # Number of function calls committed. +system.cpu3.commit.COM:int_insts 202157 # Number of committed integer instructions. system.cpu3.commit.COM:loads 86777 # Number of loads committed system.cpu3.commit.COM:membars 5899 # Number of memory barriers committed system.cpu3.commit.COM:refs 127476 # Number of memory references committed @@ -1282,6 +1348,7 @@ system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::total 196296 # Number of instructions fetched each cycle (Total) +system.cpu3.fp_regfile_writes 64 # number of floating regfile writes system.cpu3.icache.ReadReq_accesses 20572 # number of ReadReq accesses(hits+misses) system.cpu3.icache.ReadReq_avg_miss_latency 14541.928721 # average ReadReq miss latency system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11822.799097 # average ReadReq mshr miss latency @@ -1381,6 +1448,8 @@ system.cpu3.iew.lsq.thread.0.squashedStores 782 # system.cpu3.iew.memOrderViolationEvents 34 # Number of memory order violations system.cpu3.iew.predictedNotTakenIncorrect 194 # Number of branches that were predicted not taken incorrectly system.cpu3.iew.predictedTakenIncorrect 1002 # Number of branches that were predicted taken incorrectly +system.cpu3.int_regfile_reads 443221 # number of integer regfile reads +system.cpu3.int_regfile_writes 205359 # number of integer regfile writes system.cpu3.ipc 1.237689 # IPC: Instructions Per Cycle system.cpu3.ipc_total 1.237689 # IPC: Total IPC of All Threads system.cpu3.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -1472,6 +1541,14 @@ system.cpu3.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu3.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::total 196296 # Number of insts issued each cycle system.cpu3.iq.ISSUE:rate 1.290801 # Inst issue rate +system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu3.iq.int_alu_accesses 257546 # Number of integer alu accesses +system.cpu3.iq.int_inst_queue_reads 711191 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_wakeup_accesses 256019 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.int_inst_queue_writes 266954 # Number of integer instruction queue writes system.cpu3.iq.iqInstsAdded 253019 # Number of instructions added to the IQ (excludes non-spec) system.cpu3.iq.iqInstsIssued 257347 # Number of instructions issued system.cpu3.iq.iqNonSpecInstsAdded 7241 # Number of non-speculative instructions added to the IQ @@ -1483,7 +1560,11 @@ system.cpu3.memDep0.conflictingLoads 43278 # Nu system.cpu3.memDep0.conflictingStores 36990 # Number of conflicting stores. system.cpu3.memDep0.insertedLoads 88323 # Number of loads inserted to the mem dependence unit. system.cpu3.memDep0.insertedStores 41481 # Number of stores inserted to the mem dependence unit. +system.cpu3.misc_regfile_reads 130106 # number of misc regfile reads +system.cpu3.misc_regfile_writes 646 # number of misc regfile writes system.cpu3.numCycles 199370 # number of cpu cycles simulated +system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.rename.RENAME:BlockCycles 7226 # Number of cycles rename is blocking system.cpu3.rename.RENAME:CommittedMaps 202775 # Number of HB maps that are committed system.cpu3.rename.RENAME:IQFullEvents 58 # Number of times rename has blocked due to IQ full @@ -1496,10 +1577,13 @@ system.cpu3.rename.RENAME:RunCycles 111693 # Nu system.cpu3.rename.RENAME:SquashCycles 1792 # Number of cycles rename is squashing system.cpu3.rename.RENAME:UnblockCycles 593 # Number of cycles rename is unblocking system.cpu3.rename.RENAME:UndoneMaps 8286 # Number of HB maps that are undone due to squashing +system.cpu3.rename.RENAME:int_rename_lookups 585183 # Number of integer rename lookups system.cpu3.rename.RENAME:serializeStallCycles 13124 # count of cycles rename stalled for serializing inst system.cpu3.rename.RENAME:serializingInsts 957 # count of serializing insts renamed system.cpu3.rename.RENAME:skidInsts 2808 # count of insts added to the skid buffer system.cpu3.rename.RENAME:tempSerializingInsts 1009 # count of temporary serializing insts renamed +system.cpu3.rob.rob_reads 491204 # The number of ROB reads +system.cpu3.rob.rob_writes 610604 # The number of ROB writes system.cpu3.timesIdled 290 # Number of times that the entire CPU went into an idle state and unscheduled itself system.l2c.ReadExReq_accesses::0 94 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::1 12 # number of ReadExReq accesses(hits+misses) diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini index e833b46ac..01c43d58b 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu0] type=AtomicSimpleCPU diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout index 9ac3c5e14..2f8db50d8 100755 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp/simout -Redirecting stderr to build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 13:03:41 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 13:04:32 -M5 executing on zizzer -command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp +M5 compiled Feb 7 2011 02:13:30 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:13:36 +M5 executing on burrito +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 0544aca9b..2fa9a2da1 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1027581 # Simulator instruction rate (inst/s) -host_mem_usage 1133204 # Number of bytes of host memory used -host_seconds 0.66 # Real time elapsed on the host -host_tick_rate 133016942 # Simulator tick rate (ticks/s) +host_inst_rate 813548 # Simulator instruction rate (inst/s) +host_mem_usage 1149396 # Number of bytes of host memory used +host_seconds 0.83 # Real time elapsed on the host +host_tick_rate 105315075 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 677340 # Number of instructions simulated sim_seconds 0.000088 # Number of seconds simulated @@ -117,8 +117,24 @@ system.cpu0.icache.writebacks 0 # nu system.cpu0.idle_fraction 0 # Percentage of idle cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.numCycles 175428 # number of cpu cycles simulated +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.num_busy_cycles 175428 # Number of busy cycles +system.cpu0.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu0.num_fp_insts 0 # number of float instructions +system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu0.num_func_calls 0 # number of times a function call or return occured +system.cpu0.num_idle_cycles 0 # Number of idle cycles system.cpu0.num_insts 175339 # Number of instructions executed -system.cpu0.num_refs 82398 # Number of memory references +system.cpu0.num_int_alu_accesses 120388 # Number of integer alu accesses +system.cpu0.num_int_insts 120388 # number of integer instructions +system.cpu0.num_int_register_reads 349308 # number of times the integer registers were read +system.cpu0.num_int_register_writes 121996 # number of times the integer registers were written +system.cpu0.num_load_insts 54592 # Number of load instructions +system.cpu0.num_mem_refs 82398 # number of memory refs +system.cpu0.num_store_insts 27806 # Number of store instructions system.cpu0.workload.PROG:num_syscalls 89 # Number of system calls system.cpu1.dcache.ReadReq_accesses 40644 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_hits 40468 # number of ReadReq hits @@ -229,8 +245,24 @@ system.cpu1.icache.writebacks 0 # nu system.cpu1.idle_fraction 0.045506 # Percentage of idle cycles system.cpu1.not_idle_fraction 0.954494 # Percentage of non-idle cycles system.cpu1.numCycles 173308 # number of cpu cycles simulated +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.num_busy_cycles 165421.425557 # Number of busy cycles +system.cpu1.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu1.num_fp_insts 0 # number of float instructions +system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu1.num_func_calls 0 # number of times a function call or return occured +system.cpu1.num_idle_cycles 7886.574443 # Number of idle cycles system.cpu1.num_insts 167398 # Number of instructions executed -system.cpu1.num_refs 53394 # Number of memory references +system.cpu1.num_int_alu_accesses 109926 # Number of integer alu accesses +system.cpu1.num_int_insts 109926 # number of integer instructions +system.cpu1.num_int_register_reads 270038 # number of times the integer registers were read +system.cpu1.num_int_register_writes 100721 # number of times the integer registers were written +system.cpu1.num_load_insts 40652 # Number of load instructions +system.cpu1.num_mem_refs 53394 # number of memory refs +system.cpu1.num_store_insts 12742 # Number of store instructions system.cpu2.dcache.ReadReq_accesses 42354 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.ReadReq_hits 42192 # number of ReadReq hits system.cpu2.dcache.ReadReq_miss_rate 0.003825 # miss rate for ReadReq accesses @@ -340,8 +372,24 @@ system.cpu2.icache.writebacks 0 # nu system.cpu2.idle_fraction 0.045871 # Percentage of idle cycles system.cpu2.not_idle_fraction 0.954129 # Percentage of non-idle cycles system.cpu2.numCycles 173308 # number of cpu cycles simulated +system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu2.num_busy_cycles 165358.198620 # Number of busy cycles +system.cpu2.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu2.num_fp_insts 0 # number of float instructions +system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu2.num_func_calls 0 # number of times a function call or return occured +system.cpu2.num_idle_cycles 7949.801380 # Number of idle cycles system.cpu2.num_insts 167334 # Number of instructions executed -system.cpu2.num_refs 58537 # Number of memory references +system.cpu2.num_int_alu_accesses 113333 # Number of integer alu accesses +system.cpu2.num_int_insts 113333 # number of integer instructions +system.cpu2.num_int_register_reads 290613 # number of times the integer registers were read +system.cpu2.num_int_register_writes 109308 # number of times the integer registers were written +system.cpu2.num_load_insts 42362 # Number of load instructions +system.cpu2.num_mem_refs 58537 # number of memory refs +system.cpu2.num_store_insts 16175 # Number of store instructions system.cpu3.dcache.ReadReq_accesses 41458 # number of ReadReq accesses(hits+misses) system.cpu3.dcache.ReadReq_hits 41299 # number of ReadReq hits system.cpu3.dcache.ReadReq_miss_rate 0.003835 # miss rate for ReadReq accesses @@ -451,8 +499,24 @@ system.cpu3.icache.writebacks 0 # nu system.cpu3.idle_fraction 0.046241 # Percentage of idle cycles system.cpu3.not_idle_fraction 0.953759 # Percentage of non-idle cycles system.cpu3.numCycles 173307 # number of cpu cycles simulated +system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu3.num_busy_cycles 165293.030003 # Number of busy cycles +system.cpu3.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu3.num_fp_insts 0 # number of float instructions +system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu3.num_func_calls 0 # number of times a function call or return occured +system.cpu3.num_idle_cycles 8013.969997 # Number of idle cycles system.cpu3.num_insts 167269 # Number of instructions executed -system.cpu3.num_refs 55900 # Number of memory references +system.cpu3.num_int_alu_accesses 111554 # Number of integer alu accesses +system.cpu3.num_int_insts 111554 # number of integer instructions +system.cpu3.num_int_register_reads 280060 # number of times the integer registers were read +system.cpu3.num_int_register_writes 104916 # number of times the integer registers were written +system.cpu3.num_load_insts 41466 # Number of load instructions +system.cpu3.num_mem_refs 55900 # number of memory refs +system.cpu3.num_store_insts 14434 # Number of store instructions system.l2c.ReadExReq_accesses::0 99 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::1 13 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::2 12 # number of ReadExReq accesses(hits+misses) diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini index 276044213..8968b20fc 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus mem_mode=timing physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu0] type=TimingSimpleCPU diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout index cae225db3..14a3c411f 100755 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp/simout -Redirecting stderr to build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 13:03:41 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 13:03:45 -M5 executing on zizzer -command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp +M5 compiled Feb 7 2011 02:13:30 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:16:15 +M5 executing on burrito +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index a2bed5a68..dff846f53 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 583465 # Simulator instruction rate (inst/s) -host_mem_usage 215700 # Number of bytes of host memory used -host_seconds 1.12 # Real time elapsed on the host -host_tick_rate 235218525 # Simulator tick rate (ticks/s) +host_inst_rate 414570 # Simulator instruction rate (inst/s) +host_mem_usage 231892 # Number of bytes of host memory used +host_seconds 1.57 # Real time elapsed on the host +host_tick_rate 167151874 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 650423 # Number of instructions simulated sim_seconds 0.000262 # Number of seconds simulated @@ -141,8 +141,24 @@ system.cpu0.icache.writebacks 0 # nu system.cpu0.idle_fraction 0 # Percentage of idle cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.numCycles 524590 # number of cpu cycles simulated +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.num_busy_cycles 524590 # Number of busy cycles +system.cpu0.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu0.num_fp_insts 0 # number of float instructions +system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu0.num_func_calls 0 # number of times a function call or return occured +system.cpu0.num_idle_cycles 0 # Number of idle cycles system.cpu0.num_insts 158353 # Number of instructions executed -system.cpu0.num_refs 73905 # Number of memory references +system.cpu0.num_int_alu_accesses 109064 # Number of integer alu accesses +system.cpu0.num_int_insts 109064 # number of integer instructions +system.cpu0.num_int_register_reads 315336 # number of times the integer registers were read +system.cpu0.num_int_register_writes 110671 # number of times the integer registers were written +system.cpu0.num_load_insts 48930 # Number of load instructions +system.cpu0.num_mem_refs 73905 # number of memory refs +system.cpu0.num_store_insts 24975 # Number of store instructions system.cpu0.workload.PROG:num_syscalls 89 # Number of system calls system.cpu1.dcache.ReadReq_accesses 38632 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_avg_miss_latency 20316.666667 # average ReadReq miss latency @@ -279,8 +295,24 @@ system.cpu1.icache.writebacks 0 # nu system.cpu1.idle_fraction 0.130715 # Percentage of idle cycles system.cpu1.not_idle_fraction 0.869285 # Percentage of non-idle cycles system.cpu1.numCycles 513666 # number of cpu cycles simulated +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.num_busy_cycles 446521.933500 # Number of busy cycles +system.cpu1.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu1.num_fp_insts 0 # number of float instructions +system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu1.num_func_calls 0 # number of times a function call or return occured +system.cpu1.num_idle_cycles 67144.066500 # Number of idle cycles system.cpu1.num_insts 168364 # Number of instructions executed -system.cpu1.num_refs 46919 # Number of memory references +system.cpu1.num_int_alu_accesses 105930 # Number of integer alu accesses +system.cpu1.num_int_insts 105930 # number of integer instructions +system.cpu1.num_int_register_reads 244134 # number of times the integer registers were read +system.cpu1.num_int_register_writes 89763 # number of times the integer registers were written +system.cpu1.num_load_insts 38640 # Number of load instructions +system.cpu1.num_mem_refs 46919 # number of memory refs +system.cpu1.num_store_insts 8279 # Number of store instructions system.cpu2.dcache.ReadReq_accesses 40867 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.ReadReq_avg_miss_latency 15941.935484 # average ReadReq miss latency system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 12941.935484 # average ReadReq mshr miss latency @@ -416,8 +448,24 @@ system.cpu2.icache.writebacks 0 # nu system.cpu2.idle_fraction 0.131215 # Percentage of idle cycles system.cpu2.not_idle_fraction 0.868785 # Percentage of non-idle cycles system.cpu2.numCycles 513662 # number of cpu cycles simulated +system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu2.num_busy_cycles 446261.914218 # Number of busy cycles +system.cpu2.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu2.num_fp_insts 0 # number of float instructions +system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu2.num_func_calls 0 # number of times a function call or return occured +system.cpu2.num_idle_cycles 67400.085782 # Number of idle cycles system.cpu2.num_insts 161536 # Number of instructions executed -system.cpu2.num_refs 56961 # Number of memory references +system.cpu2.num_int_alu_accesses 110351 # Number of integer alu accesses +system.cpu2.num_int_insts 110351 # number of integer instructions +system.cpu2.num_int_register_reads 284309 # number of times the integer registers were read +system.cpu2.num_int_register_writes 107647 # number of times the integer registers were written +system.cpu2.num_load_insts 40875 # Number of load instructions +system.cpu2.num_mem_refs 56961 # number of memory refs +system.cpu2.num_store_insts 16086 # Number of store instructions system.cpu3.dcache.ReadReq_accesses 40736 # number of ReadReq accesses(hits+misses) system.cpu3.dcache.ReadReq_avg_miss_latency 16115.384615 # average ReadReq miss latency system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 13115.384615 # average ReadReq mshr miss latency @@ -553,8 +601,24 @@ system.cpu3.icache.writebacks 0 # nu system.cpu3.idle_fraction 0.131691 # Percentage of idle cycles system.cpu3.not_idle_fraction 0.868309 # Percentage of non-idle cycles system.cpu3.numCycles 513670 # number of cpu cycles simulated +system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu3.num_busy_cycles 446024.068564 # Number of busy cycles +system.cpu3.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu3.num_fp_insts 0 # number of float instructions +system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu3.num_func_calls 0 # number of times a function call or return occured +system.cpu3.num_idle_cycles 67645.931436 # Number of idle cycles system.cpu3.num_insts 162170 # Number of instructions executed -system.cpu3.num_refs 56264 # Number of memory references +system.cpu3.num_int_alu_accesses 110096 # Number of integer alu accesses +system.cpu3.num_int_insts 110096 # number of integer instructions +system.cpu3.num_int_register_reads 281520 # number of times the integer registers were read +system.cpu3.num_int_register_writes 106379 # number of times the integer registers were written +system.cpu3.num_load_insts 40744 # Number of load instructions +system.cpu3.num_mem_refs 56264 # number of memory refs +system.cpu3.num_store_insts 15520 # Number of store instructions system.l2c.ReadExReq_accesses::0 99 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::1 13 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::2 12 # number of ReadExReq accesses(hits+misses) diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini index 370a5746b..499a69fa0 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 [system] type=System children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 physmem ruby mem_mode=timing physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu0] type=MemTest @@ -368,10 +377,9 @@ port=system.ruby.cpu_ruby_ports0.physMemPort system.ruby.cpu_ruby_ports1.physMem [system.ruby] type=RubySystem -children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 debug network profiler tracer +children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 network profiler tracer block_size_bytes=64 clock=1 -debug=system.ruby.debug mem_size=134217728 network=system.ruby.network no_mem_vec=false @@ -383,6 +391,7 @@ tracer=system.ruby.tracer [system.ruby.cpu_ruby_ports0] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl0.cacheMemory deadlock_threshold=500000 icache=system.l1_cntrl0.cacheMemory @@ -395,6 +404,7 @@ port=system.cpu0.test [system.ruby.cpu_ruby_ports1] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl1.cacheMemory deadlock_threshold=500000 icache=system.l1_cntrl1.cacheMemory @@ -407,6 +417,7 @@ port=system.cpu1.test [system.ruby.cpu_ruby_ports2] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl2.cacheMemory deadlock_threshold=500000 icache=system.l1_cntrl2.cacheMemory @@ -419,6 +430,7 @@ port=system.cpu2.test [system.ruby.cpu_ruby_ports3] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl3.cacheMemory deadlock_threshold=500000 icache=system.l1_cntrl3.cacheMemory @@ -431,6 +443,7 @@ port=system.cpu3.test [system.ruby.cpu_ruby_ports4] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl4.cacheMemory deadlock_threshold=500000 icache=system.l1_cntrl4.cacheMemory @@ -443,6 +456,7 @@ port=system.cpu4.test [system.ruby.cpu_ruby_ports5] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl5.cacheMemory deadlock_threshold=500000 icache=system.l1_cntrl5.cacheMemory @@ -455,6 +469,7 @@ port=system.cpu5.test [system.ruby.cpu_ruby_ports6] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl6.cacheMemory deadlock_threshold=500000 icache=system.l1_cntrl6.cacheMemory @@ -467,6 +482,7 @@ port=system.cpu6.test [system.ruby.cpu_ruby_ports7] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl7.cacheMemory deadlock_threshold=500000 icache=system.l1_cntrl7.cacheMemory @@ -477,14 +493,6 @@ version=7 physMemPort=system.physmem.port[7] port=system.cpu7.test -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none - [system.ruby.network] type=SimpleNetwork children=topology diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats index f3ddd5354..86ac84392 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats @@ -34,29 +34,29 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Aug/20/2010 13:39:31 +Real time: Feb/07/2011 01:50:48 Profiler Stats -------------- -Elapsed_time_in_seconds: 69 -Elapsed_time_in_minutes: 1.15 -Elapsed_time_in_hours: 0.0191667 -Elapsed_time_in_days: 0.000798611 +Elapsed_time_in_seconds: 190 +Elapsed_time_in_minutes: 3.16667 +Elapsed_time_in_hours: 0.0527778 +Elapsed_time_in_days: 0.00219907 -Virtual_time_in_seconds: 68.75 -Virtual_time_in_minutes: 1.14583 -Virtual_time_in_hours: 0.0190972 -Virtual_time_in_days: 0.000795718 +Virtual_time_in_seconds: 99.44 +Virtual_time_in_minutes: 1.65733 +Virtual_time_in_hours: 0.0276222 +Virtual_time_in_days: 0.00115093 -Ruby_current_time: 11059012 +Ruby_current_time: 57251340 Ruby_start_time: 0 -Ruby_cycles: 11059012 +Ruby_cycles: 57251340 -mbytes_resident: 32.25 -mbytes_total: 333.105 -resident_ratio: 0.0968279 +mbytes_resident: 36.6133 +mbytes_total: 355.375 +resident_ratio: 0.103038 -ruby_cycles_executed: [ 11059013 11059013 11059013 11059013 11059013 11059013 11059013 11059013 ] +ruby_cycles_executed: [ 57251341 57251341 57251341 57251341 57251341 57251341 57251341 57251341 ] Busy Controller Counts: L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0 @@ -66,31 +66,29 @@ Directory-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1228772 average: 1.9375 | standard deviation: 0.242071 | 0 76804 1151968 ] +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1227441 average: 15.9992 | standard deviation: 0.0898992 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 1227321 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 4 max: 548 count: 1228757 average: 141.941 | standard deviation: 1.79768 | 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21 272 4811 76194 1147428 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD: [binsize: 4 max: 548 count: 798474 average: 141.942 | standard deviation: 1.87927 | 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18 174 3144 49367 745750 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST: [binsize: 4 max: 459 count: 430283 average: 141.94 | standard deviation: 1.63553 | 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 98 1667 26827 401678 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_L1Cache: [binsize: 1 max: 3 count: 14 average: 3 | standard deviation: 0 | 0 0 0 14 ] -miss_latency_Directory: [binsize: 2 max: 359 count: 2 average: 304 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_L1Cache_wCC: [binsize: 4 max: 548 count: 1228741 average: 141.942 | standard deviation: 1.72165 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21 272 4811 76194 1147428 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 6 average: 0 | standard deviation: 0 | 6 ] -miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 6 average: 0 | standard deviation: 0 | 6 ] -miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 6 average: 0 | standard deviation: 0 | 6 ] -miss_latency_wCC_first_response_to_completion: [binsize: 4 max: 495 count: 6 average: 412.667 | standard deviation: 76.4147 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -imcomplete_wCC_Times: 1228735 -miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 2 average: 0 | standard deviation: 0 | 2 ] -miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 2 average: 0 | standard deviation: 0 | 2 ] -miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 2 average: 0 | standard deviation: 0 | 2 ] -miss_latency_dir_first_response_to_completion: [binsize: 2 max: 359 count: 2 average: 304 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -imcomplete_dir_Times: 0 -miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 7 average: 3 | standard deviation: 0 | 0 0 0 7 ] -miss_latency_LD_Directory: [binsize: 2 max: 359 count: 2 average: 304 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_LD_L1Cache_wCC: [binsize: 4 max: 548 count: 798465 average: 141.943 | standard deviation: 1.81358 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18 174 3144 49367 745750 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 7 average: 3 | standard deviation: 0 | 0 0 0 7 ] -miss_latency_ST_L1Cache_wCC: [binsize: 4 max: 459 count: 430276 average: 141.942 | standard deviation: 1.53653 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 98 1667 26827 401678 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 128 max: 16170 count: 1227313 average: 5970.6 | standard deviation: 6226.1 | 0 5 5 5 5 5 5 5 3 0 6 5 4 9 28 67 117 196 325 493 850 1372 2115 2889 3474 5267 7331 8923 10961 13117 17439 19106 22197 27797 27598 30754 34950 40376 40150 37193 44218 47799 45035 44430 44397 47887 43214 42194 45299 37620 36866 36136 37155 31716 26415 28478 27184 22299 20319 18521 18170 14600 13557 13481 10233 9188 8568 8384 6564 5202 5341 4736 3697 3355 2785 2534 2139 1813 1715 1305 1213 1037 977 761 540 516 459 368 287 221 221 156 133 132 101 86 57 64 45 25 28 41 28 25 18 17 8 7 9 7 4 5 8 3 2 0 0 1 0 2 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 128 max: 16170 count: 797864 average: 5970.96 | standard deviation: 5567.96 | 0 4 4 4 4 4 4 4 1 0 1 4 4 6 23 42 79 125 214 331 544 877 1397 1863 2231 3466 4741 5801 7112 8516 11461 12380 14439 17894 17955 19944 22577 26201 26233 24153 28751 31184 29257 28993 28655 31123 28291 27538 29428 24371 23978 23499 24308 20557 17139 18652 17606 14368 13155 11966 11765 9607 8837 8844 6659 5936 5560 5504 4210 3414 3473 3145 2395 2145 1816 1622 1380 1171 1141 849 772 673 638 482 346 347 309 240 185 140 136 95 84 85 65 59 40 42 31 15 21 23 20 16 13 11 6 3 6 5 3 3 6 3 1 0 0 0 0 0 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 128 max: 15290 count: 429449 average: 5969.93 | standard deviation: 1423.42 | 0 1 1 1 1 1 1 1 2 0 5 1 0 3 5 25 38 71 111 162 306 495 718 1026 1243 1801 2590 3122 3849 4601 5978 6726 7758 9903 9643 10810 12373 14175 13917 13040 15467 16615 15778 15437 15742 16764 14923 14656 15871 13249 12888 12637 12847 11159 9276 9826 9578 7931 7164 6555 6405 4993 4720 4637 3574 3252 3008 2880 2354 1788 1868 1591 1302 1210 969 912 759 642 574 456 441 364 339 279 194 169 150 128 102 81 85 61 49 47 36 27 17 22 14 10 7 18 8 9 5 6 2 4 3 2 1 2 2 0 1 0 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_Directory: [binsize: 128 max: 16170 count: 1210799 average: 5976.91 | standard deviation: 6306.43 | 0 5 5 5 5 5 5 5 3 0 6 5 4 9 25 62 110 189 305 465 806 1312 2035 2792 3339 5094 7111 8663 10701 12775 17023 18729 21808 27255 27055 30221 34375 39759 39511 36575 43613 47122 44479 43852 43802 47301 42687 41791 44754 37147 36463 35788 36800 31395 26170 28198 26928 22083 20141 18352 18010 14477 13445 13354 10138 9095 8497 8327 6511 5159 5306 4695 3671 3321 2764 2511 2121 1803 1701 1296 1209 1028 975 758 537 511 458 365 284 218 218 156 133 132 101 86 57 62 43 25 28 41 28 25 18 17 8 7 9 7 4 5 8 3 2 0 0 1 0 2 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache_wCC: [binsize: 64 max: 12585 count: 16514 average: 5507.92 | standard deviation: 1405.44 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 3 2 3 4 3 4 10 10 16 12 19 25 26 34 35 45 45 52 71 64 84 89 98 122 124 136 137 123 165 177 197 219 187 190 187 202 274 268 276 267 243 290 258 317 297 320 337 302 325 293 290 315 320 357 281 275 296 282 331 264 270 316 252 275 203 200 297 248 265 208 206 197 170 178 187 168 186 135 131 114 140 140 129 127 114 102 100 78 86 83 72 88 56 67 54 58 72 55 56 39 45 48 44 27 26 31 22 31 24 19 19 16 27 14 14 12 24 10 13 8 8 15 10 8 4 6 9 5 3 6 2 2 2 7 1 1 0 3 1 2 3 2 0 1 2 1 2 1 2 1 1 2 0 0 0 0 0 0 0 0 0 0 0 0 1 1 2 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 16514 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 8 average: 0 | standard deviation: 0 | 8 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 8 average: 0 | standard deviation: 0 | 8 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 8 average: 0 | standard deviation: 0 | 8 ] +miss_latency_dir_first_response_to_completion: [binsize: 4 max: 569 count: 8 average: 330.25 | standard deviation: 178.281 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +imcomplete_dir_Times: 1210791 +miss_latency_LD_Directory: [binsize: 128 max: 16170 count: 787157 average: 5977.4 | standard deviation: 5638.59 | 0 4 4 4 4 4 4 4 1 0 1 4 4 6 20 37 73 120 198 310 520 832 1338 1800 2148 3355 4608 5614 6946 8289 11207 12142 14179 17561 17587 19588 22210 25807 25824 23747 28369 30735 28910 28603 28263 30729 27952 27268 29067 24058 23732 23284 24091 20357 16975 18458 17439 14222 13051 11864 11662 9526 8758 8751 6596 5876 5513 5476 4177 3395 3452 3117 2376 2125 1802 1609 1370 1164 1131 844 770 668 638 481 345 344 308 238 182 138 133 95 84 85 65 59 40 42 31 15 21 23 20 16 13 11 6 3 6 5 3 3 6 3 1 0 0 0 0 0 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_L1Cache_wCC: [binsize: 64 max: 11604 count: 10707 average: 5497.29 | standard deviation: 1398.22 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 3 2 2 4 2 3 10 6 11 10 12 12 21 24 26 33 30 33 43 40 49 62 62 71 90 97 85 81 109 118 117 137 123 115 124 136 167 166 175 193 160 196 158 209 187 207 224 185 212 194 180 202 215 234 180 167 201 189 218 174 184 210 163 176 141 129 197 164 169 144 128 118 105 110 104 113 120 80 90 74 101 93 83 84 71 75 61 43 49 53 49 54 38 43 42 37 49 44 36 27 27 33 26 21 9 19 11 22 10 9 12 9 20 8 11 8 14 6 9 5 6 7 5 5 4 3 6 4 3 2 1 1 1 4 0 0 0 1 0 1 2 1 0 1 2 0 2 1 2 0 1 2 ] +miss_latency_ST_Directory: [binsize: 128 max: 15290 count: 423642 average: 5976 | standard deviation: 1422.53 | 0 1 1 1 1 1 1 1 2 0 5 1 0 3 5 25 37 69 107 155 286 480 697 992 1191 1739 2503 3049 3755 4486 5816 6587 7629 9694 9468 10633 12165 13952 13687 12828 15244 16387 15569 15249 15539 16572 14735 14523 15687 13089 12731 12504 12709 11038 9195 9740 9489 7861 7090 6488 6348 4951 4687 4603 3542 3219 2984 2851 2334 1764 1854 1578 1295 1196 962 902 751 639 570 452 439 360 337 277 192 167 150 127 102 80 85 61 49 47 36 27 17 20 12 10 7 18 8 9 5 6 2 4 3 2 1 2 2 0 1 0 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache_wCC: [binsize: 64 max: 12585 count: 5807 average: 5527.52 | standard deviation: 1418.56 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 4 5 2 7 13 5 10 9 12 15 19 28 24 35 27 36 51 34 39 52 42 56 59 80 82 64 75 63 66 107 102 101 74 83 94 100 108 110 113 113 117 113 99 110 113 105 123 101 108 95 93 113 90 86 106 89 99 62 71 100 84 96 64 78 79 65 68 83 55 66 55 41 40 39 47 46 43 43 27 39 35 37 30 23 34 18 24 12 21 23 11 20 12 18 15 18 6 17 12 11 9 14 10 7 7 7 6 3 4 10 4 4 3 2 8 5 3 0 3 3 1 0 4 1 1 1 3 1 1 0 2 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 2 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -104,11 +102,11 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN Message Delayed Cycles ---------------------- -Total_delay_cycles: [binsize: 4 max: 151 count: 2457486 average: 47.4696 | standard deviation: 47.4806 | 1228745 0 0 0 1 0 0 1 0 0 0 1 0 0 0 2 0 0 0 7 145 2397 38169 611708 576306 0 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ] -Total_nonPF_delay_cycles: [binsize: 4 max: 151 count: 2457486 average: 47.4696 | standard deviation: 47.4806 | 1228745 0 0 0 1 0 0 1 0 0 0 1 0 0 0 2 0 0 0 7 145 2397 38169 611708 576306 0 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ] +Total_delay_cycles: [binsize: 1 max: 18 count: 2458515 average: 0.000321739 | standard deviation: 0.0752325 | 2458470 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 26 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 18 count: 2458515 average: 0.000321739 | standard deviation: 0.0752325 | 2458470 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 26 ] virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 1228743 average: 0 | standard deviation: 0 | 1228743 ] - virtual_network_2_delay_cycles: [binsize: 4 max: 151 count: 1228743 average: 94.9391 | standard deviation: 1.44451 | 2 0 0 0 1 0 0 1 0 0 0 1 0 0 0 2 0 0 0 7 145 2397 38169 611708 576306 0 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 1227313 average: 0 | standard deviation: 0 | 1227313 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 18 count: 1231202 average: 0.000642462 | standard deviation: 0.106311 | 1231157 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 26 ] virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -120,326 +118,337 @@ Total_nonPF_delay_cycles: [binsize: 4 max: 151 count: 2457486 average: 47.4696 | Resource Usage -------------- page_size: 4096 -user_time: 68 +user_time: 99 system_time: 0 -page_reclaims: 9322 +page_reclaims: 10455 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 0 +block_outputs: 112 Network Stats ------------- -total_msg_count_Control: 3686271 29490168 -total_msg_count_Response_Data: 3686229 265408488 -total_msg_count_Writeback_Control: 3686259 29490072 -total_msgs: 11058759 total_bytes: 324388728 +total_msg_count_Control: 3681972 29455776 +total_msg_count_Data: 3644124 262376928 +total_msg_count_Response_Data: 3681939 265099608 +total_msg_count_Writeback_Control: 3693606 29548848 +total_msgs: 14701641 total_bytes: 586481160 switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.434016 - links_utilized_percent_switch_0_link_0: 0.173606 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.694426 bw: 160000 base_latency: 1 +links_utilized_percent_switch_0: 0.083792 + links_utilized_percent_switch_0_link_0: 0.0334493 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.134135 bw: 160000 base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Control: 153595 1228760 [ 0 0 153595 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 153153 11027016 [ 0 0 0 0 153153 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 153635 1229080 [ 0 0 0 153635 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 153154 1225232 [ 0 0 153154 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Data: 151525 10909800 [ 0 0 151525 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 2111 151992 [ 0 0 0 0 2111 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.434016 - links_utilized_percent_switch_1_link_0: 0.173606 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.694426 bw: 160000 base_latency: 1 +links_utilized_percent_switch_1: 0.0839004 + links_utilized_percent_switch_1_link_0: 0.0334929 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.134308 bw: 160000 base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Control: 153595 1228760 [ 0 0 153595 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Data: 153353 11041416 [ 0 0 0 0 153353 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 153833 1230664 [ 0 0 0 153833 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Control: 153355 1226840 [ 0 0 153355 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Data: 151790 10928880 [ 0 0 151790 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 2044 147168 [ 0 0 0 0 2044 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.434016 - links_utilized_percent_switch_2_link_0: 0.173606 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.694426 bw: 160000 base_latency: 1 +links_utilized_percent_switch_2: 0.0839292 + links_utilized_percent_switch_2_link_0: 0.0334995 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.134359 bw: 160000 base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 153595 1228760 [ 0 0 0 153595 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Control: 153595 1228760 [ 0 0 153595 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 153380 11043360 [ 0 0 0 0 153380 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 153895 1231160 [ 0 0 0 153895 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Control: 153381 1227048 [ 0 0 153381 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Data: 151808 10930176 [ 0 0 151808 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 2088 150336 [ 0 0 0 0 2088 0 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 2 switch_3_outlinks: 2 -links_utilized_percent_switch_3: 0.434016 - links_utilized_percent_switch_3_link_0: 0.173606 bw: 640000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.694426 bw: 160000 base_latency: 1 +links_utilized_percent_switch_3: 0.0839178 + links_utilized_percent_switch_3_link_0: 0.0335004 bw: 640000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.134335 bw: 160000 base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Control: 153595 1228760 [ 0 0 153595 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 153388 11043936 [ 0 0 0 0 153388 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Writeback_Control: 153864 1230912 [ 0 0 0 153864 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Control: 153389 1227112 [ 0 0 153389 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Data: 151791 10928952 [ 0 0 151791 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 2074 149328 [ 0 0 0 0 2074 0 0 0 0 0 ] base_latency: 1 switch_4_inlinks: 2 switch_4_outlinks: 2 -links_utilized_percent_switch_4: 0.434014 - links_utilized_percent_switch_4_link_0: 0.173606 bw: 640000 base_latency: 1 - links_utilized_percent_switch_4_link_1: 0.694421 bw: 160000 base_latency: 1 +links_utilized_percent_switch_4: 0.0841195 + links_utilized_percent_switch_4_link_0: 0.0335808 bw: 640000 base_latency: 1 + links_utilized_percent_switch_4_link_1: 0.134658 bw: 160000 base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Control: 153594 1228752 [ 0 0 153594 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Data: 153592 11058624 [ 0 0 0 0 153592 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Data: 153756 11070432 [ 0 0 0 0 153756 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Writeback_Control: 154232 1233856 [ 0 0 0 154232 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Control: 153758 1230064 [ 0 0 153758 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Data: 152172 10956384 [ 0 0 152172 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Data: 2063 148536 [ 0 0 0 0 2063 0 0 0 0 0 ] base_latency: 1 switch_5_inlinks: 2 switch_5_outlinks: 2 -links_utilized_percent_switch_5: 0.434016 - links_utilized_percent_switch_5_link_0: 0.173606 bw: 640000 base_latency: 1 - links_utilized_percent_switch_5_link_1: 0.694426 bw: 160000 base_latency: 1 +links_utilized_percent_switch_5: 0.0840452 + links_utilized_percent_switch_5_link_0: 0.0335493 bw: 640000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 0.134541 bw: 160000 base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Control: 153595 1228760 [ 0 0 153595 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Data: 153611 11059992 [ 0 0 0 0 153611 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Writeback_Control: 154097 1232776 [ 0 0 0 154097 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Control: 153613 1228904 [ 0 0 153613 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Data: 152110 10951920 [ 0 0 152110 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Data: 1992 143424 [ 0 0 0 0 1992 0 0 0 0 0 ] base_latency: 1 switch_6_inlinks: 2 switch_6_outlinks: 2 -links_utilized_percent_switch_6: 0.434014 - links_utilized_percent_switch_6_link_0: 0.173606 bw: 640000 base_latency: 1 - links_utilized_percent_switch_6_link_1: 0.694421 bw: 160000 base_latency: 1 +links_utilized_percent_switch_6: 0.084233 + links_utilized_percent_switch_6_link_0: 0.0336256 bw: 640000 base_latency: 1 + links_utilized_percent_switch_6_link_1: 0.13484 bw: 160000 base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Control: 153594 1228752 [ 0 0 153594 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Data: 153592 11058624 [ 0 0 0 0 153592 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Data: 153961 11085192 [ 0 0 0 0 153961 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Writeback_Control: 154441 1235528 [ 0 0 0 154441 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Control: 153962 1231696 [ 0 0 153962 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Data: 152406 10973232 [ 0 0 152406 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Data: 2038 146736 [ 0 0 0 0 2038 0 0 0 0 0 ] base_latency: 1 switch_7_inlinks: 2 switch_7_outlinks: 2 -links_utilized_percent_switch_7: 0.434013 - links_utilized_percent_switch_7_link_0: 0.173605 bw: 640000 base_latency: 1 - links_utilized_percent_switch_7_link_1: 0.694421 bw: 160000 base_latency: 1 +links_utilized_percent_switch_7: 0.0835571 + links_utilized_percent_switch_7_link_0: 0.033353 bw: 640000 base_latency: 1 + links_utilized_percent_switch_7_link_1: 0.133761 bw: 160000 base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Data: 153592 11058624 [ 0 0 0 0 153592 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Control: 153594 1228752 [ 0 0 153594 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Data: 153592 11058624 [ 0 0 0 0 153592 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Data: 152711 10995192 [ 0 0 0 0 152711 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Writeback_Control: 153205 1225640 [ 0 0 0 153205 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Control: 152712 1221696 [ 0 0 152712 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Data: 151106 10879632 [ 0 0 151106 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Data: 2104 151488 [ 0 0 0 0 2104 0 0 0 0 0 ] base_latency: 1 switch_8_inlinks: 2 switch_8_outlinks: 2 -links_utilized_percent_switch_8: 0.347219 - links_utilized_percent_switch_8_link_0: 0.138886 bw: 640000 base_latency: 1 - links_utilized_percent_switch_8_link_1: 0.555552 bw: 160000 base_latency: 1 +links_utilized_percent_switch_8: 0.662356 + links_utilized_percent_switch_8_link_0: 0.265489 bw: 640000 base_latency: 1 + links_utilized_percent_switch_8_link_1: 1.05922 bw: 160000 base_latency: 1 - outgoing_messages_switch_8_link_0_Control: 1228757 9830056 [ 0 0 1228757 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Response_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Writeback_Control: 1228753 9830024 [ 0 0 0 1228753 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Control: 1227324 9818592 [ 0 0 1227324 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Data: 1214708 87458976 [ 0 0 1214708 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Response_Data: 1210799 87177528 [ 0 0 0 0 1210799 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Writeback_Control: 1231202 9849616 [ 0 0 0 1231202 0 0 0 0 0 0 ] base_latency: 1 switch_9_inlinks: 9 switch_9_outlinks: 9 -links_utilized_percent_switch_9: 0.678994 - links_utilized_percent_switch_9_link_0: 0.694425 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_1: 0.694425 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_2: 0.694426 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_3: 0.694425 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_4: 0.694425 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_5: 0.694425 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_6: 0.694425 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_7: 0.694421 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_8: 0.555546 bw: 160000 base_latency: 1 - - outgoing_messages_switch_9_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Writeback_Control: 153595 1228760 [ 0 0 0 153595 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_3_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_3_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_5_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_5_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Response_Data: 153592 11058624 [ 0 0 0 0 153592 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_8_Control: 1228757 9830056 [ 0 0 1228757 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_9: 0.237129 + links_utilized_percent_switch_9_link_0: 0.133797 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_1: 0.133972 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_2: 0.133998 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_3: 0.134002 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_4: 0.134323 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_5: 0.134197 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_6: 0.134503 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_7: 0.133412 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_8: 1.06196 bw: 160000 base_latency: 1 + + outgoing_messages_switch_9_link_0_Response_Data: 153153 11027016 [ 0 0 0 0 153153 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Writeback_Control: 153635 1229080 [ 0 0 0 153635 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Response_Data: 153353 11041416 [ 0 0 0 0 153353 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Writeback_Control: 153833 1230664 [ 0 0 0 153833 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Response_Data: 153380 11043360 [ 0 0 0 0 153380 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Writeback_Control: 153895 1231160 [ 0 0 0 153895 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Response_Data: 153388 11043936 [ 0 0 0 0 153388 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Writeback_Control: 153864 1230912 [ 0 0 0 153864 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Response_Data: 153756 11070432 [ 0 0 0 0 153756 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Writeback_Control: 154232 1233856 [ 0 0 0 154232 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Response_Data: 153611 11059992 [ 0 0 0 0 153611 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Writeback_Control: 154097 1232776 [ 0 0 0 154097 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Response_Data: 153961 11085192 [ 0 0 0 0 153961 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Writeback_Control: 154441 1235528 [ 0 0 0 154441 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Response_Data: 152711 10995192 [ 0 0 0 0 152711 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Writeback_Control: 153205 1225640 [ 0 0 0 153205 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_8_Control: 1227324 9818592 [ 0 0 1227324 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_8_Data: 1214708 87458976 [ 0 0 1214708 0 0 0 0 0 0 0 ] base_latency: 1 Cache Stats: system.l1_cntrl0.cacheMemory - system.l1_cntrl0.cacheMemory_total_misses: 153595 - system.l1_cntrl0.cacheMemory_total_demand_misses: 153595 + system.l1_cntrl0.cacheMemory_total_misses: 153154 + system.l1_cntrl0.cacheMemory_total_demand_misses: 153154 system.l1_cntrl0.cacheMemory_total_prefetches: 0 system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0 system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl0.cacheMemory_request_type_LD: 64.8608% - system.l1_cntrl0.cacheMemory_request_type_ST: 35.1392% + system.l1_cntrl0.cacheMemory_request_type_LD: 65.2232% + system.l1_cntrl0.cacheMemory_request_type_ST: 34.7768% - system.l1_cntrl0.cacheMemory_access_mode_type_SupervisorMode: 153595 100% + system.l1_cntrl0.cacheMemory_access_mode_type_SupervisorMode: 153154 100% --- L1Cache --- - Event Counts - -Load [100001 99948 99718 99978 99623 99719 99984 99512 ] 798483 +Load [99856 100002 99839 99184 99892 99648 99764 99685 ] 797870 Ifetch [0 0 0 0 0 0 0 0 ] 0 -Store [53593 53647 53876 53616 53974 53880 53619 54083 ] 430288 -Data [153593 153593 153593 153592 153593 153593 153593 153593 ] 1228743 -Fwd_GETX [153593 153593 153593 153592 153593 153593 153593 153593 ] 1228743 +Store [53902 53611 54123 53528 53262 53707 53617 53704 ] 429454 +Data [153756 153611 153961 152711 153153 153353 153380 153388 ] 1227313 +Fwd_GETX [2063 1992 2038 2104 2111 2044 2088 2074 ] 16514 Inv [0 0 0 0 0 0 0 0 ] 0 -Replacement [0 0 0 0 0 0 0 0 ] 0 -Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 -Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 +Replacement [153754 153609 153958 152708 153150 153351 153377 153385 ] 1227292 +Writeback_Ack [151688 151612 151917 150599 151038 151306 151288 151310 ] 1210758 +Writeback_Nack [481 493 486 502 486 483 519 480 ] 3930 - Transitions - -I Load [100001 99948 99718 99978 99623 99718 99978 99512 ] 798476 +I Load [99856 100002 99839 99184 99892 99648 99764 99685 ] 797870 I Ifetch [0 0 0 0 0 0 0 0 ] 0 -I Store [53593 53647 53876 53616 53972 53877 53617 54083 ] 430281 +I Store [53902 53611 54123 53528 53262 53707 53617 53704 ] 429454 I Inv [0 0 0 0 0 0 0 0 ] 0 -I Replacement [0 0 0 0 0 0 0 0 ] 0 +I Replacement [1582 1499 1552 1602 1625 1561 1569 1594 ] 12584 -II Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 +II Writeback_Nack [481 493 486 502 486 483 519 480 ] 3930 -M Load [0 0 0 0 0 1 6 0 ] 7 +M Load [0 0 0 0 0 0 0 0 ] 0 M Ifetch [0 0 0 0 0 0 0 0 ] 0 -M Store [0 0 0 0 2 3 2 0 ] 7 -M Fwd_GETX [153593 153593 153593 153592 153593 153593 153593 153593 ] 1228743 +M Store [0 0 0 0 0 0 0 0 ] 0 +M Fwd_GETX [1582 1499 1552 1602 1625 1561 1569 1594 ] 12584 M Inv [0 0 0 0 0 0 0 0 ] 0 -M Replacement [0 0 0 0 0 0 0 0 ] 0 +M Replacement [152172 152110 152406 151106 151525 151790 151808 151791 ] 1214708 -MI Fwd_GETX [0 0 0 0 0 0 0 0 ] 0 +MI Fwd_GETX [481 493 486 502 486 483 519 480 ] 3930 MI Inv [0 0 0 0 0 0 0 0 ] 0 -MI Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 +MI Writeback_Ack [151688 151612 151917 150599 151038 151306 151288 151310 ] 1210758 MI Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 MII Fwd_GETX [0 0 0 0 0 0 0 0 ] 0 -IS Data [100000 99946 99718 99976 99622 99716 99977 99512 ] 798467 +IS Data [99856 100000 99838 99183 99892 99647 99764 99684 ] 797864 -IM Data [53593 53647 53875 53616 53971 53877 53616 54081 ] 430276 +IM Data [53900 53611 54123 53528 53261 53706 53616 53704 ] 429449 Cache Stats: system.l1_cntrl1.cacheMemory - system.l1_cntrl1.cacheMemory_total_misses: 153595 - system.l1_cntrl1.cacheMemory_total_demand_misses: 153595 + system.l1_cntrl1.cacheMemory_total_misses: 153355 + system.l1_cntrl1.cacheMemory_total_demand_misses: 153355 system.l1_cntrl1.cacheMemory_total_prefetches: 0 system.l1_cntrl1.cacheMemory_total_sw_prefetches: 0 system.l1_cntrl1.cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl1.cacheMemory_request_type_LD: 64.9227% - system.l1_cntrl1.cacheMemory_request_type_ST: 35.0773% + system.l1_cntrl1.cacheMemory_request_type_LD: 64.9786% + system.l1_cntrl1.cacheMemory_request_type_ST: 35.0214% - system.l1_cntrl1.cacheMemory_access_mode_type_SupervisorMode: 153595 100% + system.l1_cntrl1.cacheMemory_access_mode_type_SupervisorMode: 153355 100% Cache Stats: system.l1_cntrl2.cacheMemory - system.l1_cntrl2.cacheMemory_total_misses: 153595 - system.l1_cntrl2.cacheMemory_total_demand_misses: 153595 + system.l1_cntrl2.cacheMemory_total_misses: 153381 + system.l1_cntrl2.cacheMemory_total_demand_misses: 153381 system.l1_cntrl2.cacheMemory_total_prefetches: 0 system.l1_cntrl2.cacheMemory_total_sw_prefetches: 0 system.l1_cntrl2.cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl2.cacheMemory_request_type_LD: 65.092% - system.l1_cntrl2.cacheMemory_request_type_ST: 34.908% + system.l1_cntrl2.cacheMemory_request_type_LD: 65.0433% + system.l1_cntrl2.cacheMemory_request_type_ST: 34.9567% - system.l1_cntrl2.cacheMemory_access_mode_type_SupervisorMode: 153595 100% + system.l1_cntrl2.cacheMemory_access_mode_type_SupervisorMode: 153381 100% Cache Stats: system.l1_cntrl3.cacheMemory - system.l1_cntrl3.cacheMemory_total_misses: 153595 - system.l1_cntrl3.cacheMemory_total_demand_misses: 153595 + system.l1_cntrl3.cacheMemory_total_misses: 153389 + system.l1_cntrl3.cacheMemory_total_demand_misses: 153389 system.l1_cntrl3.cacheMemory_total_prefetches: 0 system.l1_cntrl3.cacheMemory_total_sw_prefetches: 0 system.l1_cntrl3.cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl3.cacheMemory_request_type_LD: 64.7886% - system.l1_cntrl3.cacheMemory_request_type_ST: 35.2114% + system.l1_cntrl3.cacheMemory_request_type_LD: 64.9884% + system.l1_cntrl3.cacheMemory_request_type_ST: 35.0116% - system.l1_cntrl3.cacheMemory_access_mode_type_SupervisorMode: 153595 100% + system.l1_cntrl3.cacheMemory_access_mode_type_SupervisorMode: 153389 100% Cache Stats: system.l1_cntrl4.cacheMemory - system.l1_cntrl4.cacheMemory_total_misses: 153594 - system.l1_cntrl4.cacheMemory_total_demand_misses: 153594 + system.l1_cntrl4.cacheMemory_total_misses: 153758 + system.l1_cntrl4.cacheMemory_total_demand_misses: 153758 system.l1_cntrl4.cacheMemory_total_prefetches: 0 system.l1_cntrl4.cacheMemory_total_sw_prefetches: 0 system.l1_cntrl4.cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl4.cacheMemory_request_type_LD: 65.1074% - system.l1_cntrl4.cacheMemory_request_type_ST: 34.8926% + system.l1_cntrl4.cacheMemory_request_type_LD: 64.9436% + system.l1_cntrl4.cacheMemory_request_type_ST: 35.0564% - system.l1_cntrl4.cacheMemory_access_mode_type_SupervisorMode: 153594 100% + system.l1_cntrl4.cacheMemory_access_mode_type_SupervisorMode: 153758 100% Cache Stats: system.l1_cntrl5.cacheMemory - system.l1_cntrl5.cacheMemory_total_misses: 153595 - system.l1_cntrl5.cacheMemory_total_demand_misses: 153595 + system.l1_cntrl5.cacheMemory_total_misses: 153613 + system.l1_cntrl5.cacheMemory_total_demand_misses: 153613 system.l1_cntrl5.cacheMemory_total_prefetches: 0 system.l1_cntrl5.cacheMemory_total_sw_prefetches: 0 system.l1_cntrl5.cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl5.cacheMemory_request_type_LD: 65.0724% - system.l1_cntrl5.cacheMemory_request_type_ST: 34.9276% + system.l1_cntrl5.cacheMemory_request_type_LD: 65.1% + system.l1_cntrl5.cacheMemory_request_type_ST: 34.9% - system.l1_cntrl5.cacheMemory_access_mode_type_SupervisorMode: 153595 100% + system.l1_cntrl5.cacheMemory_access_mode_type_SupervisorMode: 153613 100% Cache Stats: system.l1_cntrl6.cacheMemory - system.l1_cntrl6.cacheMemory_total_misses: 153594 - system.l1_cntrl6.cacheMemory_total_demand_misses: 153594 + system.l1_cntrl6.cacheMemory_total_misses: 153962 + system.l1_cntrl6.cacheMemory_total_demand_misses: 153962 system.l1_cntrl6.cacheMemory_total_prefetches: 0 system.l1_cntrl6.cacheMemory_total_sw_prefetches: 0 system.l1_cntrl6.cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl6.cacheMemory_request_type_LD: 64.9231% - system.l1_cntrl6.cacheMemory_request_type_ST: 35.0769% + system.l1_cntrl6.cacheMemory_request_type_LD: 64.8465% + system.l1_cntrl6.cacheMemory_request_type_ST: 35.1535% - system.l1_cntrl6.cacheMemory_access_mode_type_SupervisorMode: 153594 100% + system.l1_cntrl6.cacheMemory_access_mode_type_SupervisorMode: 153962 100% Cache Stats: system.l1_cntrl7.cacheMemory - system.l1_cntrl7.cacheMemory_total_misses: 153594 - system.l1_cntrl7.cacheMemory_total_demand_misses: 153594 + system.l1_cntrl7.cacheMemory_total_misses: 152712 + system.l1_cntrl7.cacheMemory_total_demand_misses: 152712 system.l1_cntrl7.cacheMemory_total_prefetches: 0 system.l1_cntrl7.cacheMemory_total_sw_prefetches: 0 system.l1_cntrl7.cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl7.cacheMemory_request_type_LD: 65.0924% - system.l1_cntrl7.cacheMemory_request_type_ST: 34.9076% + system.l1_cntrl7.cacheMemory_request_type_LD: 64.9484% + system.l1_cntrl7.cacheMemory_request_type_ST: 35.0516% - system.l1_cntrl7.cacheMemory_access_mode_type_SupervisorMode: 153594 100% + system.l1_cntrl7.cacheMemory_access_mode_type_SupervisorMode: 152712 100% Memory controller: system.dir_cntrl0.memBuffer: - memory_total_requests: 2 - memory_reads: 2 - memory_writes: 0 - memory_refreshes: 22 - memory_total_request_delays: 31 - memory_delays_per_request: 15.5 - memory_delays_in_input_queue: 1 - memory_delays_behind_head_of_bank_queue: 10 - memory_delays_stalled_at_head_of_bank_queue: 20 - memory_stalls_for_bank_busy: 20 + memory_total_requests: 2421588 + memory_reads: 1210803 + memory_writes: 1210758 + memory_refreshes: 119274 + memory_total_request_delays: 190155514 + memory_delays_per_request: 78.5251 + memory_delays_in_input_queue: 11307810 + memory_delays_behind_head_of_bank_queue: 85310074 + memory_delays_stalled_at_head_of_bank_queue: 93537630 + memory_stalls_for_bank_busy: 14384463 memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 0 - memory_stalls_for_bus: 0 + memory_stalls_for_anti_starvation: 24076432 + memory_stalls_for_arbitration: 18499124 + memory_stalls_for_bus: 25289267 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 0 - memory_stalls_for_read_read_turnaround: 0 - accesses_per_bank: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + memory_stalls_for_read_write_turnaround: 9173208 + memory_stalls_for_read_read_turnaround: 2115136 + accesses_per_bank: 75973 75871 75584 75990 75871 76208 76264 75323 76082 76056 76271 75892 75688 75751 75586 75406 75587 75216 76023 75699 75573 75534 75382 75564 75891 75161 75298 74700 75598 75166 76030 75350 --- Directory --- - Event Counts - -GETX [1229168 ] 1229168 +GETX [2497405 ] 2497405 GETS [0 ] 0 -PUTX [0 ] 0 -PUTX_NotOwner [0 ] 0 +PUTX [1210778 ] 1210778 +PUTX_NotOwner [3930 ] 3930 DMA_READ [0 ] 0 DMA_WRITE [0 ] 0 -Memory_Data [2 ] 2 -Memory_Ack [0 ] 0 +Memory_Data [1210799 ] 1210799 +Memory_Ack [1210758 ] 1210758 - Transitions - -I GETX [2 ] 2 +I GETX [1210810 ] 1210810 I PUTX_NotOwner [0 ] 0 I DMA_READ [0 ] 0 I DMA_WRITE [0 ] 0 -M GETX [1228755 ] 1228755 -M PUTX [0 ] 0 -M PUTX_NotOwner [0 ] 0 +M GETX [16514 ] 16514 +M PUTX [1210778 ] 1210778 +M PUTX_NotOwner [3930 ] 3930 M DMA_READ [0 ] 0 M DMA_WRITE [0 ] 0 @@ -455,21 +464,21 @@ M_DWRI Memory_Ack [0 ] 0 M_DRDI GETX [0 ] 0 M_DRDI Memory_Ack [0 ] 0 -IM GETX [411 ] 411 +IM GETX [491344 ] 491344 IM GETS [0 ] 0 IM PUTX [0 ] 0 IM PUTX_NotOwner [0 ] 0 IM DMA_READ [0 ] 0 IM DMA_WRITE [0 ] 0 -IM Memory_Data [2 ] 2 +IM Memory_Data [1210799 ] 1210799 -MI GETX [0 ] 0 +MI GETX [778737 ] 778737 MI GETS [0 ] 0 MI PUTX [0 ] 0 MI PUTX_NotOwner [0 ] 0 MI DMA_READ [0 ] 0 MI DMA_WRITE [0 ] 0 -MI Memory_Ack [0 ] 0 +MI Memory_Ack [1210758 ] 1210758 ID GETX [0 ] 0 ID GETS [0 ] 0 diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr index bc0af1811..e2711df60 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr @@ -1,74 +1,74 @@ -system.cpu5: completed 10000 read accesses @1097056 -system.cpu4: completed 10000 read accesses @1101790 -system.cpu2: completed 10000 read accesses @1104058 -system.cpu0: completed 10000 read accesses @1107910 -system.cpu7: completed 10000 read accesses @1111870 -system.cpu1: completed 10000 read accesses @1114192 -system.cpu6: completed 10000 read accesses @1114876 -system.cpu3: completed 10000 read accesses @1117090 -system.cpu5: completed 20000 read accesses @2192968 -system.cpu0: completed 20000 read accesses @2201554 -system.cpu2: completed 20000 read accesses @2213290 -system.cpu4: completed 20000 read accesses @2213470 -system.cpu6: completed 20000 read accesses @2213812 -system.cpu7: completed 20000 read accesses @2222758 -system.cpu1: completed 20000 read accesses @2232856 -system.cpu3: completed 20000 read accesses @2238562 -system.cpu5: completed 30000 read accesses @3309256 -system.cpu6: completed 30000 read accesses @3313180 -system.cpu0: completed 30000 read accesses @3314566 -system.cpu4: completed 30000 read accesses @3316942 -system.cpu2: completed 30000 read accesses @3324682 -system.cpu7: completed 30000 read accesses @3331702 -system.cpu1: completed 30000 read accesses @3337912 -system.cpu3: completed 30000 read accesses @3342322 -system.cpu5: completed 40000 read accesses @4420792 -system.cpu7: completed 40000 read accesses @4420990 -system.cpu6: completed 40000 read accesses @4421692 -system.cpu4: completed 40000 read accesses @4422430 -system.cpu0: completed 40000 read accesses @4424770 -system.cpu2: completed 40000 read accesses @4424842 -system.cpu3: completed 40000 read accesses @4446316 -system.cpu1: completed 40000 read accesses @4448440 -system.cpu5: completed 50000 read accesses @5519584 -system.cpu4: completed 50000 read accesses @5528980 -system.cpu0: completed 50000 read accesses @5530150 -system.cpu2: completed 50000 read accesses @5533210 -system.cpu7: completed 50000 read accesses @5537782 -system.cpu6: completed 50000 read accesses @5538916 -system.cpu3: completed 50000 read accesses @5549410 -system.cpu1: completed 50000 read accesses @5549536 -system.cpu7: completed 60000 read accesses @6629734 -system.cpu5: completed 60000 read accesses @6636160 -system.cpu4: completed 60000 read accesses @6637060 -system.cpu2: completed 60000 read accesses @6637402 -system.cpu0: completed 60000 read accesses @6644710 -system.cpu1: completed 60000 read accesses @6651352 -system.cpu6: completed 60000 read accesses @6651892 -system.cpu3: completed 60000 read accesses @6661234 -system.cpu7: completed 70000 read accesses @7727014 -system.cpu4: completed 70000 read accesses @7730110 -system.cpu5: completed 70000 read accesses @7736608 -system.cpu2: completed 70000 read accesses @7742746 -system.cpu6: completed 70000 read accesses @7757092 -system.cpu0: completed 70000 read accesses @7759378 -system.cpu1: completed 70000 read accesses @7770088 -system.cpu3: completed 70000 read accesses @7773058 -system.cpu5: completed 80000 read accesses @8842240 -system.cpu7: completed 80000 read accesses @8843086 -system.cpu4: completed 80000 read accesses @8844580 -system.cpu2: completed 80000 read accesses @8853131 -system.cpu0: completed 80000 read accesses @8863426 -system.cpu6: completed 80000 read accesses @8876836 -system.cpu1: completed 80000 read accesses @8878960 -system.cpu3: completed 80000 read accesses @8885602 -system.cpu5: completed 90000 read accesses @9955126 -system.cpu7: completed 90000 read accesses @9956782 -system.cpu4: completed 90000 read accesses @9957844 -system.cpu2: completed 90000 read accesses @9967690 -system.cpu1: completed 90000 read accesses @9973576 -system.cpu0: completed 90000 read accesses @9976024 -system.cpu6: completed 90000 read accesses @9981604 -system.cpu3: completed 90000 read accesses @9999874 -system.cpu4: completed 100000 read accesses @11059012 +system.cpu5: completed 10000 read accesses @5727250 +system.cpu4: completed 10000 read accesses @5731690 +system.cpu7: completed 10000 read accesses @5735040 +system.cpu3: completed 10000 read accesses @5738300 +system.cpu6: completed 10000 read accesses @5748590 +system.cpu2: completed 10000 read accesses @5761080 +system.cpu0: completed 10000 read accesses @5773280 +system.cpu1: completed 10000 read accesses @5776650 +system.cpu4: completed 20000 read accesses @11398130 +system.cpu1: completed 20000 read accesses @11455110 +system.cpu3: completed 20000 read accesses @11459820 +system.cpu6: completed 20000 read accesses @11463230 +system.cpu0: completed 20000 read accesses @11469310 +system.cpu5: completed 20000 read accesses @11490080 +system.cpu2: completed 20000 read accesses @11498750 +system.cpu7: completed 20000 read accesses @11572610 +system.cpu4: completed 30000 read accesses @17076120 +system.cpu1: completed 30000 read accesses @17150670 +system.cpu5: completed 30000 read accesses @17204690 +system.cpu3: completed 30000 read accesses @17209580 +system.cpu0: completed 30000 read accesses @17264545 +system.cpu6: completed 30000 read accesses @17274220 +system.cpu2: completed 30000 read accesses @17284860 +system.cpu7: completed 30000 read accesses @17343350 +system.cpu4: completed 40000 read accesses @22747010 +system.cpu1: completed 40000 read accesses @22900920 +system.cpu5: completed 40000 read accesses @22928450 +system.cpu3: completed 40000 read accesses @22962360 +system.cpu0: completed 40000 read accesses @22981310 +system.cpu6: completed 40000 read accesses @23018750 +system.cpu2: completed 40000 read accesses @23061180 +system.cpu7: completed 40000 read accesses @23154824 +system.cpu4: completed 50000 read accesses @28547090 +system.cpu5: completed 50000 read accesses @28620310 +system.cpu1: completed 50000 read accesses @28677730 +system.cpu3: completed 50000 read accesses @28690730 +system.cpu6: completed 50000 read accesses @28729220 +system.cpu0: completed 50000 read accesses @28766380 +system.cpu2: completed 50000 read accesses @28834360 +system.cpu7: completed 50000 read accesses @28946860 +system.cpu4: completed 60000 read accesses @34313400 +system.cpu5: completed 60000 read accesses @34314670 +system.cpu3: completed 60000 read accesses @34419440 +system.cpu1: completed 60000 read accesses @34450630 +system.cpu6: completed 60000 read accesses @34477780 +system.cpu0: completed 60000 read accesses @34500340 +system.cpu2: completed 60000 read accesses @34535810 +system.cpu7: completed 60000 read accesses @34657810 +system.cpu5: completed 70000 read accesses @40003670 +system.cpu4: completed 70000 read accesses @40058990 +system.cpu3: completed 70000 read accesses @40162430 +system.cpu0: completed 70000 read accesses @40197610 +system.cpu6: completed 70000 read accesses @40218844 +system.cpu1: completed 70000 read accesses @40223070 +system.cpu2: completed 70000 read accesses @40246640 +system.cpu7: completed 70000 read accesses @40416250 +system.cpu5: completed 80000 read accesses @45745700 +system.cpu4: completed 80000 read accesses @45764460 +system.cpu3: completed 80000 read accesses @45881080 +system.cpu0: completed 80000 read accesses @45887290 +system.cpu2: completed 80000 read accesses @45902430 +system.cpu6: completed 80000 read accesses @45914170 +system.cpu1: completed 80000 read accesses @46020320 +system.cpu7: completed 80000 read accesses @46126230 +system.cpu5: completed 90000 read accesses @51539850 +system.cpu6: completed 90000 read accesses @51572100 +system.cpu4: completed 90000 read accesses @51579370 +system.cpu0: completed 90000 read accesses @51603670 +system.cpu3: completed 90000 read accesses @51633670 +system.cpu2: completed 90000 read accesses @51656890 +system.cpu1: completed 90000 read accesses @51768690 +system.cpu7: completed 90000 read accesses @51933040 +system.cpu5: completed 100000 read accesses @57251340 hack: be nice to actually delete the event here diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout index 5cb14d0de..1c1816479 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 20 2010 12:21:09 -M5 revision c4b5df973361+ 7570+ default qtip tip brad/regress_updates -M5 started Aug 20 2010 13:38:22 -M5 executing on SC2B0629 +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:38 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 11059012 because maximum number of loads reached +Exiting @ tick 57251340 because maximum number of loads reached diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt index 09849fe3c..4df469f73 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 341104 # Number of bytes of host memory used -host_seconds 68.57 # Real time elapsed on the host -host_tick_rate 161272 # Simulator tick rate (ticks/s) +host_mem_usage 363908 # Number of bytes of host memory used +host_seconds 189.81 # Real time elapsed on the host +host_tick_rate 301617 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks -sim_seconds 0.011059 # Number of seconds simulated -sim_ticks 11059012 # Number of ticks simulated +sim_seconds 0.057251 # Number of seconds simulated +sim_ticks 57251340 # Number of ticks simulated system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 99622 # number of read accesses completed -system.cpu0.num_writes 53973 # number of write accesses completed +system.cpu0.num_reads 99892 # number of read accesses completed +system.cpu0.num_writes 53261 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99717 # number of read accesses completed -system.cpu1.num_writes 53880 # number of write accesses completed +system.cpu1.num_reads 99647 # number of read accesses completed +system.cpu1.num_writes 53706 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 99983 # number of read accesses completed -system.cpu2.num_writes 53618 # number of write accesses completed +system.cpu2.num_reads 99764 # number of read accesses completed +system.cpu2.num_writes 53616 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99512 # number of read accesses completed -system.cpu3.num_writes 54081 # number of write accesses completed +system.cpu3.num_reads 99684 # number of read accesses completed +system.cpu3.num_writes 53704 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 100000 # number of read accesses completed -system.cpu4.num_writes 53593 # number of write accesses completed +system.cpu4.num_reads 99856 # number of read accesses completed +system.cpu4.num_writes 53900 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99946 # number of read accesses completed -system.cpu5.num_writes 53647 # number of write accesses completed +system.cpu5.num_reads 100000 # number of read accesses completed +system.cpu5.num_writes 53611 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99718 # number of read accesses completed -system.cpu6.num_writes 53875 # number of write accesses completed +system.cpu6.num_reads 99838 # number of read accesses completed +system.cpu6.num_writes 54123 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 99976 # number of read accesses completed -system.cpu7.num_writes 53616 # number of write accesses completed +system.cpu7.num_reads 99183 # number of read accesses completed +system.cpu7.num_writes 53528 # number of write accesses completed ---------- End Simulation Statistics ---------- diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini index 5a4805332..4e966d986 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem l2c membus physmem toL2Bus mem_mode=timing physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu0] type=MemTest diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout index 073fadf83..f3966712d 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 20 2010 15:04:49 -M5 revision 0c4a7d867247 7686 default qtip print-identical tip -M5 started Sep 20 2010 15:50:04 -M5 executing on phenom -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:38 +M5 executing on burrito +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Exiting @ tick 263488655 because maximum number of loads reached diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt index 54a425295..cebf442c3 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -1,8 +1,8 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 318984 # Number of bytes of host memory used -host_seconds 150.28 # Real time elapsed on the host -host_tick_rate 1753313 # Simulator tick rate (ticks/s) +host_mem_usage 349812 # Number of bytes of host memory used +host_seconds 357.32 # Real time elapsed on the host +host_tick_rate 737410 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_seconds 0.000263 # Number of seconds simulated sim_ticks 263488655 # Number of ticks simulated diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini index 2e46bddba..247e64cce 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 [system] type=System -children=dir_cntrl0 l1_cntrl0 physmem ruby +children=dir_cntrl0 l1_cntrl0 physmem ruby tester mem_mode=timing physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.dir_cntrl0] type=Directory_Controller @@ -52,38 +61,16 @@ version=0 [system.l1_cntrl0] type=L1Cache_Controller -children=sequencer buffer_size=0 -cacheMemory=system.l1_cntrl0.sequencer.icache +cacheMemory=system.ruby.cpu_ruby_ports.dcache cache_response_latency=12 issue_latency=2 number_of_TBEs=256 recycle_latency=10 -sequencer=system.l1_cntrl0.sequencer +sequencer=system.ruby.cpu_ruby_ports transitions_per_cycle=32 version=0 -[system.l1_cntrl0.sequencer] -type=RubySequencer -children=icache -dcache=system.l1_cntrl0.sequencer.icache -deadlock_threshold=500000 -icache=system.l1_cntrl0.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=true -version=0 -physMemPort=system.physmem.port[0] -port=root.cpuPort[0] - -[system.l1_cntrl0.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 -start_index_bit=6 - [system.physmem] type=PhysicalMemory file= @@ -92,14 +79,13 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.l1_cntrl0.sequencer.physMemPort +port=system.ruby.cpu_ruby_ports.physMemPort [system.ruby] type=RubySystem -children=debug network profiler tracer +children=cpu_ruby_ports network profiler tracer block_size_bytes=64 clock=1 -debug=system.ruby.debug mem_size=134217728 network=system.ruby.network no_mem_vec=false @@ -109,13 +95,27 @@ randomization=true stats_filename=ruby.stats tracer=system.ruby.tracer -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none +[system.ruby.cpu_ruby_ports] +type=RubySequencer +children=dcache +access_phys_mem=true +dcache=system.ruby.cpu_ruby_ports.dcache +deadlock_threshold=500000 +icache=system.ruby.cpu_ruby_ports.dcache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=true +version=0 +physMemPort=system.physmem.port[0] +port=system.tester.cpuPort[0] + +[system.ruby.cpu_ruby_ports.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 [system.ruby.network] type=SimpleNetwork @@ -131,9 +131,9 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology children=ext_links0 ext_links1 int_links0 int_links1 +description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 -name=Crossbar num_int_nodes=3 print_config=false @@ -179,3 +179,10 @@ num_of_sequencers=1 type=RubyTracer warmup_length=100000 +[system.tester] +type=RubyTester +checks_to_complete=100 +deadlock_threshold=50000 +wakeup_frequency=10 +cpuPort=system.ruby.cpu_ruby_ports.port[0] + diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats index 4b8c316dc..ce11e4002 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats @@ -13,7 +13,7 @@ RubySystem config: Network Configuration --------------------- network: SIMPLE_NETWORK -topology: Crossbar +topology: virtual_net_0: active, ordered virtual_net_1: active, ordered @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Aug/05/2010 10:10:57 +Real time: Feb/07/2011 01:47:37 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.29 -Virtual_time_in_minutes: 0.00483333 -Virtual_time_in_hours: 8.05556e-05 -Virtual_time_in_days: 3.35648e-06 +Virtual_time_in_seconds: 0.3 +Virtual_time_in_minutes: 0.005 +Virtual_time_in_hours: 8.33333e-05 +Virtual_time_in_days: 3.47222e-06 Ruby_current_time: 281031 Ruby_start_time: 0 Ruby_cycles: 281031 -mbytes_resident: 30.9531 -mbytes_total: 203.703 -resident_ratio: 0.15199 +mbytes_resident: 34.3867 +mbytes_total: 225.355 +resident_ratio: 0.152606 ruby_cycles_executed: [ 281032 ] @@ -122,11 +122,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 9003 +page_reclaims: 9878 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 0 +block_outputs: 48 Network Stats ------------- @@ -170,18 +170,18 @@ links_utilized_percent_switch_2: 0.169999 outgoing_messages_switch_2_link_1_Control: 957 7656 [ 0 0 957 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Data: 954 68688 [ 0 0 954 0 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.l1_cntrl0.sequencer.icache - system.l1_cntrl0.sequencer.icache_total_misses: 957 - system.l1_cntrl0.sequencer.icache_total_demand_misses: 957 - system.l1_cntrl0.sequencer.icache_total_prefetches: 0 - system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 - system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.ruby.cpu_ruby_ports.dcache + system.ruby.cpu_ruby_ports.dcache_total_misses: 957 + system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 957 + system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0 + system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0 + system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0 - system.l1_cntrl0.sequencer.icache_request_type_LD: 4.91118% - system.l1_cntrl0.sequencer.icache_request_type_ST: 89.7597% - system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 5.32915% + system.ruby.cpu_ruby_ports.dcache_request_type_LD: 4.91118% + system.ruby.cpu_ruby_ports.dcache_request_type_ST: 89.7597% + system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH: 5.32915% - system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 957 100% + system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 957 100% --- L1Cache --- - Event Counts - diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout index 566ba5c1a..e67c01bd9 100755 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 4 2010 17:29:21 -M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip -M5 started Aug 5 2010 10:10:57 -M5 executing on SC2B0617 +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:37 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt index 104ae3de6..e1f5ad3f1 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt @@ -1,8 +1,8 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 208596 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -host_tick_rate 3195386 # Simulator tick rate (ticks/s) +host_mem_usage 230768 # Number of bytes of host memory used +host_seconds 0.30 # Real time elapsed on the host +host_tick_rate 934733 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_seconds 0.000281 # Number of seconds simulated sim_ticks 281031 # Number of ticks simulated diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini index 84f87c01b..540e1709f 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini @@ -3,17 +3,24 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus membus physmem simple_disk terminal tsunami boot_cpu_frequency=1 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/chips/pd/randd/dist/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/chips/pd/randd/dist/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=atomic -pal=/chips/pd/randd/dist/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=drivesys.physmem -readfile=/arm/scratch/alisai01/m5/configs/boot/netperf-server.rcS +readfile=/home/gblack/m5/repos/m5.x86fs/configs/boot/netperf-server.rcS symbolfile= system_rev=1024 system_type=34 +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [drivesys.bridge] type=Bridge @@ -91,7 +98,7 @@ table_size=65536 [drivesys.disk0.image.child] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [drivesys.disk2] @@ -111,7 +118,7 @@ table_size=65536 [drivesys.disk2.image.child] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [drivesys.intrctrl] @@ -175,7 +182,7 @@ system=drivesys [drivesys.simple_disk.disk] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [drivesys.terminal] @@ -637,7 +644,9 @@ SubsystemID=0 SubsystemVendorID=0 VendorID=32902 config_latency=20000 +ctrl_offset=0 disks=drivesys.disk0 drivesys.disk2 +io_shift=0 max_backoff_delay=10000000 min_backoff_delay=4000 pci_bus=0 @@ -706,24 +715,33 @@ int1=drivesys.tsunami.ethernet.interface [root] type=Root children=drivesys etherdump etherlink testsys -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [testsys] type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus membus physmem simple_disk terminal tsunami boot_cpu_frequency=1 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/chips/pd/randd/dist/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/chips/pd/randd/dist/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=atomic -pal=/chips/pd/randd/dist/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=testsys.physmem -readfile=/arm/scratch/alisai01/m5/configs/boot/netperf-stream-client.rcS +readfile=/home/gblack/m5/repos/m5.x86fs/configs/boot/netperf-stream-client.rcS symbolfile= system_rev=1024 system_type=34 +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [testsys.bridge] type=Bridge @@ -801,7 +819,7 @@ table_size=65536 [testsys.disk0.image.child] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [testsys.disk2] @@ -821,7 +839,7 @@ table_size=65536 [testsys.disk2.image.child] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [testsys.intrctrl] @@ -885,7 +903,7 @@ system=testsys [testsys.simple_disk.disk] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [testsys.terminal] @@ -1347,7 +1365,9 @@ SubsystemID=0 SubsystemVendorID=0 VendorID=32902 config_latency=20000 +ctrl_offset=0 disks=testsys.disk0 testsys.disk2 +io_shift=0 max_backoff_delay=10000000 min_backoff_delay=4000 pci_bus=0 diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr index c18ca3505..d5294a000 100755 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr @@ -2,6 +2,10 @@ warn: Sockets disabled, not accepting terminal connections For more information see: http://www.m5sim.org/warn/8742226b warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba warn: Obsolete M5 ivlb instruction encountered. For more information see: http://www.m5sim.org/warn/fcbd217d hack: be nice to actually delete the event here diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout index 2dcdfae87..62b569073 100755 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic/simout -Redirecting stderr to build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 2 2010 23:00:12 -M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip -M5 started Nov 2 2010 23:11:17 -M5 executing on aus-bc2-b15 +M5 compiled Feb 7 2011 01:46:17 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:46:32 +M5 executing on burrito command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux -info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... Exiting @ tick 4300236804024 because checkpoint diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt index 9fb1ef54c..a776ca423 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt @@ -93,8 +93,24 @@ drivesys.cpu.kern.syscall::150 1 4.55% 100.00% # nu drivesys.cpu.kern.syscall::total 22 # number of syscalls executed drivesys.cpu.not_idle_fraction 0.000010 # Percentage of non-idle cycles drivesys.cpu.numCycles 199571362884 # number of cpu cycles simulated +drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started +drivesys.cpu.num_busy_cycles 1954747.881971 # Number of busy cycles +drivesys.cpu.num_conditional_control_insts 161093 # number of instructions that are conditional controls +drivesys.cpu.num_fp_alu_accesses 1278 # Number of float alu accesses +drivesys.cpu.num_fp_insts 1278 # number of float instructions +drivesys.cpu.num_fp_register_reads 694 # number of times the floating registers were read +drivesys.cpu.num_fp_register_writes 698 # number of times the floating registers were written +drivesys.cpu.num_func_calls 121650 # number of times a function call or return occured +drivesys.cpu.num_idle_cycles 199569408136.118042 # Number of idle cycles drivesys.cpu.num_insts 1958129 # Number of instructions executed -drivesys.cpu.num_refs 625939 # Number of memory references +drivesys.cpu.num_int_alu_accesses 1889973 # Number of integer alu accesses +drivesys.cpu.num_int_insts 1889973 # number of integer instructions +drivesys.cpu.num_int_register_reads 2411030 # number of times the integer registers were read +drivesys.cpu.num_int_register_writes 1442447 # number of times the integer registers were written +drivesys.cpu.num_load_insts 394697 # Number of load instructions +drivesys.cpu.num_mem_refs 625939 # number of memory refs +drivesys.cpu.num_store_insts 231242 # Number of store instructions drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -156,10 +172,10 @@ drivesys.tsunami.ethernet.txPPS 25 # Pa drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -host_inst_rate 245765975 # Simulator instruction rate (inst/s) -host_mem_usage 512700 # Number of bytes of host memory used -host_seconds 1.11 # Real time elapsed on the host -host_tick_rate 179775828937 # Simulator tick rate (ticks/s) +host_inst_rate 71982907 # Simulator instruction rate (inst/s) +host_mem_usage 498216 # Number of bytes of host memory used +host_seconds 3.80 # Real time elapsed on the host +host_tick_rate 52659325700 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 273374833 # Number of instructions simulated sim_seconds 0.200001 # Number of seconds simulated @@ -267,8 +283,24 @@ testsys.cpu.kern.syscall::118 2 2.41% 100.00% # nu testsys.cpu.kern.syscall::total 83 # number of syscalls executed testsys.cpu.not_idle_fraction 0.000018 # Percentage of non-idle cycles testsys.cpu.numCycles 199569460393 # number of cpu cycles simulated +testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started +testsys.cpu.num_busy_cycles 3558262.534294 # Number of busy cycles +testsys.cpu.num_conditional_control_insts 361828 # number of instructions that are conditional controls +testsys.cpu.num_fp_alu_accesses 17380 # Number of float alu accesses +testsys.cpu.num_fp_insts 17380 # number of float instructions +testsys.cpu.num_fp_register_reads 11166 # number of times the floating registers were read +testsys.cpu.num_fp_register_writes 10823 # number of times the floating registers were written +testsys.cpu.num_func_calls 107994 # number of times a function call or return occured +testsys.cpu.num_idle_cycles 199565902130.465698 # Number of idle cycles testsys.cpu.num_insts 3560411 # Number of instructions executed -testsys.cpu.num_refs 1173234 # Number of memory references +testsys.cpu.num_int_alu_accesses 3348322 # Number of integer alu accesses +testsys.cpu.num_int_insts 3348322 # number of integer instructions +testsys.cpu.num_int_register_reads 4592571 # number of times the integer registers were read +testsys.cpu.num_int_register_writes 2442795 # number of times the integer registers were written +testsys.cpu.num_load_insts 666253 # Number of load instructions +testsys.cpu.num_mem_refs 1173234 # number of memory refs +testsys.cpu.num_store_insts 506981 # Number of store instructions testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -386,8 +418,24 @@ drivesys.cpu.kern.mode_ticks::idle 0 # nu drivesys.cpu.kern.swap_context 0 # number of times the context was actually changed drivesys.cpu.not_idle_fraction 0 # Percentage of non-idle cycles drivesys.cpu.numCycles 0 # number of cpu cycles simulated +drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started +drivesys.cpu.num_busy_cycles 0 # Number of busy cycles +drivesys.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +drivesys.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +drivesys.cpu.num_fp_insts 0 # number of float instructions +drivesys.cpu.num_fp_register_reads 0 # number of times the floating registers were read +drivesys.cpu.num_fp_register_writes 0 # number of times the floating registers were written +drivesys.cpu.num_func_calls 0 # number of times a function call or return occured +drivesys.cpu.num_idle_cycles 0 # Number of idle cycles drivesys.cpu.num_insts 0 # Number of instructions executed -drivesys.cpu.num_refs 0 # Number of memory references +drivesys.cpu.num_int_alu_accesses 0 # Number of integer alu accesses +drivesys.cpu.num_int_insts 0 # number of integer instructions +drivesys.cpu.num_int_register_reads 0 # number of times the integer registers were read +drivesys.cpu.num_int_register_writes 0 # number of times the integer registers were written +drivesys.cpu.num_load_insts 0 # Number of load instructions +drivesys.cpu.num_mem_refs 0 # number of memory refs +drivesys.cpu.num_store_insts 0 # Number of store instructions drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -431,10 +479,10 @@ drivesys.tsunami.ethernet.totalSwi 0 # to drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -host_inst_rate 151538155765 # Simulator instruction rate (inst/s) -host_mem_usage 512700 # Number of bytes of host memory used +host_inst_rate 86035621838 # Simulator instruction rate (inst/s) +host_mem_usage 498216 # Number of bytes of host memory used host_seconds 0.00 # Real time elapsed on the host -host_tick_rate 415641460 # Simulator tick rate (ticks/s) +host_tick_rate 235143018 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 273374833 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated @@ -491,8 +539,24 @@ testsys.cpu.kern.mode_ticks::idle 0 # nu testsys.cpu.kern.swap_context 0 # number of times the context was actually changed testsys.cpu.not_idle_fraction 0 # Percentage of non-idle cycles testsys.cpu.numCycles 0 # number of cpu cycles simulated +testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started +testsys.cpu.num_busy_cycles 0 # Number of busy cycles +testsys.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +testsys.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +testsys.cpu.num_fp_insts 0 # number of float instructions +testsys.cpu.num_fp_register_reads 0 # number of times the floating registers were read +testsys.cpu.num_fp_register_writes 0 # number of times the floating registers were written +testsys.cpu.num_func_calls 0 # number of times a function call or return occured +testsys.cpu.num_idle_cycles 0 # Number of idle cycles testsys.cpu.num_insts 0 # Number of instructions executed -testsys.cpu.num_refs 0 # Number of memory references +testsys.cpu.num_int_alu_accesses 0 # Number of integer alu accesses +testsys.cpu.num_int_insts 0 # number of integer instructions +testsys.cpu.num_int_register_reads 0 # number of times the integer registers were read +testsys.cpu.num_int_register_writes 0 # number of times the integer registers were written +testsys.cpu.num_load_insts 0 # Number of load instructions +testsys.cpu.num_mem_refs 0 # number of memory refs +testsys.cpu.num_store_insts 0 # Number of store instructions testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). |