diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:25 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:25 -0500 |
| commit | 1114be4b78c0855d96004b9f71c61d4b6a050d3a (patch) | |
| tree | eb1e2047d27bd31626530cae97cd9224e1dbbb11 /tests/quick | |
| parent | 7dde557fdc51140988092962137e1006d1609bea (diff) | |
| download | gem5-1114be4b78c0855d96004b9f71c61d4b6a050d3a.tar.xz | |
O3: Update stats for memory order violation checking patch.
Diffstat (limited to 'tests/quick')
28 files changed, 3812 insertions, 3792 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 6d12585e0..694ecbd33 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -115,6 +115,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -413,6 +414,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -448,6 +450,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=1000 max_miss_count=0 mshrs=10 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout index 517aaa9a6..99080254c 100755 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout @@ -5,13 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:37 -M5 executing on burrito +M5 compiled Mar 17 2011 21:44:37 +M5 started Mar 17 2011 21:44:43 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 12412500 because target called exit() +Exiting @ tick 12357500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt index eda10e1bd..614787416 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 34686 # Simulator instruction rate (inst/s) -host_mem_usage 223912 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host -host_tick_rate 67319594 # Simulator tick rate (ticks/s) +host_inst_rate 83889 # Simulator instruction rate (inst/s) +host_mem_usage 205772 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host +host_tick_rate 161742329 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6386 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12412500 # Number of ticks simulated +sim_ticks 12357500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 680 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 1800 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 670 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1765 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 65 # Number of incorrect RAS predictions. system.cpu.BPredUnit.condIncorrect 443 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 1320 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 2222 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 313 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.condPredicted 1297 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2180 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 306 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 1051 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 117 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 127 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 12265 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.522055 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.306636 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 12090 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.529611 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.331978 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 9355 76.27% 76.27% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 1631 13.30% 89.57% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 489 3.99% 93.56% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 266 2.17% 95.73% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 144 1.17% 96.90% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 131 1.07% 97.97% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 95 0.77% 98.74% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 37 0.30% 99.05% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 117 0.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 9222 76.28% 76.28% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 1613 13.34% 89.62% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 453 3.75% 93.37% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 264 2.18% 95.55% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 157 1.30% 96.85% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 121 1.00% 97.85% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 88 0.73% 98.58% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 45 0.37% 98.95% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 127 1.05% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 12265 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 12090 # Number of insts commited each cycle system.cpu.commit.COM:count 6403 # Number of instructions committed system.cpu.commit.COM:fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 127 # Number of function calls committed. @@ -47,348 +47,348 @@ system.cpu.commit.COM:swp_count 0 # Nu system.cpu.commit.branchMispredicts 369 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4518 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4249 # The number of squashed insts skipped by commit system.cpu.committedInsts 6386 # Number of Instructions Simulated system.cpu.committedInsts_total 6386 # Number of Instructions Simulated -system.cpu.cpi 3.887567 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.887567 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1765 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 35761.146497 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36257.425743 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1608 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5614500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.088952 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 157 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 56 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 3662000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.057224 # mshr miss rate for ReadReq accesses +system.cpu.cpi 3.870341 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.870341 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1705 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 36146.666667 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36227.722772 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1555 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 5422000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.087977 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 150 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 49 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 3659000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.059238 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 34971.751412 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35815.068493 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 511 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 12380000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.409249 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 354 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 281 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2614500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 35022.471910 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35883.561644 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 509 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 12468000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.411561 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 356 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2619500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 12.178161 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11.862069 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2630 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 35214.285714 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 36071.839080 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2119 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 17994500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.194297 # miss rate for demand accesses -system.cpu.dcache.demand_misses 511 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 337 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 6276500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.066160 # mshr miss rate for demand accesses +system.cpu.dcache.demand_accesses 2570 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 35355.731225 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 36083.333333 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2064 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 17890000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.196887 # miss rate for demand accesses +system.cpu.dcache.demand_misses 506 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 332 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 6278500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.067704 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 174 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.026868 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 110.049713 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 2630 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 35214.285714 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 36071.839080 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.026841 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 109.940770 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 2570 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 35355.731225 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 36083.333333 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2119 # number of overall hits -system.cpu.dcache.overall_miss_latency 17994500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.194297 # miss rate for overall accesses -system.cpu.dcache.overall_misses 511 # number of overall misses -system.cpu.dcache.overall_mshr_hits 337 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 6276500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.066160 # mshr miss rate for overall accesses +system.cpu.dcache.overall_hits 2064 # number of overall hits +system.cpu.dcache.overall_miss_latency 17890000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.196887 # miss rate for overall accesses +system.cpu.dcache.overall_misses 506 # number of overall misses +system.cpu.dcache.overall_mshr_hits 332 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 6278500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.067704 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 174 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 110.049713 # Cycle average of tags in use -system.cpu.dcache.total_refs 2119 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 109.940770 # Cycle average of tags in use +system.cpu.dcache.total_refs 2064 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1016 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BlockedCycles 1035 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 75 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12350 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 8913 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2277 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 884 # Number of cycles decode is squashing +system.cpu.decode.DECODE:BranchResolved 181 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12021 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 8780 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2228 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 825 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 209 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 59 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 2921 # DTB accesses +system.cpu.decode.DECODE:UnblockCycles 47 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 2822 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 2860 # DTB hits +system.cpu.dtb.data_hits 2761 # DTB hits system.cpu.dtb.data_misses 61 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 1845 # DTB read accesses +system.cpu.dtb.read_accesses 1786 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 1809 # DTB read hits +system.cpu.dtb.read_hits 1750 # DTB read hits system.cpu.dtb.read_misses 36 # DTB read misses -system.cpu.dtb.write_accesses 1076 # DTB write accesses +system.cpu.dtb.write_accesses 1036 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 1051 # DTB write hits +system.cpu.dtb.write_hits 1011 # DTB write hits system.cpu.dtb.write_misses 25 # DTB write misses -system.cpu.fetch.Branches 2222 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1774 # Number of cache lines fetched -system.cpu.fetch.Cycles 2385 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 267 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13186 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 503 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.089503 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1774 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 993 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.531137 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 13149 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.002814 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.396074 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 2180 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1711 # Number of cache lines fetched +system.cpu.fetch.Cycles 2325 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 248 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 12863 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 482 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.088202 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1711 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 976 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.520432 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 12915 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.995974 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.389736 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10764 81.86% 81.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 240 1.83% 83.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 218 1.66% 85.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 183 1.39% 86.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 231 1.76% 88.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 163 1.24% 89.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 224 1.70% 91.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 130 0.99% 92.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 996 7.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10590 82.00% 82.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 233 1.80% 83.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 211 1.63% 85.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 179 1.39% 86.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 229 1.77% 88.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 156 1.21% 89.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 218 1.69% 91.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 125 0.97% 92.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 974 7.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13149 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 12915 # Number of instructions fetched each cycle (Total) system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 1774 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35292.253521 # average ReadReq miss latency +system.cpu.icache.ReadReq_accesses 1711 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35919.512195 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35283.387622 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1348 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15034500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.240135 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 426 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 119 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_hits 1301 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 14727000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.239626 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 410 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 103 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_miss_latency 10832000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.173055 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.179427 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 4.390879 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.237785 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1774 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35292.253521 # average overall miss latency +system.cpu.icache.demand_accesses 1711 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35919.512195 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency -system.cpu.icache.demand_hits 1348 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15034500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.240135 # miss rate for demand accesses -system.cpu.icache.demand_misses 426 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 119 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_hits 1301 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 14727000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.239626 # miss rate for demand accesses +system.cpu.icache.demand_misses 410 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 103 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 10832000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.173055 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.179427 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 307 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.077067 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 157.832479 # Average occupied blocks per context -system.cpu.icache.overall_accesses 1774 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35292.253521 # average overall miss latency +system.cpu.icache.occ_%::0 0.076986 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 157.666490 # Average occupied blocks per context +system.cpu.icache.overall_accesses 1711 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35919.512195 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1348 # number of overall hits -system.cpu.icache.overall_miss_latency 15034500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.240135 # miss rate for overall accesses -system.cpu.icache.overall_misses 426 # number of overall misses -system.cpu.icache.overall_mshr_hits 119 # number of overall MSHR hits +system.cpu.icache.overall_hits 1301 # number of overall hits +system.cpu.icache.overall_miss_latency 14727000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.239626 # miss rate for overall accesses +system.cpu.icache.overall_misses 410 # number of overall misses +system.cpu.icache.overall_mshr_hits 103 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 10832000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.173055 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.179427 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 307 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 157.832479 # Cycle average of tags in use -system.cpu.icache.total_refs 1348 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 157.666490 # Cycle average of tags in use +system.cpu.icache.total_refs 1301 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 11677 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1435 # Number of branches executed +system.cpu.idleCycles 11801 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1424 # Number of branches executed system.cpu.iew.EXEC:nop 82 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.361798 # Inst execution rate -system.cpu.iew.EXEC:refs 2929 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1078 # Number of stores executed +system.cpu.iew.EXEC:rate 0.357542 # Inst execution rate +system.cpu.iew.EXEC:refs 2832 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1038 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 6007 # num instructions consuming a value -system.cpu.iew.WB:count 8682 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.744798 # average fanout of values written-back +system.cpu.iew.WB:consumers 5952 # num instructions consuming a value +system.cpu.iew.WB:count 8559 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.744120 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4474 # num instructions producing a value -system.cpu.iew.WB:rate 0.349714 # insts written-back per cycle -system.cpu.iew.WB:sent 8783 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 428 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 63 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2242 # Number of dispatched load instructions +system.cpu.iew.WB:producers 4429 # num instructions producing a value +system.cpu.iew.WB:rate 0.346294 # insts written-back per cycle +system.cpu.iew.WB:sent 8658 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 429 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 67 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2144 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 193 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1259 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 10955 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1851 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 291 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 8982 # Number of executed instructions +system.cpu.iew.iewDispStoreInsts 1195 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 10669 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1794 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 271 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8837 # Number of executed instructions system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 884 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 825 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 43 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.forwLoads 44 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 63 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 16 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1057 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 394 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 63 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 303 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.lsq.thread.0.squashedLoads 959 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 330 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 304 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 11489 # number of integer regfile reads -system.cpu.int_regfile_writes 6462 # number of integer regfile writes -system.cpu.ipc 0.257230 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.257230 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 11291 # number of integer regfile reads +system.cpu.int_regfile_writes 6385 # number of integer regfile writes +system.cpu.ipc 0.258375 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.258375 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 6230 67.18% 67.21% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 67.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 67.24% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 1943 20.95% 88.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1095 11.81% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 6174 67.79% 67.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 67.82% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 67.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 1875 20.59% 88.43% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1054 11.57% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 9273 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 91 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.009813 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 9108 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 88 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.009662 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 1 1.10% 1.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 1.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 1.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 1.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 1.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 1.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 1.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 1.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 1.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 1.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 1.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 1.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 1.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 1.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 1.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 1.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 1.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 1.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 1.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 1.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 1.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 1.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 55 60.44% 61.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 35 38.46% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 1 1.14% 1.14% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 52 59.09% 60.23% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 35 39.77% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 13149 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.705225 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.302669 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 12915 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.705226 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.305176 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 8989 68.36% 68.36% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 1668 12.69% 81.05% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 1105 8.40% 89.45% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 696 5.29% 94.74% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 356 2.71% 97.45% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 185 1.41% 98.86% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 104 0.79% 99.65% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 34 0.26% 99.91% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 8840 68.45% 68.45% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 1652 12.79% 81.24% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 1039 8.04% 89.28% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 684 5.30% 94.58% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 367 2.84% 97.42% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 198 1.53% 98.95% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 88 0.68% 99.64% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 36 0.28% 99.91% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 11 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 13149 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.373520 # Inst issue rate +system.cpu.iq.ISSUE:issued_per_cycle::total 12915 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.368506 # Inst issue rate system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 9351 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 31807 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 8672 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 14983 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 10848 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 9273 # Number of instructions issued +system.cpu.iq.int_alu_accesses 9183 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 31223 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 8549 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 14386 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 10562 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 9108 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 4076 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 42 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3797 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 25 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2476 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 2286 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 1808 # ITB accesses +system.cpu.itb.fetch_accesses 1744 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 1774 # ITB hits -system.cpu.itb.fetch_misses 34 # ITB misses +system.cpu.itb.fetch_hits 1711 # ITB hits +system.cpu.itb.fetch_misses 33 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -398,22 +398,22 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34506.849315 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31424.657534 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2519000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 34493.150685 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31383.561644 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2518000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2294000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2291000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34420.147420 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31243.243243 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34409.090909 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31228.501229 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 14009000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 14004500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.997549 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 407 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12716000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 12710000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997549 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 407 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -425,31 +425,31 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34433.333333 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31270.833333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 34421.875000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31252.083333 # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 16528000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 16522500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.997921 # miss rate for demand accesses system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 15010000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 15001000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.997921 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.006704 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 219.690126 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.006698 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 219.485914 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34433.333333 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31270.833333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 34421.875000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31252.083333 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 16528000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 16522500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses system.cpu.l2cache.overall_misses 480 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 15010000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 15001000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -457,40 +457,40 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 407 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 219.690126 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 219.485914 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 34 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 26 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 2242 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1259 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 2144 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1195 # Number of stores inserted to the mem dependence unit. system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.numCycles 24826 # number of cpu cycles simulated +system.cpu.numCycles 24716 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 346 # Number of cycles rename is blocking +system.cpu.rename.RENAME:BlockCycles 337 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4583 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 8 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 9063 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 234 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 15033 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11933 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8883 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 2180 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 884 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 270 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4300 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:IdleCycles 8928 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 260 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 14615 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11616 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8669 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 2118 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 825 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 301 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4086 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:fp_rename_lookups 17 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 15016 # Number of integer rename lookups +system.cpu.rename.RENAME:int_rename_lookups 14598 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 406 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 28 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 694 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 754 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 22718 # The number of ROB reads -system.cpu.rob.rob_writes 22732 # The number of ROB writes -system.cpu.timesIdled 239 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rob.rob_reads 22264 # The number of ROB reads +system.cpu.rob.rob_writes 22135 # The number of ROB writes +system.cpu.timesIdled 240 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index e99d2d594..e2033d8c4 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -115,6 +115,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -413,6 +414,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -448,6 +450,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=1000 max_miss_count=0 mshrs=10 diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout index 8339eb49f..6c13eb8f5 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout @@ -5,13 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:49 -M5 executing on burrito +M5 compiled Mar 17 2011 21:44:37 +M5 started Mar 17 2011 21:45:02 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 7300000 because target called exit() +Exiting @ tick 7289000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index c17e16760..3fca93af7 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 33498 # Simulator instruction rate (inst/s) -host_mem_usage 222808 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host -host_tick_rate 102057061 # Simulator tick rate (ticks/s) +host_inst_rate 58135 # Simulator instruction rate (inst/s) +host_mem_usage 204672 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +host_tick_rate 176416397 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated sim_seconds 0.000007 # Number of seconds simulated -sim_ticks 7300000 # Number of ticks simulated +sim_ticks 7289000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 190 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 683 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 197 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 687 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 35 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 220 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 476 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 926 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 179 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.condIncorrect 223 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 485 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 931 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 174 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 396 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 35 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 41 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 6328 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.407080 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.186255 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 6308 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.408370 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.199072 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 5362 84.73% 84.73% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 264 4.17% 88.91% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 341 5.39% 94.30% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 139 2.20% 96.49% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 71 1.12% 97.61% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 66 1.04% 98.66% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 31 0.49% 99.15% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 19 0.30% 99.45% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 35 0.55% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 5350 84.81% 84.81% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 259 4.11% 88.92% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 343 5.44% 94.36% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 133 2.11% 96.46% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 72 1.14% 97.61% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 64 1.01% 98.62% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 26 0.41% 99.03% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 20 0.32% 99.35% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 41 0.65% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 6328 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 6308 # Number of insts commited each cycle system.cpu.commit.COM:count 2576 # Number of instructions committed system.cpu.commit.COM:fp_insts 6 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 71 # Number of function calls committed. @@ -44,24 +44,24 @@ system.cpu.commit.COM:loads 415 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 709 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 143 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 146 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1998 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1995 # The number of squashed insts skipped by commit system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 6.116883 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.116883 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 599 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 35045 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35696.721311 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 499 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3504500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.166945 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 100 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 39 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2177500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.101836 # mshr miss rate for ReadReq accesses +system.cpu.cpi 6.107667 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.107667 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 589 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 33939.814815 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35704.918033 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 481 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3665500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.183362 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 108 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 47 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2178000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.103565 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 38819.444444 # average WriteReq miss latency @@ -76,317 +76,317 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # m system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.482353 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 8.270588 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 893 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 36625 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35823.529412 # average overall mshr miss latency -system.cpu.dcache.demand_hits 721 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 6299500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.192609 # miss rate for demand accesses -system.cpu.dcache.demand_misses 172 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 87 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3045000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.095185 # mshr miss rate for demand accesses +system.cpu.dcache.demand_accesses 883 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 35891.666667 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35829.411765 # average overall mshr miss latency +system.cpu.dcache.demand_hits 703 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 6460500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.203851 # miss rate for demand accesses +system.cpu.dcache.demand_misses 180 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 95 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 3045500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.096263 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.011350 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 46.490005 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 893 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 36625 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35823.529412 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.011366 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 46.556735 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 883 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 35891.666667 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35829.411765 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 721 # number of overall hits -system.cpu.dcache.overall_miss_latency 6299500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.192609 # miss rate for overall accesses -system.cpu.dcache.overall_misses 172 # number of overall misses -system.cpu.dcache.overall_mshr_hits 87 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3045000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.095185 # mshr miss rate for overall accesses +system.cpu.dcache.overall_hits 703 # number of overall hits +system.cpu.dcache.overall_miss_latency 6460500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.203851 # miss rate for overall accesses +system.cpu.dcache.overall_misses 180 # number of overall misses +system.cpu.dcache.overall_mshr_hits 95 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 3045500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.096263 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 46.490005 # Cycle average of tags in use -system.cpu.dcache.total_refs 721 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 46.556735 # Cycle average of tags in use +system.cpu.dcache.total_refs 703 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 226 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BlockedCycles 217 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction system.cpu.decode.DECODE:BranchResolved 136 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 5050 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 5122 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 978 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 373 # Number of cycles decode is squashing +system.cpu.decode.DECODE:DecodedInsts 5047 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 5111 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 977 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 374 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 284 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 2 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 1016 # DTB accesses +system.cpu.decode.DECODE:UnblockCycles 3 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 1010 # DTB accesses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_hits 978 # DTB hits -system.cpu.dtb.data_misses 38 # DTB misses +system.cpu.dtb.data_hits 964 # DTB hits +system.cpu.dtb.data_misses 46 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 648 # DTB read accesses +system.cpu.dtb.read_accesses 644 # DTB read accesses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_hits 627 # DTB read hits -system.cpu.dtb.read_misses 21 # DTB read misses -system.cpu.dtb.write_accesses 368 # DTB write accesses +system.cpu.dtb.read_hits 617 # DTB read hits +system.cpu.dtb.read_misses 27 # DTB read misses +system.cpu.dtb.write_accesses 366 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 351 # DTB write hits -system.cpu.dtb.write_misses 17 # DTB write misses -system.cpu.fetch.Branches 926 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 782 # Number of cache lines fetched -system.cpu.fetch.Cycles 988 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 117 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 5752 # Number of instructions fetch has processed +system.cpu.dtb.write_hits 347 # DTB write hits +system.cpu.dtb.write_misses 19 # DTB write misses +system.cpu.fetch.Branches 931 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 777 # Number of cache lines fetched +system.cpu.fetch.Cycles 986 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 113 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 5745 # Number of instructions fetch has processed system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 249 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.063420 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 782 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 369 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.393946 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 6701 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.858379 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.271912 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.SquashCycles 246 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.063859 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 777 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 371 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.394060 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 6682 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.859773 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.273067 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 5713 85.26% 85.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 53 0.79% 86.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 100 1.49% 87.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 71 1.06% 88.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 125 1.87% 90.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 52 0.78% 91.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 55 0.82% 92.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 60 0.90% 92.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 472 7.04% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 5696 85.24% 85.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 43 0.64% 85.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 112 1.68% 87.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 72 1.08% 88.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 123 1.84% 90.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 53 0.79% 91.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 50 0.75% 92.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 59 0.88% 92.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 474 7.09% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 6701 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 6682 # Number of instructions fetched each cycle (Total) system.cpu.fp_regfile_reads 6 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 782 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 36074.786325 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35303.867403 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 548 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 8441500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.299233 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 234 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 53 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 6390000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.231458 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_accesses 777 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 36200.431034 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35306.629834 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 545 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 8398500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.298584 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 232 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 51 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 6390500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.232947 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 181 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.027624 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.011050 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 782 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 36074.786325 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35303.867403 # average overall mshr miss latency -system.cpu.icache.demand_hits 548 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 8441500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.299233 # miss rate for demand accesses -system.cpu.icache.demand_misses 234 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 53 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6390000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.231458 # mshr miss rate for demand accesses +system.cpu.icache.demand_accesses 777 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 36200.431034 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35306.629834 # average overall mshr miss latency +system.cpu.icache.demand_hits 545 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 8398500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.298584 # miss rate for demand accesses +system.cpu.icache.demand_misses 232 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 51 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 6390500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.232947 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 181 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.044097 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 90.310423 # Average occupied blocks per context -system.cpu.icache.overall_accesses 782 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 36074.786325 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35303.867403 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.044195 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 90.511194 # Average occupied blocks per context +system.cpu.icache.overall_accesses 777 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 36200.431034 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35306.629834 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 548 # number of overall hits -system.cpu.icache.overall_miss_latency 8441500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.299233 # miss rate for overall accesses -system.cpu.icache.overall_misses 234 # number of overall misses -system.cpu.icache.overall_mshr_hits 53 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6390000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.231458 # mshr miss rate for overall accesses +system.cpu.icache.overall_hits 545 # number of overall hits +system.cpu.icache.overall_miss_latency 8398500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.298584 # miss rate for overall accesses +system.cpu.icache.overall_misses 232 # number of overall misses +system.cpu.icache.overall_mshr_hits 51 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 6390500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.232947 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 181 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 181 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 90.310423 # Cycle average of tags in use -system.cpu.icache.total_refs 548 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 90.511194 # Cycle average of tags in use +system.cpu.icache.total_refs 545 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 7900 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 601 # Number of branches executed -system.cpu.iew.EXEC:nop 306 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.241079 # Inst execution rate -system.cpu.iew.EXEC:refs 1017 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 368 # Number of stores executed +system.cpu.idleCycles 7897 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 600 # Number of branches executed +system.cpu.iew.EXEC:nop 311 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.241855 # Inst execution rate +system.cpu.iew.EXEC:refs 1011 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 366 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1981 # num instructions consuming a value -system.cpu.iew.WB:count 3402 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.795558 # average fanout of values written-back +system.cpu.iew.WB:consumers 1995 # num instructions consuming a value +system.cpu.iew.WB:count 3404 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.790977 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1576 # num instructions producing a value -system.cpu.iew.WB:rate 0.232998 # insts written-back per cycle -system.cpu.iew.WB:sent 3452 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 164 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 55 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 793 # Number of dispatched load instructions +system.cpu.iew.WB:producers 1578 # num instructions producing a value +system.cpu.iew.WB:rate 0.233487 # insts written-back per cycle +system.cpu.iew.WB:sent 3463 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 171 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 48 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 779 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 68 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 435 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 4588 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 649 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 111 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 3520 # Number of executed instructions +system.cpu.iew.iewDispSquashedInsts 58 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 428 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 4585 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 645 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 109 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 3526 # Number of executed instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 373 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 374 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 3 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 28 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 13 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 4 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 378 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 141 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 109 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 55 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 4283 # number of integer regfile reads -system.cpu.int_regfile_writes 2601 # number of integer regfile writes -system.cpu.ipc 0.163482 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.163482 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.squashedLoads 364 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 134 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 4 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 118 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 4291 # number of integer regfile reads +system.cpu.int_regfile_writes 2610 # number of integer regfile writes +system.cpu.ipc 0.163729 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.163729 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 2584 71.16% 71.16% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.03% 71.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 71.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 71.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 71.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 71.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 71.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 71.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 71.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 71.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 71.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 71.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 71.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 71.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 71.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 71.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 71.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 71.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 71.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 71.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 71.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 71.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 71.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 71.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 71.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 673 18.53% 89.73% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 373 10.27% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 2594 71.36% 71.36% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.03% 71.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 71.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 669 18.40% 89.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 371 10.21% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 3631 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.009639 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 3635 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 32 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.008803 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 1 2.86% 2.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 12 34.29% 37.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 22 62.86% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 1 3.12% 3.12% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 9 28.12% 31.25% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 22 68.75% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 6701 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.541859 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.220931 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 6682 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.543999 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.232060 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 5144 76.76% 76.76% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 631 9.42% 86.18% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 352 5.25% 91.43% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 241 3.60% 95.03% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 180 2.69% 97.72% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 94 1.40% 99.12% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 38 0.57% 99.69% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 13 0.19% 99.88% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 8 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 5130 76.77% 76.77% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 639 9.56% 86.34% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 335 5.01% 91.35% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 242 3.62% 94.97% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 178 2.66% 97.64% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 94 1.41% 99.04% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 39 0.58% 99.63% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 16 0.24% 99.87% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 9 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 6701 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.248682 # Inst issue rate +system.cpu.iq.ISSUE:issued_per_cycle::total 6682 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.249331 # Inst issue rate system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 3659 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 14008 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 3396 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 5997 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 4276 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 3631 # Number of instructions issued +system.cpu.iq.int_alu_accesses 3660 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 14000 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 3398 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 5975 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 4268 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 3635 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1710 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1704 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 29 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 972 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 959 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 811 # ITB accesses +system.cpu.itb.fetch_accesses 806 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 782 # ITB hits +system.cpu.itb.fetch_hits 777 # ITB hits system.cpu.itb.fetch_misses 29 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations @@ -406,12 +406,12 @@ system.cpu.l2cache.ReadExReq_mshr_miss_latency 756000 system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 242 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34322.314050 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31132.231405 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 8306000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 34326.446281 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31144.628099 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 8307000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 242 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 7534000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 7537000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 242 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -423,31 +423,31 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 266 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34347.744361 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31165.413534 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 34351.503759 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31176.691729 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9136500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 9137500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 266 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 8290000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 8293000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 266 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.003651 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 119.628373 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.003658 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 119.871330 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 266 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34347.744361 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31165.413534 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 34351.503759 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31176.691729 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9136500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 9137500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 266 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 8290000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 8293000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 266 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -455,40 +455,40 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 242 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 119.628373 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 119.871330 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 16 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 16 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 793 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 435 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 779 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 428 # Number of stores inserted to the mem dependence unit. system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.numCycles 14601 # number of cpu cycles simulated +system.cpu.numCycles 14579 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 63 # Number of cycles rename is blocking +system.cpu.rename.RENAME:BlockCycles 55 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 3 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 5203 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 3 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 5514 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 4876 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 3481 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 5189 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 5515 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 4879 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 3490 # Number of destination operands rename has renamed system.cpu.rename.RENAME:RunCycles 901 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 373 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 15 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1713 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:SquashCycles 374 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 17 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1722 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:fp_rename_lookups 12 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 5502 # Number of integer rename lookups +system.cpu.rename.RENAME:int_rename_lookups 5503 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 146 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 78 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 74 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 10620 # The number of ROB reads -system.cpu.rob.rob_writes 9524 # The number of ROB writes -system.cpu.timesIdled 152 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rob.rob_reads 10591 # The number of ROB reads +system.cpu.rob.rob_writes 9519 # The number of ROB writes +system.cpu.timesIdled 151 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini index 6bf13d8ce..82f1d72df 100644 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini @@ -496,7 +496,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/test-progs/hello/bin/arm/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout index 769c3535d..bd4c923a3 100755 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout @@ -5,12 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 11 2011 20:10:09 -M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch -M5 started Mar 11 2011 20:10:13 -M5 executing on u200439-lin.austin.arm.com +M5 compiled Mar 18 2011 20:12:03 +M5 started Mar 18 2011 21:02:41 +M5 executing on zizzer command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 10855000 because target called exit() +Exiting @ tick 10827000 because target called exit() diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt index 8fe241344..7a0a94c69 100644 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 4296 # Simulator instruction rate (inst/s) -host_mem_usage 251256 # Number of bytes of host memory used -host_seconds 1.34 # Real time elapsed on the host -host_tick_rate 8125103 # Simulator tick rate (ticks/s) +host_inst_rate 64369 # Simulator instruction rate (inst/s) +host_mem_usage 217368 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +host_tick_rate 121073299 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5739 # Number of instructions simulated sim_seconds 0.000011 # Number of seconds simulated -sim_ticks 10855000 # Number of ticks simulated +sim_ticks 10827000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 646 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 1753 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 638 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1727 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions. system.cpu.BPredUnit.condIncorrect 388 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 1655 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 2162 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 243 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.condPredicted 1625 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2128 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 237 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 927 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 59 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 60 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 11145 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.514939 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.233206 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 11088 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.517587 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.238879 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 8562 76.82% 76.82% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 1244 11.16% 87.99% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 554 4.97% 92.96% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 326 2.93% 95.88% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 181 1.62% 97.51% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 133 1.19% 98.70% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 54 0.48% 99.18% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 32 0.29% 99.47% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 59 0.53% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 8513 76.78% 76.78% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 1240 11.18% 87.96% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 548 4.94% 92.90% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 324 2.92% 95.82% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 182 1.64% 97.47% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 135 1.22% 98.68% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 54 0.49% 99.17% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 32 0.29% 99.46% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 60 0.54% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 11145 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 11088 # Number of insts commited each cycle system.cpu.commit.COM:count 5739 # Number of instructions committed system.cpu.commit.COM:fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 82 # Number of function calls committed. @@ -47,11 +47,11 @@ system.cpu.commit.COM:swp_count 0 # Nu system.cpu.commit.branchMispredicts 318 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 5739 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 24 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4681 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4548 # The number of squashed insts skipped by commit system.cpu.committedInsts 5739 # Number of Instructions Simulated system.cpu.committedInsts_total 5739 # Number of Instructions Simulated -system.cpu.cpi 3.783063 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.783063 # CPI: Total CPI of All Threads +system.cpu.cpi 3.773305 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.773305 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_avg_miss_latency 38250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits @@ -59,82 +59,82 @@ system.cpu.dcache.LoadLockedReq_miss_latency 76500 system.cpu.dcache.LoadLockedReq_miss_rate 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.ReadReq_accesses 1862 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 32845.679012 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 29990.825688 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1700 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5321000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.087003 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 162 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 53 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 3269000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.058539 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_accesses 1838 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 32906.832298 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1677 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 5298000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.087595 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 161 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 52 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 3270000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.059304 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 109 # number of ReadReq MSHR misses system.cpu.dcache.StoreCondReq_accesses 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_hits 11 # number of StoreCondReq hits system.cpu.dcache.WriteReq_accesses 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 35254.295533 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35797.619048 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 35365.979381 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35785.714286 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 622 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 10259000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 10291500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.318729 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 291 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 249 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1503500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1503000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 42 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 15.509934 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 15.357616 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2775 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 34392.935982 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 31605.960265 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2322 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 15580000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.163243 # miss rate for demand accesses -system.cpu.dcache.demand_misses 453 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 302 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4772500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.054414 # mshr miss rate for demand accesses +system.cpu.dcache.demand_accesses 2751 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 34490.044248 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 31609.271523 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2299 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 15589500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.164304 # miss rate for demand accesses +system.cpu.dcache.demand_misses 452 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 301 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 4773000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.054889 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 151 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.022190 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 90.890102 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 2775 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 34392.935982 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 31605.960265 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.022173 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 90.822117 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 2751 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 34490.044248 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 31609.271523 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2322 # number of overall hits -system.cpu.dcache.overall_miss_latency 15580000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.163243 # miss rate for overall accesses -system.cpu.dcache.overall_misses 453 # number of overall misses -system.cpu.dcache.overall_mshr_hits 302 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4772500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.054414 # mshr miss rate for overall accesses +system.cpu.dcache.overall_hits 2299 # number of overall hits +system.cpu.dcache.overall_miss_latency 15589500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.164304 # miss rate for overall accesses +system.cpu.dcache.overall_misses 452 # number of overall misses +system.cpu.dcache.overall_mshr_hits 301 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 4773000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.054889 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 151 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 151 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 90.890102 # Cycle average of tags in use -system.cpu.dcache.total_refs 2342 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 90.822117 # Cycle average of tags in use +system.cpu.dcache.total_refs 2319 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1262 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BlockedCycles 1287 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 156 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 341 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12417 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 7526 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2297 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 804 # Number of cycles decode is squashing +system.cpu.decode.DECODE:BranchResolved 338 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12224 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 7477 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2264 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 778 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 556 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 59 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses @@ -158,175 +158,175 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 2162 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1609 # Number of cache lines fetched -system.cpu.fetch.Cycles 2418 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 235 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 11261 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2128 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1580 # Number of cache lines fetched +system.cpu.fetch.Cycles 2383 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 231 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 11094 # Number of instructions fetch has processed system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 506 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.099581 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1609 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 889 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.518677 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 11948 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.172497 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.587798 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.SquashCycles 497 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.098268 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1580 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 875 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.512307 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 11865 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.163675 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.580533 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9530 79.76% 79.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 215 1.80% 81.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 150 1.26% 82.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 199 1.67% 84.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 194 1.62% 86.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 272 2.28% 88.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 117 0.98% 89.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 109 0.91% 90.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1162 9.73% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9482 79.92% 79.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 214 1.80% 81.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 146 1.23% 82.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 197 1.66% 84.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 189 1.59% 86.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 268 2.26% 88.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 115 0.97% 89.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 108 0.91% 90.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1146 9.66% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11948 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 11865 # Number of instructions fetched each cycle (Total) system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 1609 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 34710.914454 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 33335.069444 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1270 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 11767000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.210690 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 339 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 51 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 9600500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.178993 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_accesses 1580 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 34689.349112 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 33338.541667 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1242 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 11725000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.213924 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 338 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 50 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 9601500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.182278 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 288 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 4.409722 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.312500 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1609 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 34710.914454 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 33335.069444 # average overall mshr miss latency -system.cpu.icache.demand_hits 1270 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 11767000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.210690 # miss rate for demand accesses -system.cpu.icache.demand_misses 339 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 51 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 9600500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.178993 # mshr miss rate for demand accesses +system.cpu.icache.demand_accesses 1580 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 34689.349112 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 33338.541667 # average overall mshr miss latency +system.cpu.icache.demand_hits 1242 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 11725000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.213924 # miss rate for demand accesses +system.cpu.icache.demand_misses 338 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 50 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 9601500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.182278 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 288 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.071695 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 146.831980 # Average occupied blocks per context -system.cpu.icache.overall_accesses 1609 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 34710.914454 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 33335.069444 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.071625 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 146.687091 # Average occupied blocks per context +system.cpu.icache.overall_accesses 1580 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 34689.349112 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 33338.541667 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1270 # number of overall hits -system.cpu.icache.overall_miss_latency 11767000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.210690 # miss rate for overall accesses -system.cpu.icache.overall_misses 339 # number of overall misses -system.cpu.icache.overall_mshr_hits 51 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 9600500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.178993 # mshr miss rate for overall accesses +system.cpu.icache.overall_hits 1242 # number of overall hits +system.cpu.icache.overall_miss_latency 11725000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.213924 # miss rate for overall accesses +system.cpu.icache.overall_misses 338 # number of overall misses +system.cpu.icache.overall_mshr_hits 50 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 9601500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.182278 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 288 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 2 # number of replacements system.cpu.icache.sampled_refs 288 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 146.831980 # Cycle average of tags in use -system.cpu.icache.total_refs 1270 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 146.687091 # Cycle average of tags in use +system.cpu.icache.total_refs 1242 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 9763 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1290 # Number of branches executed +system.cpu.idleCycles 9790 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1278 # Number of branches executed system.cpu.iew.EXEC:nop 18 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.381972 # Inst execution rate -system.cpu.iew.EXEC:refs 3149 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1151 # Number of stores executed +system.cpu.iew.EXEC:rate 0.379774 # Inst execution rate +system.cpu.iew.EXEC:refs 3122 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1148 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 7351 # num instructions consuming a value -system.cpu.iew.WB:count 7821 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.493674 # average fanout of values written-back +system.cpu.iew.WB:consumers 7311 # num instructions consuming a value +system.cpu.iew.WB:count 7762 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.493093 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 3629 # num instructions producing a value -system.cpu.iew.WB:rate 0.360232 # insts written-back per cycle -system.cpu.iew.WB:sent 8026 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 368 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 195 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2420 # Number of dispatched load instructions +system.cpu.iew.WB:producers 3605 # num instructions producing a value +system.cpu.iew.WB:rate 0.358439 # insts written-back per cycle +system.cpu.iew.WB:sent 7965 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 367 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 201 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2382 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 106 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1527 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 10583 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1998 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 333 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 8293 # Number of executed instructions +system.cpu.iew.iewDispSquashedInsts 98 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1514 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 10450 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1974 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 329 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8224 # Number of executed instructions system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 804 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 778 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 51 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 30 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 13 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1219 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 589 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 30 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 273 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.lsq.thread.0.squashedLoads 1181 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 576 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 272 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 95 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 18798 # number of integer regfile reads -system.cpu.int_regfile_writes 5617 # number of integer regfile writes -system.cpu.ipc 0.264336 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.264336 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 18651 # number of integer regfile reads +system.cpu.int_regfile_writes 5571 # number of integer regfile writes +system.cpu.ipc 0.265020 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.265020 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 5295 61.38% 61.38% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 6 0.07% 61.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 61.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 61.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 61.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 61.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 61.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 61.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 61.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 61.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 61.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 61.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 61.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 61.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 61.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 61.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 61.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 61.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 61.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 61.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 61.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 61.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 61.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 61.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 61.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.03% 61.49% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 2134 24.74% 86.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1188 13.77% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 5254 61.43% 61.43% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 6 0.07% 61.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 61.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 61.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 61.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 61.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 61.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 61.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 61.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 61.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 61.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 61.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 61.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 61.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 61.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 61.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 61.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 61.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 61.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 61.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 61.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 61.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 61.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 61.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 61.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.04% 61.53% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 2109 24.66% 86.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1181 13.81% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 8626 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 8553 # Type of FU issued system.cpu.iq.ISSUE:fu_busy_cnt 186 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.021563 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate 0.021747 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntAlu 6 3.23% 3.23% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 3.23% # attempts to use FU when none available @@ -361,39 +361,39 @@ system.cpu.iq.ISSUE:fu_full::MemRead 120 64.52% 67.74% # at system.cpu.iq.ISSUE:fu_full::MemWrite 60 32.26% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 11948 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.721962 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.365135 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 11865 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.720860 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.364573 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 8312 69.57% 69.57% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 1403 11.74% 81.31% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 852 7.13% 88.44% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 582 4.87% 93.31% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 409 3.42% 96.74% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 241 2.02% 98.75% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 119 1.00% 99.75% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 22 0.18% 99.93% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 8254 69.57% 69.57% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 1404 11.83% 81.40% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 840 7.08% 88.48% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 572 4.82% 93.30% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 408 3.44% 96.74% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 241 2.03% 98.77% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 114 0.96% 99.73% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 24 0.20% 99.93% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::8 8 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 11948 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.397310 # Inst issue rate +system.cpu.iq.ISSUE:issued_per_cycle::total 11865 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.394967 # Inst issue rate system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 8792 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 29375 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 7805 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 14943 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 10540 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8626 # Number of instructions issued +system.cpu.iq.int_alu_accesses 8719 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 29141 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 7746 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 14669 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 10407 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8553 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 4372 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 25 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4242 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 20 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 6854 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 6639 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -416,19 +416,19 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34404.761905 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31285.714286 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1445000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 34416.666667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31273.809524 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 1445500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 42 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1314000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1313500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 42 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 397 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34355.153203 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34356.545961 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31244.318182 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 38 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 12333500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 12334000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.904282 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 359 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_hits 7 # number of ReadReq MSHR hits @@ -444,31 +444,31 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 439 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34360.349127 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31248.730964 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 34362.842893 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31247.461929 # average overall mshr miss latency system.cpu.l2cache.demand_hits 38 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 13778500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 13779500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.913440 # miss rate for demand accesses system.cpu.l2cache.demand_misses 401 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 7 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 12312000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 12311500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.897494 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 394 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.005712 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 187.177998 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.005707 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 187.002555 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 439 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34360.349127 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31248.730964 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 34362.842893 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31247.461929 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 38 # number of overall hits -system.cpu.l2cache.overall_miss_latency 13778500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 13779500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.913440 # miss rate for overall accesses system.cpu.l2cache.overall_misses 401 # number of overall misses system.cpu.l2cache.overall_mshr_hits 7 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 12312000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 12311500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.897494 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 394 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -476,40 +476,40 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 352 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 187.177998 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 187.002555 # Cycle average of tags in use system.cpu.l2cache.total_refs 38 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. +system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 2420 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1527 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 14141 # number of misc regfile reads +system.cpu.memDep0.insertedLoads 2382 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1514 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 13955 # number of misc regfile reads system.cpu.misc_regfile_writes 4 # number of misc regfile writes -system.cpu.numCycles 21711 # number of cpu cycles simulated +system.cpu.numCycles 21655 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 323 # Number of cycles rename is blocking +system.cpu.rename.RENAME:BlockCycles 331 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4124 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 29 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 7791 # Number of cycles rename is idle +system.cpu.rename.RENAME:IQFullEvents 31 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 7738 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 132 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 30367 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11639 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8331 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 2090 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 804 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 195 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4204 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:RenameLookups 29900 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11466 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8204 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 2060 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 778 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 198 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4077 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:fp_rename_lookups 390 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 29977 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 745 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:int_rename_lookups 29510 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 760 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 16 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 568 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 569 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 14 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 21349 # The number of ROB reads -system.cpu.rob.rob_writes 21656 # The number of ROB writes -system.cpu.timesIdled 201 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rob.rob_reads 21158 # The number of ROB reads +system.cpu.rob.rob_writes 21364 # The number of ROB writes +system.cpu.timesIdled 200 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 13 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini index a58be5b4d..f2ed87236 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini @@ -169,6 +169,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -467,6 +468,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -502,6 +504,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=1000 max_miss_count=0 mshrs=10 diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout index 5ff276ac0..27c18cbea 100755 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout @@ -5,13 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:55:51 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:56:01 -M5 executing on burrito +M5 compiled Mar 17 2011 23:01:20 +M5 started Mar 17 2011 23:01:33 +M5 executing on zizzer command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 12784500 because target called exit() +Exiting @ tick 12793500 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt index 7a8012ce7..81b1a48e3 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 37179 # Simulator instruction rate (inst/s) -host_mem_usage 224748 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host -host_tick_rate 91756799 # Simulator tick rate (ticks/s) +host_inst_rate 71769 # Simulator instruction rate (inst/s) +host_mem_usage 206840 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 176990793 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5169 # Number of instructions simulated sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 12784500 # Number of ticks simulated +sim_ticks 12793500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 538 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 1522 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 531 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1503 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 66 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 378 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 1192 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 1744 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 215 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.condIncorrect 380 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 1180 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 1716 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 206 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 916 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 76 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 77 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 12273 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.474701 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.213395 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 12220 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.476759 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.219720 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 9782 79.70% 79.70% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 1006 8.20% 87.90% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 705 5.74% 93.64% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 340 2.77% 96.41% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 169 1.38% 97.79% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 96 0.78% 98.57% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 67 0.55% 99.12% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 32 0.26% 99.38% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 76 0.62% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 9742 79.72% 79.72% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 995 8.14% 87.86% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 703 5.75% 93.62% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 335 2.74% 96.36% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 169 1.38% 97.74% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 98 0.80% 98.54% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 69 0.56% 99.11% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 32 0.26% 99.37% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 77 0.63% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 12273 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 12220 # Number of insts commited each cycle system.cpu.commit.COM:count 5826 # Number of instructions committed system.cpu.commit.COM:fp_insts 2 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 87 # Number of function calls committed. @@ -44,88 +44,88 @@ system.cpu.commit.COM:loads 1164 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 2089 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 339 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 3481 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 3363 # The number of squashed insts skipped by commit system.cpu.committedInsts 5169 # Number of Instructions Simulated system.cpu.committedInsts_total 5169 # Number of Instructions Simulated -system.cpu.cpi 4.946798 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.946798 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1824 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 36046.875000 # average ReadReq miss latency +system.cpu.cpi 4.950281 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.950281 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1798 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 36128.906250 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35938.888889 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1696 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4614000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.070175 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_hits 1670 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4624500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.071190 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 128 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 38 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 3234500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.049342 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.050056 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 90 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 34184.971098 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36196.078431 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 34186.416185 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36205.882353 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 579 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 11828000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 11828500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.374054 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 346 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 295 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1846000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1846500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 16.134752 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 15.950355 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2749 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 34687.763713 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 36031.914894 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2275 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 16442000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.172426 # miss rate for demand accesses +system.cpu.dcache.demand_accesses 2723 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 34710.970464 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 36035.460993 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2249 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 16453000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.174073 # miss rate for demand accesses system.cpu.dcache.demand_misses 474 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 333 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 5080500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.051291 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_latency 5081000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.051781 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 141 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.022390 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 91.708831 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 2749 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 34687.763713 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 36031.914894 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.022393 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 91.720291 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 2723 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 34710.970464 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 36035.460993 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2275 # number of overall hits -system.cpu.dcache.overall_miss_latency 16442000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.172426 # miss rate for overall accesses +system.cpu.dcache.overall_hits 2249 # number of overall hits +system.cpu.dcache.overall_miss_latency 16453000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.174073 # miss rate for overall accesses system.cpu.dcache.overall_misses 474 # number of overall misses system.cpu.dcache.overall_mshr_hits 333 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 5080500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.051291 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_latency 5081000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.051781 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 141 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 91.708831 # Cycle average of tags in use -system.cpu.dcache.total_refs 2275 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 91.720291 # Cycle average of tags in use +system.cpu.dcache.total_refs 2249 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 736 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BlockedCycles 742 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 42 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 88 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 10461 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 8771 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2729 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 649 # Number of cycles decode is squashing +system.cpu.decode.DECODE:BranchResolved 89 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 10279 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 8753 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2688 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 636 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 153 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 37 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses @@ -137,243 +137,242 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 1744 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1555 # Number of cache lines fetched -system.cpu.fetch.Cycles 2837 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 219 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 11052 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1716 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1531 # Number of cache lines fetched +system.cpu.fetch.Cycles 2794 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 211 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 10867 # Number of instructions fetch has processed system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 393 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.068205 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1555 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 753 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.432225 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 12922 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.855286 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.122030 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.SquashCycles 387 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.067063 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1531 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 737 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.424691 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 12856 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.845286 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.112165 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10085 78.05% 78.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1182 9.15% 87.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 138 1.07% 88.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 127 0.98% 89.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 278 2.15% 91.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 124 0.96% 92.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 162 1.25% 93.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 99 0.77% 94.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 727 5.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10062 78.27% 78.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1173 9.12% 87.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 132 1.03% 88.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 122 0.95% 89.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 273 2.12% 91.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 123 0.96% 92.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 157 1.22% 93.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 97 0.75% 94.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 717 5.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12922 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 12856 # Number of instructions fetched each cycle (Total) system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 1555 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 36274.074074 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35024.316109 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1150 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 14691000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.260450 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 405 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 76 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11523000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.211576 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_accesses 1531 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 36303.482587 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35016.717325 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1129 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 14594000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.262573 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 402 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 73 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 11520500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.214892 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 329 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.495441 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.431611 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1555 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 36274.074074 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35024.316109 # average overall mshr miss latency -system.cpu.icache.demand_hits 1150 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 14691000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.260450 # miss rate for demand accesses -system.cpu.icache.demand_misses 405 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 76 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11523000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.211576 # mshr miss rate for demand accesses +system.cpu.icache.demand_accesses 1531 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 36303.482587 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35016.717325 # average overall mshr miss latency +system.cpu.icache.demand_hits 1129 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 14594000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.262573 # miss rate for demand accesses +system.cpu.icache.demand_misses 402 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 73 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 11520500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.214892 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 329 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.077565 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 158.853467 # Average occupied blocks per context -system.cpu.icache.overall_accesses 1555 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 36274.074074 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35024.316109 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.077515 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 158.750706 # Average occupied blocks per context +system.cpu.icache.overall_accesses 1531 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 36303.482587 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35016.717325 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1150 # number of overall hits -system.cpu.icache.overall_miss_latency 14691000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.260450 # miss rate for overall accesses -system.cpu.icache.overall_misses 405 # number of overall misses -system.cpu.icache.overall_mshr_hits 76 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11523000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.211576 # mshr miss rate for overall accesses +system.cpu.icache.overall_hits 1129 # number of overall hits +system.cpu.icache.overall_miss_latency 14594000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.262573 # miss rate for overall accesses +system.cpu.icache.overall_misses 402 # number of overall misses +system.cpu.icache.overall_mshr_hits 73 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 11520500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.214892 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 329 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 15 # number of replacements system.cpu.icache.sampled_refs 329 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 158.853467 # Cycle average of tags in use -system.cpu.icache.total_refs 1150 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 158.750706 # Cycle average of tags in use +system.cpu.icache.total_refs 1129 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 12648 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1183 # Number of branches executed -system.cpu.iew.EXEC:nop 1244 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.279625 # Inst execution rate -system.cpu.iew.EXEC:refs 2950 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1042 # Number of stores executed +system.cpu.idleCycles 12732 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1171 # Number of branches executed +system.cpu.iew.EXEC:nop 1220 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.276575 # Inst execution rate +system.cpu.iew.EXEC:refs 2915 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1038 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 3586 # num instructions consuming a value -system.cpu.iew.WB:count 6793 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.717513 # average fanout of values written-back +system.cpu.iew.WB:consumers 3566 # num instructions consuming a value +system.cpu.iew.WB:count 6732 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.716489 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 2573 # num instructions producing a value -system.cpu.iew.WB:rate 0.265663 # insts written-back per cycle -system.cpu.iew.WB:sent 6861 # cumulative count of insts sent to commit +system.cpu.iew.WB:producers 2555 # num instructions producing a value +system.cpu.iew.WB:rate 0.263092 # insts written-back per cycle +system.cpu.iew.WB:sent 6801 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 377 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 165 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2139 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 207 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1135 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9313 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1908 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 223 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 7150 # Number of executed instructions +system.cpu.iew.iewDispLoadInsts 2109 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 10 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 198 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1127 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 9195 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1877 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 216 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 7077 # Number of executed instructions system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 649 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 636 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 14 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 66 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.forwLoads 59 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 16 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 5 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 975 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 210 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations +system.cpu.iew.lsq.thread.0.squashedLoads 945 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 202 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 259 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 118 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 9780 # number of integer regfile reads -system.cpu.int_regfile_writes 4751 # number of integer regfile writes -system.cpu.ipc 0.202151 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.202151 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9689 # number of integer regfile reads +system.cpu.int_regfile_writes 4703 # number of integer regfile writes +system.cpu.ipc 0.202009 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.202009 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 4328 58.70% 58.70% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 4 0.05% 58.75% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 2 0.03% 58.78% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.03% 58.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 58.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 58.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 58.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 58.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 58.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 58.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 58.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 58.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 58.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 58.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 58.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 58.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 58.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 58.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 58.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 58.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 58.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 58.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 58.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 58.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 58.81% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 1984 26.91% 85.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1053 14.28% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 4286 58.77% 58.77% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 4 0.05% 58.82% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 2 0.03% 58.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.03% 58.88% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 1952 26.77% 85.64% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1047 14.36% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 7373 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 142 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.019259 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 7293 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 143 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.019608 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 7 4.93% 4.93% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 4.93% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 4.93% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 4.93% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 4.93% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 4.93% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 4.93% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 4.93% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 4.93% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 4.93% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 4.93% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 4.93% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 4.93% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 4.93% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 4.93% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 4.93% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 4.93% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 4.93% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 4.93% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 4.93% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 4.93% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 4.93% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 4.93% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 4.93% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 4.93% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 4.93% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 4.93% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 4.93% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 4.93% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 83 58.45% 63.38% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 52 36.62% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 7 4.90% 4.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 4.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 84 58.74% 63.64% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 52 36.36% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 12922 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.570577 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.213210 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 12856 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.567284 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.210668 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 9579 74.13% 74.13% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 1454 11.25% 85.38% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 793 6.14% 91.52% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 511 3.95% 95.47% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 304 2.35% 97.83% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 160 1.24% 99.06% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 76 0.59% 99.65% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 32 0.25% 99.90% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 13 0.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 9551 74.29% 74.29% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 1436 11.17% 85.46% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 786 6.11% 91.58% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 503 3.91% 95.49% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 300 2.33% 97.82% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 160 1.24% 99.07% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 76 0.59% 99.66% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 32 0.25% 99.91% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 12922 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.288346 # Inst issue rate +system.cpu.iq.ISSUE:issued_per_cycle::total 12856 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.285016 # Inst issue rate system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 7513 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 27837 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 6791 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 10538 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 8058 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 7373 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 2456 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.int_alu_accesses 7434 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 27612 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 6730 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 10338 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 7965 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 7293 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 10 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 2360 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 1522 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 1480 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses @@ -384,22 +383,22 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34696.078431 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34686.274510 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31490.196078 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1769500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 1769000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 1606000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 419 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34325.721154 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31134.615385 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34317.307692 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31129.807692 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 14279500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 14276000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.992840 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 416 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12952000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 12950000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.992840 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 416 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -411,31 +410,31 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 470 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34366.167024 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31173.447537 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 34357.601713 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31169.164882 # average overall mshr miss latency system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 16049000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 16045000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.993617 # miss rate for demand accesses system.cpu.l2cache.demand_misses 467 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 14558000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 14556000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.993617 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 467 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.006661 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 218.261856 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.006657 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 218.141494 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 470 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34366.167024 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31173.447537 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 34357.601713 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31169.164882 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 3 # number of overall hits -system.cpu.l2cache.overall_miss_latency 16049000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 16045000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.993617 # miss rate for overall accesses system.cpu.l2cache.overall_misses 467 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 14558000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 14556000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.993617 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 467 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -443,38 +442,38 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 416 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 218.261856 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 218.141494 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads. +system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 2139 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1135 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 136 # number of misc regfile reads -system.cpu.numCycles 25570 # number of cpu cycles simulated +system.cpu.memDep0.insertedLoads 2109 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1127 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 134 # number of misc regfile reads +system.cpu.numCycles 25588 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 238 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 3410 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 8931 # Number of cycles rename is idle +system.cpu.rename.RENAME:IdleCycles 8904 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 71 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 12088 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 10031 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 6119 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 2609 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 649 # Number of cycles rename is squashing +system.cpu.rename.RENAME:RenameLookups 11929 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 9880 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 6029 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 2577 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 636 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 81 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 2709 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:UndoneMaps 2619 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:fp_rename_lookups 5 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 12083 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 414 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 16 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 196 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 11 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 21491 # The number of ROB reads -system.cpu.rob.rob_writes 19268 # The number of ROB writes -system.cpu.timesIdled 259 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:int_rename_lookups 11924 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 420 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 15 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 193 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 10 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 21319 # The number of ROB reads +system.cpu.rob.rob_writes 19020 # The number of ROB writes +system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 8 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini index 195dd9e9c..8890f2cb3 100644 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini @@ -116,6 +116,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -414,6 +415,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -449,6 +451,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=1000 max_miss_count=0 mshrs=10 diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr index 799831583..9c2f3b607 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr @@ -1,5 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: allowing mmap of file @ fd 42898616. This will break if not /dev/zero. +warn: allowing mmap of file @ fd 17488232. This will break if not /dev/zero. For more information see: http://www.m5sim.org/warn/3a2134f6 hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/00.hello/ref/power/linux/o3-timing/simout index 9ed661104..db07f12a1 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simout @@ -5,12 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:06:34 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:06:41 -M5 executing on burrito +M5 compiled Mar 18 2011 02:41:27 +M5 started Mar 18 2011 02:41:29 +M5 executing on zizzer command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 11733000 because target called exit() +Exiting @ tick 11695000 because target called exit() diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt index eed636458..6e32b0c6c 100644 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 32835 # Simulator instruction rate (inst/s) -host_mem_usage 222408 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host -host_tick_rate 66311402 # Simulator tick rate (ticks/s) +host_inst_rate 15140 # Simulator instruction rate (inst/s) +host_mem_usage 204452 # Number of bytes of host memory used +host_seconds 0.38 # Real time elapsed on the host +host_tick_rate 30510356 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5800 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 11733000 # Number of ticks simulated +sim_ticks 11695000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 687 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 1888 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 679 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1865 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 31 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 387 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 1757 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 2100 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 189 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.condIncorrect 388 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 1734 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2075 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 187 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 1038 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 51 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 42 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 10473 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.553805 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.272090 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 10395 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.557961 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.275569 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 7930 75.72% 75.72% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 1118 10.68% 86.39% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 663 6.33% 92.72% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 256 2.44% 95.17% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 224 2.14% 97.31% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 123 1.17% 98.48% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 87 0.83% 99.31% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 21 0.20% 99.51% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 51 0.49% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 7869 75.70% 75.70% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 1103 10.61% 86.31% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 649 6.24% 92.55% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 257 2.47% 95.03% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 223 2.15% 97.17% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 132 1.27% 98.44% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 100 0.96% 99.40% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 20 0.19% 99.60% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 42 0.40% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 10473 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 10395 # Number of insts commited each cycle system.cpu.commit.COM:count 5800 # Number of instructions committed system.cpu.commit.COM:fp_insts 22 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 103 # Number of function calls committed. @@ -47,86 +47,86 @@ system.cpu.commit.COM:swp_count 0 # Nu system.cpu.commit.branchMispredicts 240 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 5800 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 3389 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 3301 # The number of squashed insts skipped by commit system.cpu.committedInsts 5800 # Number of Instructions Simulated system.cpu.committedInsts_total 5800 # Number of Instructions Simulated -system.cpu.cpi 4.046034 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.046034 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1444 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 33681.818182 # average ReadReq miss latency +system.cpu.cpi 4.032931 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.032931 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1431 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 33954.022989 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34464.285714 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1356 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2964000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.060942 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 88 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 32 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_hits 1344 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 2954000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.060797 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 87 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 31 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 1930000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.038781 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.039133 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 56 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 33737.864078 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36302.083333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 33770.226537 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36291.666667 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 737 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 10425000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 10435000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.295411 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 309 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 261 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1742500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1742000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.045889 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 48 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 20.125000 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 20.009615 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2490 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 33725.440806 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35312.500000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2093 # number of demand (read+write) hits +system.cpu.dcache.demand_accesses 2477 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 33810.606061 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35307.692308 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2081 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 13389000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.159438 # miss rate for demand accesses -system.cpu.dcache.demand_misses 397 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 293 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3672500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.041767 # mshr miss rate for demand accesses +system.cpu.dcache.demand_miss_rate 0.159871 # miss rate for demand accesses +system.cpu.dcache.demand_misses 396 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 292 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 3672000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.041986 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 104 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.016245 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 66.538229 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 2490 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 33725.440806 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35312.500000 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.016225 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 66.459259 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 2477 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 33810.606061 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35307.692308 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2093 # number of overall hits +system.cpu.dcache.overall_hits 2081 # number of overall hits system.cpu.dcache.overall_miss_latency 13389000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.159438 # miss rate for overall accesses -system.cpu.dcache.overall_misses 397 # number of overall misses -system.cpu.dcache.overall_mshr_hits 293 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3672500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.041767 # mshr miss rate for overall accesses +system.cpu.dcache.overall_miss_rate 0.159871 # miss rate for overall accesses +system.cpu.dcache.overall_misses 396 # number of overall misses +system.cpu.dcache.overall_mshr_hits 292 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 3672000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.041986 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 104 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 104 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 66.538229 # Cycle average of tags in use -system.cpu.dcache.total_refs 2093 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 66.459259 # Cycle average of tags in use +system.cpu.dcache.total_refs 2081 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 885 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 150 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 267 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 10406 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 7574 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 1944 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 570 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 416 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:BlockedCycles 887 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 151 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 265 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 10261 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 7524 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 1914 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 549 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 421 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 70 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits @@ -137,243 +137,243 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 2100 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1490 # Number of cache lines fetched -system.cpu.fetch.Cycles 2070 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 225 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 11687 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2075 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1460 # Number of cache lines fetched +system.cpu.fetch.Cycles 2040 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 218 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 11548 # Number of instructions fetch has processed system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 410 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.089487 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1490 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 876 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.498018 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 11043 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.058317 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.450976 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.SquashCycles 402 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.088709 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1460 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 866 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.493694 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 10944 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.055190 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.449465 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8973 81.26% 81.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 161 1.46% 82.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 189 1.71% 84.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 155 1.40% 85.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 202 1.83% 87.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 136 1.23% 88.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 272 2.46% 91.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 77 0.70% 92.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 878 7.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8904 81.36% 81.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 156 1.43% 82.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 186 1.70% 84.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 150 1.37% 85.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 199 1.82% 87.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 133 1.22% 88.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 272 2.49% 91.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 75 0.69% 92.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 869 7.94% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11043 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 10944 # Number of instructions fetched each cycle (Total) system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 1490 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 36422.279793 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34777.108434 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1104 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 14059000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.259060 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 386 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11546000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.222819 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 332 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 1460 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 36594.488189 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34774.774775 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1079 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 13942500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.260959 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 381 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 48 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 11580000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.228082 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 333 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.325301 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.240240 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1490 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 36422.279793 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34777.108434 # average overall mshr miss latency -system.cpu.icache.demand_hits 1104 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 14059000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.259060 # miss rate for demand accesses -system.cpu.icache.demand_misses 386 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 54 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11546000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.222819 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 332 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 1460 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 36594.488189 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34774.774775 # average overall mshr miss latency +system.cpu.icache.demand_hits 1079 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 13942500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.260959 # miss rate for demand accesses +system.cpu.icache.demand_misses 381 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 48 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 11580000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.228082 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 333 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.078715 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 161.207549 # Average occupied blocks per context -system.cpu.icache.overall_accesses 1490 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 36422.279793 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34777.108434 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.078664 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 161.104076 # Average occupied blocks per context +system.cpu.icache.overall_accesses 1460 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 36594.488189 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34774.774775 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1104 # number of overall hits -system.cpu.icache.overall_miss_latency 14059000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.259060 # miss rate for overall accesses -system.cpu.icache.overall_misses 386 # number of overall misses -system.cpu.icache.overall_mshr_hits 54 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11546000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.222819 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 332 # number of overall MSHR misses +system.cpu.icache.overall_hits 1079 # number of overall hits +system.cpu.icache.overall_miss_latency 13942500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.260959 # miss rate for overall accesses +system.cpu.icache.overall_misses 381 # number of overall misses +system.cpu.icache.overall_mshr_hits 48 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 11580000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.228082 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 333 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 332 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 333 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 161.207549 # Cycle average of tags in use -system.cpu.icache.total_refs 1104 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 161.104076 # Cycle average of tags in use +system.cpu.icache.total_refs 1079 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 12424 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1261 # Number of branches executed +system.cpu.idleCycles 12447 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1262 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.331998 # Inst execution rate -system.cpu.iew.EXEC:refs 2813 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1315 # Number of stores executed +system.cpu.iew.EXEC:rate 0.332008 # Inst execution rate +system.cpu.iew.EXEC:refs 2790 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1305 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5926 # num instructions consuming a value -system.cpu.iew.WB:count 7582 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.645461 # average fanout of values written-back +system.cpu.iew.WB:consumers 5916 # num instructions consuming a value +system.cpu.iew.WB:count 7563 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.645030 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 3825 # num instructions producing a value -system.cpu.iew.WB:rate 0.323092 # insts written-back per cycle -system.cpu.iew.WB:sent 7642 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 277 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 3816 # num instructions producing a value +system.cpu.iew.WB:rate 0.323329 # insts written-back per cycle +system.cpu.iew.WB:sent 7623 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 279 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 130 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 1681 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 1666 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 14 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 97 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1450 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9185 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1498 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 298 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 7791 # Number of executed instructions +system.cpu.iew.iewDispSquashedInsts 100 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1436 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 9097 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1485 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 289 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 7766 # Number of executed instructions system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 570 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 549 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 30 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 29 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 42 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 13 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 719 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 404 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 42 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 201 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 76 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 12419 # number of integer regfile reads -system.cpu.int_regfile_writes 6594 # number of integer regfile writes -system.cpu.ipc 0.247156 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.247156 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.squashedLoads 704 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 390 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 202 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 77 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 12407 # number of integer regfile reads +system.cpu.int_regfile_writes 6585 # number of integer regfile writes +system.cpu.ipc 0.247959 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.247959 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 5126 63.37% 63.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 63.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 63.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 63.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 1593 19.69% 83.09% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1368 16.91% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 5116 63.51% 63.51% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 63.51% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 63.51% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 63.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 1580 19.62% 83.15% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1357 16.85% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 8089 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 153 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.018915 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 8055 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 152 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.018870 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 11 7.19% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 7.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 73 47.71% 54.90% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 69 45.10% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 11 7.24% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 7.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 72 47.37% 54.61% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 69 45.39% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 11043 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.732500 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.410424 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 10944 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.736020 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.423307 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 7773 70.39% 70.39% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 1167 10.57% 80.96% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 813 7.36% 88.32% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 500 4.53% 92.85% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 391 3.54% 96.39% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 222 2.01% 98.40% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 124 1.12% 99.52% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 46 0.42% 99.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 7700 70.36% 70.36% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 1176 10.75% 81.10% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 793 7.25% 88.35% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 485 4.43% 92.78% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 365 3.34% 96.12% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 233 2.13% 98.25% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 138 1.26% 99.51% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 47 0.43% 99.94% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::8 7 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 11043 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.344697 # Inst issue rate +system.cpu.iq.ISSUE:issued_per_cycle::total 10944 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.344363 # Inst issue rate system.cpu.iq.fp_alu_accesses 31 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 59 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 8211 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 27329 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 7555 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 12158 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 9163 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8089 # Number of instructions issued +system.cpu.iq.int_alu_accesses 8176 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 27162 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 7536 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 11998 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 9075 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8055 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 2985 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 14 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2924 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 15 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2761 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 2633 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses @@ -384,97 +384,97 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 48 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34947.916667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34937.500000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31770.833333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1677500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 1677000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 48 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 1525000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 48 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 388 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34326.315789 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31147.368421 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 389 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34322.834646 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31146.981627 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 8 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 13044000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.979381 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 380 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 11836000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.979381 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 380 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 13077000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.979434 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 381 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 11867000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.979434 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 381 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.021053 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.020997 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 436 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34396.028037 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31217.289720 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 437 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34391.608392 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31216.783217 # average overall mshr miss latency system.cpu.l2cache.demand_hits 8 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 14721500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.981651 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 428 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 14754000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.981693 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 429 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 13361000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.981651 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 428 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 13392000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.981693 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 429 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.005863 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 192.111326 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 436 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34396.028037 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31217.289720 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.005859 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 191.979751 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 437 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34391.608392 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31216.783217 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 8 # number of overall hits -system.cpu.l2cache.overall_miss_latency 14721500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.981651 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 428 # number of overall misses +system.cpu.l2cache.overall_miss_latency 14754000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.981693 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 429 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 13361000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.981651 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 428 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 13392000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.981693 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 429 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 380 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 381 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 192.111326 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 191.979751 # Cycle average of tags in use system.cpu.l2cache.total_refs 8 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 67 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 1681 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1450 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 23467 # number of cpu cycles simulated +system.cpu.memDep0.conflictingLoads 48 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 1666 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1436 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 23391 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 312 # Number of cycles rename is blocking +system.cpu.rename.RENAME:BlockCycles 314 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 5007 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 7 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 7756 # Number of cycles rename is idle +system.cpu.rename.RENAME:IdleCycles 7703 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 194 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 16232 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 9925 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8708 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1825 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 570 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 243 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 3701 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:RenameLookups 16001 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 9789 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8584 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 1797 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 549 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 244 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 3577 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:fp_rename_lookups 55 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 16177 # Number of integer rename lookups +system.cpu.rename.RENAME:int_rename_lookups 15946 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 337 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 22 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 473 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 471 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 19611 # The number of ROB reads -system.cpu.rob.rob_writes 18950 # The number of ROB writes -system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rob.rob_reads 19454 # The number of ROB reads +system.cpu.rob.rob_writes 18753 # The number of ROB writes +system.cpu.timesIdled 229 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 9 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini index 1fab00bfb..7618192c8 100644 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini @@ -115,6 +115,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -413,6 +414,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -448,6 +450,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=1000 max_miss_count=0 mshrs=10 diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout index 9b7c5bb35..18b684d12 100755 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout @@ -5,13 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 1 2011 23:14:11 -M5 revision 42f62a19a71d 8104 default qbase qtip tip x86seo3stats.patch -M5 started Mar 1 2011 23:14:13 -M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing +M5 compiled Mar 18 2011 20:12:06 +M5 started Mar 18 2011 20:30:23 +M5 executing on zizzer +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 11421500 because target called exit() +Exiting @ tick 11371000 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt index b2e2e6e9e..738321b57 100644 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 103787 # Simulator instruction rate (inst/s) -host_mem_usage 224152 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -host_tick_rate 120600528 # Simulator tick rate (ticks/s) +host_inst_rate 85944 # Simulator instruction rate (inst/s) +host_mem_usage 211192 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host +host_tick_rate 99394076 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9809 # Number of instructions simulated sim_seconds 0.000011 # Number of seconds simulated -sim_ticks 11421500 # Number of ticks simulated +sim_ticks 11371000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 944 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 2550 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 931 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 2531 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.BPredUnit.condIncorrect 485 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 2777 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 2777 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 2758 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2758 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 1214 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 139 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 141 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 11906 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.823870 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.588166 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 11809 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.830638 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.597584 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 8274 69.49% 69.49% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 1230 10.33% 79.83% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 588 4.94% 84.76% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 963 8.09% 92.85% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 395 3.32% 96.17% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 136 1.14% 97.31% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 125 1.05% 98.36% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 56 0.47% 98.83% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 139 1.17% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 8189 69.35% 69.35% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 1225 10.37% 79.72% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 582 4.93% 84.65% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 958 8.11% 92.76% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 396 3.35% 96.11% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 132 1.12% 97.23% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 128 1.08% 98.31% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 58 0.49% 98.81% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 141 1.19% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 11906 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 11809 # Number of insts commited each cycle system.cpu.commit.COM:count 9809 # Number of instructions committed system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 0 # Number of function calls committed. @@ -47,334 +47,334 @@ system.cpu.commit.COM:swp_count 0 # Nu system.cpu.commit.branchMispredicts 485 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 9809 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 9374 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9222 # The number of squashed insts skipped by commit system.cpu.committedInsts 9809 # Number of Instructions Simulated system.cpu.committedInsts_total 9809 # Number of Instructions Simulated -system.cpu.cpi 2.328882 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.328882 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1541 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 34473.684211 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35119.402985 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1427 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3930000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.073978 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 114 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 47 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2353000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.043478 # mshr miss rate for ReadReq accesses +system.cpu.cpi 2.318585 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.318585 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1531 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 34504.424779 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35141.791045 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1418 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3899000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.073808 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 113 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 46 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2354500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.043762 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 67 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 34089.456869 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36012.987013 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 34084.664537 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 621 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 10670000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 10668500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.335118 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 313 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 236 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2773000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2772000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.082441 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 77 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 14.321678 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 14.258741 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2475 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 34192.037471 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35597.222222 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 14600000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.172525 # miss rate for demand accesses -system.cpu.dcache.demand_misses 427 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 283 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 5126000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.058182 # mshr miss rate for demand accesses +system.cpu.dcache.demand_accesses 2465 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 34196.009390 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35600.694444 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2039 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 14567500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.172819 # miss rate for demand accesses +system.cpu.dcache.demand_misses 426 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 282 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 5126500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.058418 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 144 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.020970 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 85.892970 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 2475 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 34192.037471 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35597.222222 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.020965 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 85.873455 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 2465 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 34196.009390 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35600.694444 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2048 # number of overall hits -system.cpu.dcache.overall_miss_latency 14600000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.172525 # miss rate for overall accesses -system.cpu.dcache.overall_misses 427 # number of overall misses -system.cpu.dcache.overall_mshr_hits 283 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 5126000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.058182 # mshr miss rate for overall accesses +system.cpu.dcache.overall_hits 2039 # number of overall hits +system.cpu.dcache.overall_miss_latency 14567500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.172819 # miss rate for overall accesses +system.cpu.dcache.overall_misses 426 # number of overall misses +system.cpu.dcache.overall_mshr_hits 282 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 5126500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.058418 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 144 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 143 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 85.892970 # Cycle average of tags in use -system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 85.873455 # Cycle average of tags in use +system.cpu.dcache.total_refs 2039 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1367 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 22275 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 7155 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 3308 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1504 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 76 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 2777 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1732 # Number of cache lines fetched -system.cpu.fetch.Cycles 3623 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 245 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 12976 # Number of instructions fetch has processed +system.cpu.decode.DECODE:BlockedCycles 1369 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 22088 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 7085 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 3278 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1477 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 77 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 2758 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1703 # Number of cache lines fetched +system.cpu.fetch.Cycles 3590 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 238 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 12847 # Number of instructions fetch has processed system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 508 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.121564 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1732 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 944 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.568027 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 13410 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.734526 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.109133 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.SquashCycles 497 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.121268 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1703 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 931 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.564877 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 13286 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.734834 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.110520 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9877 73.65% 73.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 162 1.21% 74.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 123 0.92% 75.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 227 1.69% 77.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 192 1.43% 78.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 174 1.30% 80.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 266 1.98% 82.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 175 1.30% 83.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2214 16.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9786 73.66% 73.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 161 1.21% 74.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 122 0.92% 75.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 227 1.71% 77.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 192 1.45% 78.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 168 1.26% 80.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 257 1.93% 82.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 171 1.29% 83.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2202 16.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13410 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 13286 # Number of instructions fetched each cycle (Total) system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 1732 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 36454.794521 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35105.084746 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1367 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 13306000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.210739 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 365 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 70 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 10356000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.170323 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_accesses 1703 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 36577.562327 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35100 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1342 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 13204500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.211979 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 361 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 66 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 10354500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.173224 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 295 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 4.633898 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.549153 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1732 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 36454.794521 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35105.084746 # average overall mshr miss latency -system.cpu.icache.demand_hits 1367 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 13306000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.210739 # miss rate for demand accesses -system.cpu.icache.demand_misses 365 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 70 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 10356000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.170323 # mshr miss rate for demand accesses +system.cpu.icache.demand_accesses 1703 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 36577.562327 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35100 # average overall mshr miss latency +system.cpu.icache.demand_hits 1342 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 13204500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.211979 # miss rate for demand accesses +system.cpu.icache.demand_misses 361 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 66 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 10354500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.173224 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 295 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.070726 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 144.846093 # Average occupied blocks per context -system.cpu.icache.overall_accesses 1732 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 36454.794521 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35105.084746 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.070743 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 144.881554 # Average occupied blocks per context +system.cpu.icache.overall_accesses 1703 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 36577.562327 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35100 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1367 # number of overall hits -system.cpu.icache.overall_miss_latency 13306000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.210739 # miss rate for overall accesses -system.cpu.icache.overall_misses 365 # number of overall misses -system.cpu.icache.overall_mshr_hits 70 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 10356000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.170323 # mshr miss rate for overall accesses +system.cpu.icache.overall_hits 1342 # number of overall hits +system.cpu.icache.overall_miss_latency 13204500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.211979 # miss rate for overall accesses +system.cpu.icache.overall_misses 361 # number of overall misses +system.cpu.icache.overall_mshr_hits 66 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 10354500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.173224 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 295 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 295 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 144.846093 # Cycle average of tags in use -system.cpu.icache.total_refs 1367 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 144.881554 # Cycle average of tags in use +system.cpu.icache.total_refs 1342 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 9434 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1551 # Number of branches executed +system.cpu.idleCycles 9457 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1545 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.676108 # Inst execution rate -system.cpu.iew.EXEC:refs 2970 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1306 # Number of stores executed +system.cpu.iew.EXEC:rate 0.675461 # Inst execution rate +system.cpu.iew.EXEC:refs 2952 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1295 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 14702 # num instructions consuming a value -system.cpu.iew.WB:count 15138 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.679703 # average fanout of values written-back +system.cpu.iew.WB:consumers 14668 # num instructions consuming a value +system.cpu.iew.WB:count 15056 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.677734 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 9993 # num instructions producing a value -system.cpu.iew.WB:rate 0.662669 # insts written-back per cycle -system.cpu.iew.WB:sent 15262 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 565 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 9941 # num instructions producing a value +system.cpu.iew.WB:rate 0.662006 # insts written-back per cycle +system.cpu.iew.WB:sent 15179 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 566 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 187 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2105 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2082 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 207 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1639 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 19184 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1664 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 710 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 15445 # Number of executed instructions +system.cpu.iew.iewDispStoreInsts 1617 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 19032 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1657 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 693 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 15362 # Number of executed instructions system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1504 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 1477 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 20 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 68 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.forwLoads 69 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 31 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 14 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1049 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 705 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 31 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 496 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.lsq.thread.0.squashedLoads 1026 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 683 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 497 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 23049 # number of integer regfile reads -system.cpu.int_regfile_writes 14062 # number of integer regfile writes -system.cpu.ipc 0.429391 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.429391 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 22959 # number of integer regfile reads +system.cpu.int_regfile_writes 13993 # number of integer regfile writes +system.cpu.ipc 0.431298 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.431298 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 12967 80.27% 80.29% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 80.29% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 80.29% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 80.29% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 80.29% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 80.29% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 80.29% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 80.29% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 80.29% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 80.29% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 80.29% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 80.29% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 80.29% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 80.29% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 80.29% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 80.29% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 80.29% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 80.29% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 80.29% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 80.29% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 80.29% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 80.29% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 80.29% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 80.29% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 80.29% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 80.29% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 80.29% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 80.29% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 80.29% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 1785 11.05% 91.34% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1399 8.66% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 12893 80.31% 80.33% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 80.33% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 1771 11.03% 91.36% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1387 8.64% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 16155 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 142 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.008790 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 16055 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 147 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.009156 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 97 68.31% 68.31% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 68.31% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 68.31% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 68.31% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 68.31% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 68.31% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 68.31% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 68.31% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 68.31% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 68.31% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 68.31% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 68.31% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 68.31% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 68.31% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 68.31% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 68.31% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 68.31% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 68.31% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 68.31% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 68.31% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 68.31% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 68.31% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 68.31% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 68.31% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 68.31% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 68.31% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 68.31% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 68.31% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 68.31% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 26 18.31% 86.62% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 19 13.38% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 101 68.71% 68.71% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 68.71% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 68.71% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 68.71% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 68.71% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 68.71% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 68.71% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 68.71% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 68.71% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 68.71% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 68.71% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 68.71% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 68.71% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 68.71% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 68.71% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 68.71% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 68.71% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 68.71% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 68.71% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 68.71% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 68.71% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 68.71% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 68.71% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 68.71% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 68.71% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 68.71% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 68.71% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 68.71% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 68.71% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 27 18.37% 87.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 19 12.93% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 13410 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.204698 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.912453 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 13286 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.208415 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.917020 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 8282 61.76% 61.76% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 1307 9.75% 71.51% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 986 7.35% 78.86% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 745 5.56% 84.41% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 788 5.88% 90.29% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 587 4.38% 94.67% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 498 3.71% 98.38% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 170 1.27% 99.65% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 8201 61.73% 61.73% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 1290 9.71% 71.44% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 986 7.42% 78.86% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 726 5.46% 84.32% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 782 5.89% 90.21% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 580 4.37% 94.57% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 507 3.82% 98.39% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 167 1.26% 99.65% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::8 47 0.35% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 13410 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.707188 # Inst issue rate +system.cpu.iq.ISSUE:issued_per_cycle::total 13286 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.705931 # Inst issue rate system.cpu.iq.fp_alu_accesses 5 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 9 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 16288 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 45906 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 15134 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 27963 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 19151 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 16155 # Number of instructions issued +system.cpu.iq.int_alu_accesses 16193 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 45588 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 15052 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 27650 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 18999 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 16055 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 33 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 8758 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8610 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 20 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 11055 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 10851 # Number of squashed operands that are examined and possibly removed from graph system.cpu.l2cache.ReadExReq_accesses 77 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34616.883117 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31389.610390 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2665500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 34603.896104 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31396.103896 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2664500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 77 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2417000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2417500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 77 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 362 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34245.833333 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34244.444444 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31040.277778 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 12328500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 12328000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.994475 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 360 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 11174500 # number of ReadReq MSHR miss cycles @@ -389,31 +389,31 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 439 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34311.212815 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31101.830664 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 34307.780320 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31102.974828 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 14994000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 14992500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.995444 # miss rate for demand accesses system.cpu.l2cache.demand_misses 437 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 13591500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 13592000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.995444 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 437 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.005436 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 178.138745 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.005438 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 178.188786 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 439 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34311.212815 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31101.830664 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 34307.780320 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31102.974828 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 14994000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 14992500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.995444 # miss rate for overall accesses system.cpu.l2cache.overall_misses 437 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 13591500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 13592000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.995444 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 437 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -421,39 +421,39 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 178.138745 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 178.188786 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 23 # Number of conflicting loads. +system.cpu.memDep0.conflictingLoads 14 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 2105 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1639 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 6856 # number of misc regfile reads -system.cpu.numCycles 22844 # number of cpu cycles simulated +system.cpu.memDep0.insertedLoads 2082 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1617 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 6812 # number of misc regfile reads +system.cpu.numCycles 22743 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 565 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 9368 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 51 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 7399 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 247 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:IQFullEvents 52 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 7327 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 248 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 44700 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 21187 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 19905 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 3124 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1504 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 378 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 10537 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:RenameLookups 44292 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 21008 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 19746 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 3097 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1477 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 380 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 10378 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:fp_rename_lookups 16 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 44684 # Number of integer rename lookups +system.cpu.rename.RENAME:int_rename_lookups 44276 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 440 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 32 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 1476 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 1483 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 31 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 30950 # The number of ROB reads -system.cpu.rob.rob_writes 39896 # The number of ROB writes +system.cpu.rob.rob_reads 30699 # The number of ROB reads +system.cpu.rob.rob_writes 39564 # The number of ROB writes system.cpu.timesIdled 184 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 11 # Number of system calls diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index 0109e92d9..cf8986b59 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -115,6 +115,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -413,6 +414,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -448,6 +450,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=1000 max_miss_count=0 mshrs=10 diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index e012c16b8..c3da6f6a9 100755 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:39 -M5 executing on burrito +M5 compiled Mar 17 2011 21:44:37 +M5 started Mar 17 2011 21:44:41 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -16,4 +15,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. Hello world! Hello world! -Exiting @ tick 14139000 because target called exit() +Exiting @ tick 14058000 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 816b3e660..aedd2d287 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 41761 # Simulator instruction rate (inst/s) -host_mem_usage 224488 # Number of bytes of host memory used -host_seconds 0.31 # Real time elapsed on the host -host_tick_rate 46181742 # Simulator tick rate (ticks/s) +host_inst_rate 72321 # Simulator instruction rate (inst/s) +host_mem_usage 206332 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host +host_tick_rate 79473363 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 12773 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 14139000 # Number of ticks simulated +sim_ticks 14058000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 916 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 4600 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 174 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 1521 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 3069 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 5341 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 654 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.BTBHits 845 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 4555 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 177 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 1551 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 3023 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 5318 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 660 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches::0 1051 # Number of branches committed system.cpu.commit.COM:branches::1 1051 # Number of branches committed system.cpu.commit.COM:branches::total 2102 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 132 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 151 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 22158 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.577985 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.311672 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 22336 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.573379 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.337408 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 16375 73.90% 73.90% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 2877 12.98% 86.89% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 1274 5.75% 92.63% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 599 2.70% 95.34% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 362 1.63% 96.97% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 252 1.14% 98.11% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 188 0.85% 98.96% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 99 0.45% 99.40% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 132 0.60% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 16656 74.57% 74.57% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 2886 12.92% 87.49% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 1149 5.14% 92.64% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 571 2.56% 95.19% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 362 1.62% 96.81% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 238 1.07% 97.88% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 197 0.88% 98.76% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 126 0.56% 99.32% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 151 0.68% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 22158 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 22336 # Number of insts commited each cycle system.cpu.commit.COM:count::0 6404 # Number of instructions committed system.cpu.commit.COM:count::1 6403 # Number of instructions committed system.cpu.commit.COM:count::total 12807 # Number of instructions committed @@ -64,80 +64,80 @@ system.cpu.commit.COM:refs::total 4100 # Nu system.cpu.commit.COM:swp_count::0 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count::1 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count::total 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 1116 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 1135 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 10253 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10106 # The number of squashed insts skipped by commit system.cpu.committedInsts::0 6387 # Number of Instructions Simulated system.cpu.committedInsts::1 6386 # Number of Instructions Simulated system.cpu.committedInsts_total 12773 # Number of Instructions Simulated -system.cpu.cpi::0 4.427587 # CPI: Cycles Per Instruction -system.cpu.cpi::1 4.428281 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.213967 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 3796 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 36145.962733 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36145.962733 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::0 36908.415842 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 3474 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency::0 11639000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11639000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.084826 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 322 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits::0 120 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 120 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency::0 7455500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7455500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.053214 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053214 # mshr miss rate for ReadReq accesses +system.cpu.cpi::0 4.402223 # CPI: Cycles Per Instruction +system.cpu.cpi::1 4.402913 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.201284 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 3727 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 36433.554817 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36433.554817 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::0 36821.782178 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 3426 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency::0 10966500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10966500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.080762 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 301 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits::0 99 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 99 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency::0 7438000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7438000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.054199 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054199 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses::0 202 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 202 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 32784.604520 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 32784.604520 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::0 36119.863014 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 1022 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency::0 23211500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23211500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.409249 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 708 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits::0 562 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 562 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency::0 5273500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5273500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency::0 32498.595506 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 32498.595506 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::0 35993.150685 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 1018 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency::0 23139000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23139000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.411561 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 712 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits::0 566 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 566 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency::0 5255000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5255000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses::0 146 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 12.919540 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 12.770115 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 5526 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 33835.436893 # average overall miss latency +system.cpu.dcache.demand_accesses 5457 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 33667.818361 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 0 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33835.436893 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::0 36577.586207 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33667.818361 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::0 36474.137931 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.dcache.demand_hits 4496 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency::0 34850500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_hits 4444 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency::0 34105500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34850500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.186392 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1030 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits::0 682 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_miss_latency::total 34105500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.185633 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1013 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits::0 665 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 682 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency::0 12729000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::total 665 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency::0 12693000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12729000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.062975 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_latency::total 12693000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.063771 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.062975 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063771 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses::0 348 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 348 # number of demand (read+write) MSHR misses @@ -146,33 +146,33 @@ system.cpu.dcache.mshr_cap_events::0 0 # nu system.cpu.dcache.mshr_cap_events::1 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events::total 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.053836 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 220.510583 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 5526 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 33835.436893 # average overall miss latency +system.cpu.dcache.occ_%::0 0.053796 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 220.347711 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 5457 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 33667.818361 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 0 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 33835.436893 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::0 36577.586207 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency::total 33667.818361 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::0 36474.137931 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 4496 # number of overall hits -system.cpu.dcache.overall_miss_latency::0 34850500 # number of overall miss cycles +system.cpu.dcache.overall_hits 4444 # number of overall hits +system.cpu.dcache.overall_miss_latency::0 34105500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::1 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34850500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.186392 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1030 # number of overall misses -system.cpu.dcache.overall_mshr_hits::0 682 # number of overall MSHR hits +system.cpu.dcache.overall_miss_latency::total 34105500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.185633 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1013 # number of overall misses +system.cpu.dcache.overall_mshr_hits::0 665 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::1 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 682 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency::0 12729000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_hits::total 665 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency::0 12693000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12729000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.062975 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_latency::total 12693000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.063771 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.062975 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063771 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses::0 348 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::1 0 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 348 # number of overall MSHR misses @@ -189,114 +189,114 @@ system.cpu.dcache.sampled_refs 348 # Sa system.cpu.dcache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 220.510583 # Cycle average of tags in use -system.cpu.dcache.total_refs 4496 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 220.347711 # Cycle average of tags in use +system.cpu.dcache.total_refs 4444 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks::0 0 # number of writebacks system.cpu.dcache.writebacks::1 0 # number of writebacks system.cpu.dcache.writebacks::total 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 4667 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 414 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 569 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 26624 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 32585 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 4771 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 2039 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 734 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 167 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 6131 # DTB accesses +system.cpu.decode.DECODE:BlockedCycles 4700 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 432 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 582 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 26467 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 33032 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 4744 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1971 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 600 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 114 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 6011 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 5993 # DTB hits -system.cpu.dtb.data_misses 138 # DTB misses +system.cpu.dtb.data_hits 5860 # DTB hits +system.cpu.dtb.data_misses 151 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 3997 # DTB read accesses +system.cpu.dtb.read_accesses 3932 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 3913 # DTB read hits -system.cpu.dtb.read_misses 84 # DTB read misses -system.cpu.dtb.write_accesses 2134 # DTB write accesses +system.cpu.dtb.read_hits 3840 # DTB read hits +system.cpu.dtb.read_misses 92 # DTB read misses +system.cpu.dtb.write_accesses 2079 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 2080 # DTB write hits -system.cpu.dtb.write_misses 54 # DTB write misses -system.cpu.fetch.Branches 5341 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 3993 # Number of cache lines fetched -system.cpu.fetch.Cycles 5113 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 611 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 29881 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 56 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 1641 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.188868 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 3993 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1570 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.056650 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 22205 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.345688 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.736511 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.write_hits 2020 # DTB write hits +system.cpu.dtb.write_misses 59 # DTB write misses +system.cpu.fetch.Branches 5318 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 3965 # Number of cache lines fetched +system.cpu.fetch.Cycles 5044 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 575 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 29681 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 55 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 1624 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.189138 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 3965 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1505 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.055625 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 22371 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.326762 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.728526 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 17092 76.97% 76.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 418 1.88% 78.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 346 1.56% 80.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 428 1.93% 82.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 443 2.00% 84.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 320 1.44% 85.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 433 1.95% 87.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 283 1.27% 89.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2442 11.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 17327 77.45% 77.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 412 1.84% 79.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 325 1.45% 80.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 422 1.89% 82.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 410 1.83% 84.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 313 1.40% 85.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 439 1.96% 87.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 270 1.21% 89.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2453 10.97% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 22205 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 22371 # Number of instructions fetched each cycle (Total) system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 3993 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 35767.942584 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35767.942584 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::0 35489.482201 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 3157 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency::0 29902000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 29902000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.209366 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 836 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits::0 218 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 218 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency::0 21932500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21932500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.154771 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.154771 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_accesses 3965 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 36242.350061 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36242.350061 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::0 35491.100324 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 3148 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency::0 29610000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 29610000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.206053 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 817 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits::0 199 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 199 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency::0 21933500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 21933500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.155864 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.155864 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses::0 618 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 618 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 5.108414 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.093851 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 3993 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 35767.942584 # average overall miss latency +system.cpu.icache.demand_accesses 3965 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 36242.350061 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 0 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35767.942584 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::0 35489.482201 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency::total 36242.350061 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::0 35491.100324 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.icache.demand_hits 3157 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency::0 29902000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_hits 3148 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency::0 29610000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 29902000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.209366 # miss rate for demand accesses -system.cpu.icache.demand_misses 836 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits::0 218 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_miss_latency::total 29610000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.206053 # miss rate for demand accesses +system.cpu.icache.demand_misses 817 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits::0 199 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 218 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency::0 21932500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_hits::total 199 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency::0 21933500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21932500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.154771 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency::total 21933500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.155864 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.154771 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.155864 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses::0 618 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 618 # number of demand (read+write) MSHR misses @@ -305,33 +305,33 @@ system.cpu.icache.mshr_cap_events::0 0 # nu system.cpu.icache.mshr_cap_events::1 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events::total 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.155666 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 318.803897 # Average occupied blocks per context -system.cpu.icache.overall_accesses 3993 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 35767.942584 # average overall miss latency +system.cpu.icache.occ_%::0 0.155654 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 318.780075 # Average occupied blocks per context +system.cpu.icache.overall_accesses 3965 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 36242.350061 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 0 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35767.942584 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::0 35489.482201 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency::total 36242.350061 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::0 35491.100324 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 3157 # number of overall hits -system.cpu.icache.overall_miss_latency::0 29902000 # number of overall miss cycles +system.cpu.icache.overall_hits 3148 # number of overall hits +system.cpu.icache.overall_miss_latency::0 29610000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::1 0 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 29902000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.209366 # miss rate for overall accesses -system.cpu.icache.overall_misses 836 # number of overall misses -system.cpu.icache.overall_mshr_hits::0 218 # number of overall MSHR hits +system.cpu.icache.overall_miss_latency::total 29610000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.206053 # miss rate for overall accesses +system.cpu.icache.overall_misses 817 # number of overall misses +system.cpu.icache.overall_mshr_hits::0 199 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::1 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 218 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency::0 21932500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_hits::total 199 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency::0 21933500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21932500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.154771 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency::total 21933500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.155864 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.154771 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.155864 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses::0 618 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::1 0 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 618 # number of overall MSHR misses @@ -348,284 +348,284 @@ system.cpu.icache.sampled_refs 618 # Sa system.cpu.icache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 318.803897 # Cycle average of tags in use -system.cpu.icache.total_refs 3157 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 318.780075 # Cycle average of tags in use +system.cpu.icache.total_refs 3148 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks::0 0 # number of writebacks system.cpu.icache.writebacks::1 0 # number of writebacks system.cpu.icache.writebacks::total 0 # number of writebacks -system.cpu.idleCycles 6074 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches::0 1552 # Number of branches executed -system.cpu.iew.EXEC:branches::1 1552 # Number of branches executed -system.cpu.iew.EXEC:branches::total 3104 # Number of branches executed -system.cpu.iew.EXEC:nop::0 64 # number of nop insts executed +system.cpu.idleCycles 5746 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches::0 1549 # Number of branches executed +system.cpu.iew.EXEC:branches::1 1545 # Number of branches executed +system.cpu.iew.EXEC:branches::total 3094 # Number of branches executed +system.cpu.iew.EXEC:nop::0 67 # number of nop insts executed system.cpu.iew.EXEC:nop::1 70 # number of nop insts executed -system.cpu.iew.EXEC:nop::total 134 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.666325 # Inst execution rate -system.cpu.iew.EXEC:refs::0 3105 # number of memory reference insts executed -system.cpu.iew.EXEC:refs::1 3045 # number of memory reference insts executed -system.cpu.iew.EXEC:refs::total 6150 # number of memory reference insts executed -system.cpu.iew.EXEC:stores::0 1087 # Number of stores executed -system.cpu.iew.EXEC:stores::1 1064 # Number of stores executed -system.cpu.iew.EXEC:stores::total 2151 # Number of stores executed +system.cpu.iew.EXEC:nop::total 137 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.665505 # Inst execution rate +system.cpu.iew.EXEC:refs::0 3042 # number of memory reference insts executed +system.cpu.iew.EXEC:refs::1 2988 # number of memory reference insts executed +system.cpu.iew.EXEC:refs::total 6030 # number of memory reference insts executed +system.cpu.iew.EXEC:stores::0 1059 # Number of stores executed +system.cpu.iew.EXEC:stores::1 1037 # Number of stores executed +system.cpu.iew.EXEC:stores::total 2096 # Number of stores executed system.cpu.iew.EXEC:swp::0 0 # number of swp insts executed system.cpu.iew.EXEC:swp::1 0 # number of swp insts executed system.cpu.iew.EXEC:swp::total 0 # number of swp insts executed -system.cpu.iew.WB:consumers::0 5852 # num instructions consuming a value -system.cpu.iew.WB:consumers::1 5867 # num instructions consuming a value -system.cpu.iew.WB:consumers::total 11719 # num instructions consuming a value -system.cpu.iew.WB:count::0 9073 # cumulative count of insts written-back -system.cpu.iew.WB:count::1 9067 # cumulative count of insts written-back -system.cpu.iew.WB:count::total 18140 # cumulative count of insts written-back -system.cpu.iew.WB:fanout::0 0.775290 # average fanout of values written-back -system.cpu.iew.WB:fanout::1 0.774501 # average fanout of values written-back -system.cpu.iew.WB:fanout::total 1.549792 # average fanout of values written-back +system.cpu.iew.WB:consumers::0 5857 # num instructions consuming a value +system.cpu.iew.WB:consumers::1 5876 # num instructions consuming a value +system.cpu.iew.WB:consumers::total 11733 # num instructions consuming a value +system.cpu.iew.WB:count::0 9007 # cumulative count of insts written-back +system.cpu.iew.WB:count::1 9010 # cumulative count of insts written-back +system.cpu.iew.WB:count::total 18017 # cumulative count of insts written-back +system.cpu.iew.WB:fanout::0 0.769336 # average fanout of values written-back +system.cpu.iew.WB:fanout::1 0.769401 # average fanout of values written-back +system.cpu.iew.WB:fanout::total 1.538737 # average fanout of values written-back system.cpu.iew.WB:penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized::total 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers::0 4537 # num instructions producing a value -system.cpu.iew.WB:producers::1 4544 # num instructions producing a value -system.cpu.iew.WB:producers::total 9081 # num instructions producing a value -system.cpu.iew.WB:rate::0 0.320839 # insts written-back per cycle -system.cpu.iew.WB:rate::1 0.320627 # insts written-back per cycle -system.cpu.iew.WB:rate::total 0.641465 # insts written-back per cycle -system.cpu.iew.WB:sent::0 9197 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent::1 9165 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent::total 18362 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 1270 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 840 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 4751 # Number of dispatched load instructions +system.cpu.iew.WB:producers::0 4506 # num instructions producing a value +system.cpu.iew.WB:producers::1 4521 # num instructions producing a value +system.cpu.iew.WB:producers::total 9027 # num instructions producing a value +system.cpu.iew.WB:rate::0 0.320340 # insts written-back per cycle +system.cpu.iew.WB:rate::1 0.320447 # insts written-back per cycle +system.cpu.iew.WB:rate::total 0.640787 # insts written-back per cycle +system.cpu.iew.WB:sent::0 9150 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent::1 9113 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent::total 18263 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 1313 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 965 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 4691 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 46 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 669 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 2526 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 23137 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts::0 2018 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 1981 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 3999 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1059 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 18843 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 813 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 2450 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 22978 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts::0 1983 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 1951 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 3934 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1099 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 18712 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 39 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 2039 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 64 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1971 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 57 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 56 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 68 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 15 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1198 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 429 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 1178 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 386 # Number of stores squashed system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.1.forwLoads 58 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.1.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.1.forwLoads 55 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.1.ignoredResponses 10 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.1.memOrderViolation 63 # Number of memory ordering violations +system.cpu.iew.lsq.thread.1.memOrderViolation 13 # Number of memory ordering violations system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.1.squashedLoads 1183 # Number of loads squashed -system.cpu.iew.lsq.thread.1.squashedStores 367 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 131 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 1010 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 260 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 23900 # number of integer regfile reads -system.cpu.int_regfile_writes 13586 # number of integer regfile writes -system.cpu.ipc::0 0.225857 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.225821 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.451678 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.1.squashedLoads 1143 # Number of loads squashed +system.cpu.iew.lsq.thread.1.squashedStores 334 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1056 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 257 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 23704 # number of integer regfile reads +system.cpu.int_regfile_writes 13551 # number of integer regfile writes +system.cpu.ipc::0 0.227158 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.227122 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.454280 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 6654 67.06% 67.08% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 67.09% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 67.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 2121 21.37% 88.48% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1143 11.52% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 6672 67.35% 67.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 67.38% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.38% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 67.40% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.40% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.40% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.40% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.40% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.40% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.40% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.40% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.40% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.40% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.40% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.40% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.40% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.40% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.40% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.40% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.40% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.40% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.40% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.40% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.40% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.40% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.40% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.40% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.40% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.40% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 2121 21.41% 88.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1109 11.19% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 9923 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 9907 # Type of FU issued system.cpu.iq.ISSUE:FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::IntAlu 6748 67.62% 67.64% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::IntMult 1 0.01% 67.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::IntDiv 0 0.00% 67.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::FloatAdd 2 0.02% 67.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::FloatCmp 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::FloatCvt 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::FloatMult 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::FloatDiv 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::FloatSqrt 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::SimdAdd 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::SimdAddAcc 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::SimdAlu 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::SimdCmp 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::SimdCvt 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::SimdMisc 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::SimdMult 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::SimdMultAcc 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::SimdShift 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::SimdShiftAcc 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::SimdSqrt 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::SimdFloatAdd 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::SimdFloatAlu 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::SimdFloatCmp 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::SimdFloatCvt 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::SimdFloatDiv 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::SimdFloatMisc 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::SimdFloatMult 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::SimdFloatMultAcc 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::SimdFloatSqrt 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::MemRead 2103 21.07% 88.75% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::MemWrite 1123 11.25% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::IntAlu 6738 68.03% 68.05% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::IntMult 1 0.01% 68.06% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::IntDiv 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatAdd 2 0.02% 68.08% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatCmp 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatCvt 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatMult 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatDiv 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatSqrt 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdAdd 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdAddAcc 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdAlu 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdCmp 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdCvt 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdMisc 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdMult 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdMultAcc 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdShift 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdShiftAcc 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdSqrt 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdFloatAdd 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdFloatAlu 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdFloatCmp 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdFloatCvt 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdFloatDiv 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdFloatMisc 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdFloatMult 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdFloatMultAcc 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdFloatSqrt 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::MemRead 2064 20.84% 88.92% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::MemWrite 1097 11.08% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::total 9979 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::total 9904 # Type of FU issued system.cpu.iq.ISSUE:FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::IntAlu 13402 67.34% 67.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::IntMult 2 0.01% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::IntDiv 0 0.00% 67.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::FloatAdd 4 0.02% 67.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::FloatCmp 0 0.00% 67.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::FloatCvt 0 0.00% 67.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::FloatMult 0 0.00% 67.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::FloatDiv 0 0.00% 67.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::FloatSqrt 0 0.00% 67.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::SimdAdd 0 0.00% 67.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::SimdAddAcc 0 0.00% 67.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::SimdAlu 0 0.00% 67.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::SimdCmp 0 0.00% 67.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::SimdCvt 0 0.00% 67.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::SimdMisc 0 0.00% 67.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::SimdMult 0 0.00% 67.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::SimdMultAcc 0 0.00% 67.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::SimdShift 0 0.00% 67.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::SimdShiftAcc 0 0.00% 67.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::SimdSqrt 0 0.00% 67.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::SimdFloatAdd 0 0.00% 67.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::SimdFloatAlu 0 0.00% 67.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::SimdFloatCmp 0 0.00% 67.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::SimdFloatCvt 0 0.00% 67.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::SimdFloatDiv 0 0.00% 67.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::SimdFloatMisc 0 0.00% 67.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::SimdFloatMult 0 0.00% 67.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::SimdFloatMultAcc 0 0.00% 67.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::SimdFloatSqrt 0 0.00% 67.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::MemRead 4224 21.22% 88.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::MemWrite 2266 11.39% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::IntAlu 13410 67.69% 67.71% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::IntMult 2 0.01% 67.72% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::IntDiv 0 0.00% 67.72% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatAdd 4 0.02% 67.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatCmp 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatCvt 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatMult 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatDiv 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatSqrt 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdAdd 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdAddAcc 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdAlu 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdCmp 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdCvt 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdMisc 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdMult 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdMultAcc 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdShift 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdShiftAcc 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdSqrt 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdFloatAdd 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdFloatAlu 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdFloatCmp 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdFloatCvt 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdFloatDiv 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdFloatMisc 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdFloatMult 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdFloatMultAcc 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdFloatSqrt 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::MemRead 4185 21.12% 88.86% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::MemWrite 2206 11.14% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::total 19902 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt::0 80 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt::1 85 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt::total 165 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate::0 0.004020 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate::1 0.004271 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate::total 0.008291 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type::total 19811 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt::0 76 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt::1 88 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt::total 164 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate::0 0.003836 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate::1 0.004442 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate::total 0.008278 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 16 9.70% 9.70% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 9.70% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 89 53.94% 63.64% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 60 36.36% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 10 6.10% 6.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 6.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 6.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 6.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 6.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 6.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 6.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 6.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 6.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 6.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 6.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 6.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 6.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 6.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 6.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 6.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 6.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 6.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 6.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 6.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 6.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 6.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 6.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 6.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 6.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 6.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 6.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 6.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 6.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 90 54.88% 60.98% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 64 39.02% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 22205 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.896285 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.439530 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 22371 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.885566 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.449509 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 13672 61.57% 61.57% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 3186 14.35% 75.92% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 2211 9.96% 85.88% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 1439 6.48% 92.36% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 897 4.04% 96.40% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 509 2.29% 98.69% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 214 0.96% 99.65% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 56 0.25% 99.91% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 21 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 13920 62.22% 62.22% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 3143 14.05% 76.27% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 2295 10.26% 86.53% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 1308 5.85% 92.38% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 818 3.66% 96.04% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 557 2.49% 98.52% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 231 1.03% 99.56% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 81 0.36% 99.92% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 18 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 22205 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.703773 # Inst issue rate +system.cpu.iq.ISSUE:issued_per_cycle::total 22371 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.704592 # Inst issue rate system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 20041 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 62207 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 18120 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 32069 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 22957 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 19902 # Number of instructions issued +system.cpu.iq.int_alu_accesses 19949 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 62191 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 17997 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 31607 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 22795 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 19811 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 9000 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 75 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8766 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 76 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 5071 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 4974 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 4049 # ITB accesses +system.cpu.itb.fetch_accesses 4020 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 3993 # ITB hits -system.cpu.itb.fetch_misses 56 # ITB misses +system.cpu.itb.fetch_hits 3965 # ITB hits +system.cpu.itb.fetch_misses 55 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -635,30 +635,30 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 146 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency::0 34643.835616 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34643.835616 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::0 31544.520548 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency::0 5058000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5058000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency::0 34506.849315 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34506.849315 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::0 31441.780822 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency::0 5038000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5038000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 146 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::0 4605500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4605500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::0 4590500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4590500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses::0 146 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 820 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency::0 34537.897311 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34537.897311 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::0 31396.088020 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::0 34518.948655 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34518.948655 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::0 31380.195599 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency::0 28252000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 28252000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::0 28236500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 28236500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.997561 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 818 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::0 25682000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25682000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::0 25669000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25669000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::0 0.997561 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997561 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses::0 818 # number of ReadReq MSHR misses @@ -672,24 +672,24 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 27000 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 966 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency::0 34553.941909 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::0 34517.116183 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::1 0 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34553.941909 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::0 31418.568465 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34517.116183 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::0 31389.522822 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency::0 33310000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::0 33274500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 33310000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 33274500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.997930 # miss rate for demand accesses system.cpu.l2cache.demand_misses 964 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits::0 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency::0 30287500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::0 30259500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30287500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30259500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate::0 0.997930 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.997930 # mshr miss rate for demand accesses @@ -701,30 +701,30 @@ system.cpu.l2cache.mshr_cap_events::0 0 # nu system.cpu.l2cache.mshr_cap_events::1 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events::total 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.013480 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 441.702410 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.013478 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 441.662390 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 966 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency::0 34553.941909 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::0 34517.116183 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::1 0 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34553.941909 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::0 31418.568465 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34517.116183 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::0 31389.522822 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency::0 33310000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::0 33274500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::1 0 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 33310000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 33274500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.997930 # miss rate for overall accesses system.cpu.l2cache.overall_misses 964 # number of overall misses system.cpu.l2cache.overall_mshr_hits::0 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::1 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency::0 30287500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::0 30259500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30287500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30259500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate::0 0.997930 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997930 # mshr miss rate for overall accesses @@ -744,47 +744,47 @@ system.cpu.l2cache.sampled_refs 818 # Sa system.cpu.l2cache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 441.702410 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 441.662390 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks::0 0 # number of writebacks system.cpu.l2cache.writebacks::1 0 # number of writebacks system.cpu.l2cache.writebacks::total 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 43 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 2383 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1294 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep1.conflictingLoads 22 # Number of conflicting loads. -system.cpu.memDep1.conflictingStores 7 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 2368 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1232 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 2363 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1251 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 0 # Number of conflicting loads. +system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. +system.cpu.memDep1.insertedLoads 2328 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1199 # Number of stores inserted to the mem dependence unit. system.cpu.misc_regfile_reads 2 # number of misc regfile reads system.cpu.misc_regfile_writes 2 # number of misc regfile writes -system.cpu.numCycles 28279 # number of cpu cycles simulated +system.cpu.numCycles 28117 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 2728 # Number of cycles rename is blocking +system.cpu.rename.RENAME:BlockCycles 2820 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 9166 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 33046 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1284 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:IdleCycles 33480 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1251 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 31631 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 25294 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 18871 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 4411 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 2039 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 1326 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 9705 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:RenameLookups 31536 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 25241 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 18899 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 4323 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1971 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1300 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 9733 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:fp_rename_lookups 34 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 31597 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 679 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:int_rename_lookups 31502 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 667 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 50 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 3216 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 3351 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 38 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 106394 # The number of ROB reads -system.cpu.rob.rob_writes 48170 # The number of ROB writes -system.cpu.timesIdled 276 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rob.rob_reads 106938 # The number of ROB reads +system.cpu.rob.rob_writes 47804 # The number of ROB writes +system.cpu.timesIdled 269 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini index 4c6ef2b94..4308ebe8c 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -115,6 +115,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -413,6 +414,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -448,6 +450,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=1000 max_miss_count=0 mshrs=10 diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout index a2a0eb0e5..1c0d12619 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:13:30 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:13:49 -M5 executing on burrito +M5 compiled Mar 17 2011 23:04:27 +M5 started Mar 17 2011 23:04:36 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +22,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 18656000 because target called exit() +Exiting @ tick 18633000 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 7ae6650a8..d6c8de2b4 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 30834 # Simulator instruction rate (inst/s) -host_mem_usage 224180 # Number of bytes of host memory used -host_seconds 0.47 # Real time elapsed on the host -host_tick_rate 39786625 # Simulator tick rate (ticks/s) +host_inst_rate 81712 # Simulator instruction rate (inst/s) +host_mem_usage 206196 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host +host_tick_rate 105251575 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 14449 # Number of instructions simulated sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 18656000 # Number of ticks simulated +sim_ticks 18633000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 2698 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 5085 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 2697 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 5067 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.BPredUnit.condIncorrect 714 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 5172 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 5172 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 5154 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 5154 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 3359 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 84 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 86 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 27579 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.550237 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.187070 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 27481 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.552200 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.190718 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 19793 71.77% 71.77% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 4521 16.39% 88.16% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 1461 5.30% 93.46% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 765 2.77% 96.23% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 373 1.35% 97.59% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 256 0.93% 98.51% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 289 1.05% 99.56% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 37 0.13% 99.70% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 84 0.30% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 19704 71.70% 71.70% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 4516 16.43% 88.13% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 1458 5.31% 93.44% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 763 2.78% 96.22% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 370 1.35% 97.56% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 256 0.93% 98.49% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 290 1.06% 99.55% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 38 0.14% 99.69% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 86 0.31% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 27579 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 27481 # Number of insts commited each cycle system.cpu.commit.COM:count 15175 # Number of instructions committed system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 0 # Number of function calls committed. @@ -47,254 +47,254 @@ system.cpu.commit.COM:swp_count 0 # Nu system.cpu.commit.branchMispredicts 714 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 5133 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5051 # The number of squashed insts skipped by commit system.cpu.committedInsts 14449 # Number of Instructions Simulated system.cpu.committedInsts_total 14449 # Number of Instructions Simulated -system.cpu.cpi 2.582393 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.582393 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 2777 # number of ReadReq accesses(hits+misses) +system.cpu.cpi 2.579210 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.579210 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 2764 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 33620.967742 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35563.492063 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2653 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 2640 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 4169000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.044653 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate 0.044863 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 124 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 61 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 2240500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.022686 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.022793 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 63 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 35892.156863 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35843.373494 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 35890.931373 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35837.349398 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 1034 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 14644000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 14643500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.282940 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 408 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 325 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2975000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2974500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.057559 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 83 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 25.294521 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 25.205479 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 4219 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 35362.781955 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35722.602740 # average overall mshr miss latency -system.cpu.dcache.demand_hits 3687 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 18813000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.126096 # miss rate for demand accesses +system.cpu.dcache.demand_accesses 4206 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 35361.842105 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35719.178082 # average overall mshr miss latency +system.cpu.dcache.demand_hits 3674 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 18812500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.126486 # miss rate for demand accesses system.cpu.dcache.demand_misses 532 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 386 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 5215500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.034605 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_latency 5215000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.034712 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.024937 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 102.143173 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 4219 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 35362.781955 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35722.602740 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.024936 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 102.139862 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 4206 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 35361.842105 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35719.178082 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 3687 # number of overall hits -system.cpu.dcache.overall_miss_latency 18813000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.126096 # miss rate for overall accesses +system.cpu.dcache.overall_hits 3674 # number of overall hits +system.cpu.dcache.overall_miss_latency 18812500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.126486 # miss rate for overall accesses system.cpu.dcache.overall_misses 532 # number of overall misses system.cpu.dcache.overall_mshr_hits 386 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 5215500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.034605 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_latency 5215000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.034712 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 102.143173 # Cycle average of tags in use -system.cpu.dcache.total_refs 3693 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 102.139862 # Cycle average of tags in use +system.cpu.dcache.total_refs 3680 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 7077 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 23586 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 13112 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 7266 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1178 # Number of cycles decode is squashing +system.cpu.decode.DECODE:BlockedCycles 7079 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 23444 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 13037 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 7241 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1159 # Number of cycles decode is squashing system.cpu.decode.DECODE:UnblockCycles 107 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 5172 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 4077 # Number of cache lines fetched -system.cpu.fetch.Cycles 7506 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 385 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 23982 # Number of instructions fetch has processed +system.cpu.fetch.Branches 5154 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 4051 # Number of cache lines fetched +system.cpu.fetch.Cycles 7481 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 377 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 23840 # Number of instructions fetch has processed system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 826 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.138611 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 4077 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 2698 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.642725 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 28740 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.834447 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.949360 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.SquashCycles 813 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.138299 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 4051 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 2697 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.639708 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 28623 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.832897 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.946042 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 21234 73.88% 73.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3581 12.46% 86.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 587 2.04% 88.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 509 1.77% 90.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 664 2.31% 92.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 529 1.84% 94.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 246 0.86% 95.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 197 0.69% 95.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1193 4.15% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 21142 73.86% 73.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3578 12.50% 86.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 587 2.05% 88.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 505 1.76% 90.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 662 2.31% 92.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 528 1.84% 94.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 244 0.85% 95.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 195 0.68% 95.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1182 4.13% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 28740 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 4077 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 34819.301848 # average ReadReq miss latency +system.cpu.fetch.rateDist::total 28623 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 4051 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35069.791667 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 34975.988701 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 3590 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 16957000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.119451 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 487 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 133 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_hits 3571 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 16833500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.118489 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 480 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 126 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_miss_latency 12381500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.086829 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.087386 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 354 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 10.141243 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 10.087571 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 4077 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 34819.301848 # average overall miss latency +system.cpu.icache.demand_accesses 4051 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35069.791667 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 34975.988701 # average overall mshr miss latency -system.cpu.icache.demand_hits 3590 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 16957000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.119451 # miss rate for demand accesses -system.cpu.icache.demand_misses 487 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_hits 3571 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 16833500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.118489 # miss rate for demand accesses +system.cpu.icache.demand_misses 480 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 126 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 12381500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.086829 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.087386 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 354 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.099779 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 204.347725 # Average occupied blocks per context -system.cpu.icache.overall_accesses 4077 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 34819.301848 # average overall miss latency +system.cpu.icache.occ_%::0 0.099792 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 204.373592 # Average occupied blocks per context +system.cpu.icache.overall_accesses 4051 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35069.791667 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 34975.988701 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 3590 # number of overall hits -system.cpu.icache.overall_miss_latency 16957000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.119451 # miss rate for overall accesses -system.cpu.icache.overall_misses 487 # number of overall misses -system.cpu.icache.overall_mshr_hits 133 # number of overall MSHR hits +system.cpu.icache.overall_hits 3571 # number of overall hits +system.cpu.icache.overall_miss_latency 16833500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.118489 # miss rate for overall accesses +system.cpu.icache.overall_misses 480 # number of overall misses +system.cpu.icache.overall_mshr_hits 126 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 12381500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.086829 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.087386 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 354 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 1 # number of replacements system.cpu.icache.sampled_refs 354 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 204.347725 # Cycle average of tags in use -system.cpu.icache.total_refs 3590 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 204.373592 # Cycle average of tags in use +system.cpu.icache.total_refs 3571 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 8573 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 3856 # Number of branches executed -system.cpu.iew.EXEC:nop 1087 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.470989 # Inst execution rate -system.cpu.iew.EXEC:refs 4619 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1763 # Number of stores executed +system.cpu.idleCycles 8644 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 3851 # Number of branches executed +system.cpu.iew.EXEC:nop 1086 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.469692 # Inst execution rate +system.cpu.iew.EXEC:refs 4584 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1742 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 9338 # num instructions consuming a value -system.cpu.iew.WB:count 17128 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.855858 # average fanout of values written-back +system.cpu.iew.WB:consumers 9307 # num instructions consuming a value +system.cpu.iew.WB:count 17063 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.856022 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 7992 # num instructions producing a value -system.cpu.iew.WB:rate 0.459036 # insts written-back per cycle -system.cpu.iew.WB:sent 17304 # cumulative count of insts sent to commit +system.cpu.iew.WB:producers 7967 # num instructions producing a value +system.cpu.iew.WB:rate 0.457858 # insts written-back per cycle +system.cpu.iew.WB:sent 17239 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 800 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 147 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 3058 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 566 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispLoadInsts 3044 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 564 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 420 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1925 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 20324 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 2856 # Number of load instructions executed +system.cpu.iew.iewDispStoreInsts 1894 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 20242 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 2842 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 465 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 17574 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 17504 # Number of executed instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1178 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 1159 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 31 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 30 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 54 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 30 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 832 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 477 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 54 # Number of memory order violations +system.cpu.iew.lsq.thread.0.squashedLoads 818 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 446 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 30 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 560 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 240 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 28146 # number of integer regfile reads -system.cpu.int_regfile_writes 15679 # number of integer regfile writes -system.cpu.ipc 0.387238 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.387238 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 28062 # number of integer regfile reads +system.cpu.int_regfile_writes 15640 # number of integer regfile writes +system.cpu.ipc 0.387716 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.387716 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 13302 73.74% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 73.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 2921 16.19% 89.93% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1816 10.07% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 13268 73.84% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 2908 16.18% 90.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1793 9.98% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 18039 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 17969 # Type of FU issued system.cpu.iq.ISSUE:fu_busy_cnt 125 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.006929 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate 0.006956 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntAlu 28 22.40% 22.40% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 22.40% # attempts to use FU when none available @@ -329,43 +329,43 @@ system.cpu.iq.ISSUE:fu_full::MemRead 29 23.20% 45.60% # at system.cpu.iq.ISSUE:fu_full::MemWrite 68 54.40% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 28740 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.627662 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.192852 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 28623 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.627782 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.193207 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 19886 69.19% 69.19% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 4262 14.83% 84.02% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 1894 6.59% 90.61% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 1722 5.99% 96.60% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 431 1.50% 98.10% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 279 0.97% 99.07% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 19805 69.19% 69.19% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 4241 14.82% 84.01% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 1891 6.61% 90.62% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 1717 6.00% 96.61% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 425 1.48% 98.10% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 278 0.97% 99.07% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::6 172 0.60% 99.67% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 80 0.28% 99.95% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 14 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 79 0.28% 99.95% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 15 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 28740 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.483451 # Inst issue rate +system.cpu.iq.ISSUE:issued_per_cycle::total 28623 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.482169 # Inst issue rate system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 18164 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 65024 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 17128 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 23367 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 18671 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 18039 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 566 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 4088 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.int_alu_accesses 18094 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 64767 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 17063 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 23189 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 18592 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 17969 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 564 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 4009 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 81 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 91 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 3603 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 89 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 3563 # Number of squashed operands that are examined and possibly removed from graph system.cpu.l2cache.ReadExReq_accesses 83 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34596.385542 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34590.361446 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31451.807229 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2871500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2871000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 83 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 2610500 # number of ReadExReq MSHR miss cycles @@ -390,10 +390,10 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 500 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34361.895161 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 34360.887097 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 31144.153226 # average overall mshr miss latency system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 17043500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 17043000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.992000 # miss rate for demand accesses system.cpu.l2cache.demand_misses 496 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits @@ -403,14 +403,14 @@ system.cpu.l2cache.demand_mshr_misses 496 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.007282 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 238.619810 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.007283 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 238.651434 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 500 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34361.895161 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34360.887097 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31144.153226 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 4 # number of overall hits -system.cpu.l2cache.overall_miss_latency 17043500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 17043000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.992000 # miss rate for overall accesses system.cpu.l2cache.overall_misses 496 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits @@ -422,38 +422,38 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 413 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 238.619810 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 238.651434 # Cycle average of tags in use system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads. +system.cpu.memDep0.conflictingLoads 8 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 3058 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1925 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 6238 # number of misc regfile reads +system.cpu.memDep0.insertedLoads 3044 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1894 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 6202 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes -system.cpu.numCycles 37313 # number of cpu cycles simulated +system.cpu.numCycles 37267 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 254 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 13832 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 13569 # Number of cycles rename is idle +system.cpu.rename.RENAME:IdleCycles 13492 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 112 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 40450 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 21815 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 19528 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 7042 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1178 # Number of cycles rename is squashing +system.cpu.rename.RENAME:RenameLookups 40241 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 21695 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 19448 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 7019 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1159 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 421 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 5696 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:int_rename_lookups 40450 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 6276 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 617 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 2691 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 583 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 46980 # The number of ROB reads -system.cpu.rob.rob_writes 41800 # The number of ROB writes -system.cpu.timesIdled 183 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:UndoneMaps 5616 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:int_rename_lookups 40241 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 6278 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 613 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 2673 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 579 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 46798 # The number of ROB reads +system.cpu.rob.rob_writes 41616 # The number of ROB writes +system.cpu.timesIdled 184 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 18 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini index 08b40bb1a..a3508244c 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini @@ -115,6 +115,7 @@ assoc=4 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=4 @@ -413,6 +414,7 @@ assoc=1 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=4 @@ -560,6 +562,7 @@ assoc=4 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=4 @@ -858,6 +861,7 @@ assoc=1 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=4 @@ -986,6 +990,7 @@ assoc=4 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=4 @@ -1284,6 +1289,7 @@ assoc=1 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=4 @@ -1412,6 +1418,7 @@ assoc=4 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=4 @@ -1710,6 +1717,7 @@ assoc=1 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=4 @@ -1748,6 +1756,7 @@ assoc=8 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=92 diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index d3d241630..7a384b968 100755 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -5,69 +5,68 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:13:30 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:13:39 -M5 executing on burrito +M5 compiled Mar 17 2011 23:04:27 +M5 started Mar 17 2011 23:09:03 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done [Iteration 1, Thread 2] Got lock [Iteration 1, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 1, Thread 3] Got lock -[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 1, Thread 1] Got lock -[Iteration 1, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 1, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 1, Thread 3] Got lock +[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3 Iteration 1 completed +[Iteration 2, Thread 3] Got lock +[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 2, Thread 1] Got lock -[Iteration 2, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 2, Thread 2] Got lock [Iteration 2, Thread 2] Critical section done, previously next=1, now next=2 -[Iteration 2, Thread 3] Got lock -[Iteration 2, Thread 3] Critical section done, previously next=2, now next=3 Iteration 2 completed +[Iteration 3, Thread 2] Got lock +[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 3, Thread 3] Got lock -[Iteration 3, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 3, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 3, Thread 1] Got lock [Iteration 3, Thread 1] Critical section done, previously next=3, now next=1 -[Iteration 3, Thread 2] Got lock -[Iteration 3, Thread 2] Critical section done, previously next=1, now next=2 Iteration 3 completed +[Iteration 4, Thread 1] Got lock +[Iteration 4, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 4, Thread 2] Got lock -[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 4, Thread 2] Critical section done, previously next=1, now next=2 [Iteration 4, Thread 3] Got lock [Iteration 4, Thread 3] Critical section done, previously next=2, now next=3 -[Iteration 4, Thread 1] Got lock -[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1 Iteration 4 completed -[Iteration 5, Thread 3] Got lock -[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 5, Thread 2] Got lock -[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 5, Thread 1] Got lock [Iteration 5, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 5, Thread 3] Got lock +[Iteration 5, Thread 3] Critical section done, previously next=1, now next=3 Iteration 5 completed [Iteration 6, Thread 1] Got lock [Iteration 6, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 6, Thread 3] Got lock -[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 6, Thread 2] Got lock -[Iteration 6, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 6, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 6, Thread 3] Got lock +[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3 Iteration 6 completed -[Iteration 7, Thread 2] Got lock -[Iteration 7, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 7, Thread 1] Got lock -[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 7, Thread 3] Got lock [Iteration 7, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 7, Thread 2] Got lock +[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2 Iteration 7 completed -[Iteration 8, Thread 2] Got lock -[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 8, Thread 3] Got lock -[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 8, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 8, Thread 2] Got lock +[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 8, Thread 1] Got lock -[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1 Iteration 8 completed [Iteration 9, Thread 2] Got lock [Iteration 9, Thread 2] Critical section done, previously next=0, now next=2 @@ -76,12 +75,12 @@ Iteration 8 completed [Iteration 9, Thread 1] Got lock [Iteration 9, Thread 1] Critical section done, previously next=3, now next=1 Iteration 9 completed -[Iteration 10, Thread 3] Got lock -[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 10, Thread 2] Got lock -[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 10, Thread 1] Got lock -[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 10, Thread 2] Got lock +[Iteration 10, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 10, Thread 3] Got lock +[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3 Iteration 10 completed PASSED :-) -Exiting @ tick 117496500 because target called exit() +Exiting @ tick 117445500 because target called exit() diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index acba85fd7..60b4e57e2 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,1602 +1,1602 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 67069 # Simulator instruction rate (inst/s) -host_mem_usage 234672 # Number of bytes of host memory used -host_seconds 17.20 # Real time elapsed on the host -host_tick_rate 6832636 # Simulator tick rate (ticks/s) +host_inst_rate 134273 # Simulator instruction rate (inst/s) +host_mem_usage 216692 # Number of bytes of host memory used +host_seconds 8.59 # Real time elapsed on the host +host_tick_rate 13675054 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1153323 # Number of instructions simulated +sim_insts 1153138 # Number of instructions simulated sim_seconds 0.000117 # Number of seconds simulated -sim_ticks 117496500 # Number of ticks simulated +sim_ticks 117445500 # Number of ticks simulated system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.BTBHits 89278 # Number of BTB hits -system.cpu0.BPredUnit.BTBLookups 91911 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 89261 # Number of BTB hits +system.cpu0.BPredUnit.BTBLookups 91887 # Number of BTB lookups system.cpu0.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu0.BPredUnit.condIncorrect 1075 # Number of conditional branches incorrect -system.cpu0.BPredUnit.condPredicted 92364 # Number of conditional branches predicted -system.cpu0.BPredUnit.lookups 92364 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 92336 # Number of conditional branches predicted +system.cpu0.BPredUnit.lookups 92336 # Number of BP lookups system.cpu0.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu0.commit.COM:branches 89553 # Number of branches committed -system.cpu0.commit.COM:bw_lim_events 219 # number cycles where commit BW limit reached +system.cpu0.commit.COM:branches 89544 # Number of branches committed +system.cpu0.commit.COM:bw_lim_events 223 # number cycles where commit BW limit reached system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.commit.COM:committed_per_cycle::samples 214839 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::mean 2.488128 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::stdev 2.121442 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::samples 214748 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::mean 2.488931 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::stdev 2.121519 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::0 33722 15.70% 15.70% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::1 90658 42.20% 57.89% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::2 2488 1.16% 59.05% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::3 738 0.34% 59.40% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::4 743 0.35% 59.74% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::5 85727 39.90% 99.64% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::6 468 0.22% 99.86% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::0 33657 15.67% 15.67% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::1 90653 42.21% 57.89% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::2 2478 1.15% 59.04% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::3 734 0.34% 59.38% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::4 738 0.34% 59.73% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::5 85720 39.92% 99.64% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::6 469 0.22% 99.86% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::7 76 0.04% 99.90% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::8 219 0.10% 100.00% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::8 223 0.10% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::total 214839 # Number of insts commited each cycle -system.cpu0.commit.COM:count 534547 # Number of instructions committed +system.cpu0.commit.COM:committed_per_cycle::total 214748 # Number of insts commited each cycle +system.cpu0.commit.COM:count 534493 # Number of instructions committed system.cpu0.commit.COM:fp_insts 0 # Number of committed floating point instructions. system.cpu0.commit.COM:function_calls 0 # Number of function calls committed. -system.cpu0.commit.COM:int_insts 359798 # Number of committed integer instructions. -system.cpu0.commit.COM:loads 174318 # Number of loads committed +system.cpu0.commit.COM:int_insts 359762 # Number of committed integer instructions. +system.cpu0.commit.COM:loads 174300 # Number of loads committed system.cpu0.commit.COM:membars 84 # Number of memory barriers committed -system.cpu0.commit.COM:refs 261983 # Number of memory references committed +system.cpu0.commit.COM:refs 261956 # Number of memory references committed system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu0.commit.branchMispredicts 1075 # The number of times a branch was mispredicted -system.cpu0.commit.commitCommittedInsts 534547 # The number of committed instructions +system.cpu0.commit.commitCommittedInsts 534493 # The number of committed instructions system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.commitSquashedInsts 9542 # The number of squashed insts skipped by commit -system.cpu0.committedInsts 448179 # Number of Instructions Simulated -system.cpu0.committedInsts_total 448179 # Number of Instructions Simulated -system.cpu0.cpi 0.524331 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.524331 # CPI: Total CPI of All Threads -system.cpu0.dcache.ReadReq_accesses 89513 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency 27025.458248 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 27734.972678 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_hits 89022 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 13269500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate 0.005485 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 491 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_hits 308 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_miss_latency 5075500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002044 # mshr miss rate for ReadReq accesses +system.cpu0.commit.commitSquashedInsts 9438 # The number of squashed insts skipped by commit +system.cpu0.committedInsts 448134 # Number of Instructions Simulated +system.cpu0.committedInsts_total 448134 # Number of Instructions Simulated +system.cpu0.cpi 0.524156 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.524156 # CPI: Total CPI of All Threads +system.cpu0.dcache.ReadReq_accesses 89494 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency 27082.653061 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 27751.366120 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_hits 89004 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 13270500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate 0.005475 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 490 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_hits 307 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_miss_latency 5078500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002045 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_misses 183 # number of ReadReq MSHR misses system.cpu0.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_avg_miss_latency 16807.692308 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 13807.692308 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency 16923.076923 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 13923.076923 # average SwapReq mshr miss latency system.cpu0.dcache.SwapReq_hits 16 # number of SwapReq hits -system.cpu0.dcache.SwapReq_miss_latency 437000 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency 440000 # number of SwapReq miss cycles system.cpu0.dcache.SwapReq_miss_rate 0.619048 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_misses 26 # number of SwapReq misses -system.cpu0.dcache.SwapReq_mshr_miss_latency 359000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency 362000 # number of SwapReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_rate 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_misses 26 # number of SwapReq MSHR misses -system.cpu0.dcache.WriteReq_accesses 87623 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency 46095.340741 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 36862.857143 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_hits 87083 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 24891484 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_accesses 87614 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency 46112.007407 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 37114.942529 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_hits 87074 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 24900484 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_rate 0.006163 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_misses 540 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_hits 365 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_miss_latency 6451000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate 0.001997 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 175 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_hits 366 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_miss_latency 6458000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.001986 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_misses 174 # number of WriteReq MSHR misses system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8595.238095 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 607.620690 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 608.017241 # Average number of references to valid blocks. system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_mshrs 180500 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 177136 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency 37013.563531 # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 32196.927374 # average overall mshr miss latency -system.cpu0.dcache.demand_hits 176105 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 38160984 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.005820 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 1031 # number of demand (read+write) misses +system.cpu0.dcache.demand_accesses 177108 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 37059.207767 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 32315.126050 # average overall mshr miss latency +system.cpu0.dcache.demand_hits 176078 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 38170984 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.005816 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 1030 # number of demand (read+write) misses system.cpu0.dcache.demand_mshr_hits 673 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 11526500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate 0.002021 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 358 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_miss_latency 11536500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0.002016 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 357 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.occ_%::0 0.275951 # Average percentage of cache occupancy -system.cpu0.dcache.occ_%::1 -0.002548 # Average percentage of cache occupancy -system.cpu0.dcache.occ_blocks::0 141.286787 # Average occupied blocks per context -system.cpu0.dcache.occ_blocks::1 -1.304354 # Average occupied blocks per context -system.cpu0.dcache.overall_accesses 177136 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency 37013.563531 # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 32196.927374 # average overall mshr miss latency +system.cpu0.dcache.occ_%::0 0.275966 # Average percentage of cache occupancy +system.cpu0.dcache.occ_%::1 -0.002190 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::0 141.294426 # Average occupied blocks per context +system.cpu0.dcache.occ_blocks::1 -1.121239 # Average occupied blocks per context +system.cpu0.dcache.overall_accesses 177108 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 37059.207767 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 32315.126050 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 176105 # number of overall hits -system.cpu0.dcache.overall_miss_latency 38160984 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.005820 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 1031 # number of overall misses +system.cpu0.dcache.overall_hits 176078 # number of overall hits +system.cpu0.dcache.overall_miss_latency 38170984 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.005816 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 1030 # number of overall misses system.cpu0.dcache.overall_mshr_hits 673 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 11526500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate 0.002021 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 358 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_miss_latency 11536500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0.002016 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 357 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.dcache.replacements 9 # number of replacements system.cpu0.dcache.sampled_refs 174 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 139.982434 # Cycle average of tags in use -system.cpu0.dcache.total_refs 105726 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 140.173187 # Cycle average of tags in use +system.cpu0.dcache.total_refs 105795 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.dcache.writebacks 6 # number of writebacks -system.cpu0.decode.DECODE:BlockedCycles 13489 # Number of cycles decode is blocked -system.cpu0.decode.DECODE:DecodedInsts 549068 # Number of instructions handled by decode -system.cpu0.decode.DECODE:IdleCycles 20046 # Number of cycles decode is idle -system.cpu0.decode.DECODE:RunCycles 181085 # Number of cycles decode is running -system.cpu0.decode.DECODE:SquashCycles 2062 # Number of cycles decode is squashing -system.cpu0.decode.DECODE:UnblockCycles 202 # Number of cycles decode is unblocking -system.cpu0.fetch.Branches 92364 # Number of branches that fetch encountered -system.cpu0.fetch.CacheLines 5264 # Number of cache lines fetched -system.cpu0.fetch.Cycles 181529 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.IcacheSquashes 482 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.Insts 550067 # Number of instructions fetch has processed +system.cpu0.decode.DECODE:BlockedCycles 13474 # Number of cycles decode is blocked +system.cpu0.decode.DECODE:DecodedInsts 548904 # Number of instructions handled by decode +system.cpu0.decode.DECODE:IdleCycles 20013 # Number of cycles decode is idle +system.cpu0.decode.DECODE:RunCycles 181043 # Number of cycles decode is running +system.cpu0.decode.DECODE:SquashCycles 2044 # Number of cycles decode is squashing +system.cpu0.decode.DECODE:UnblockCycles 201 # Number of cycles decode is unblocking +system.cpu0.fetch.Branches 92336 # Number of branches that fetch encountered +system.cpu0.fetch.CacheLines 5242 # Number of cache lines fetched +system.cpu0.fetch.Cycles 181487 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.IcacheSquashes 476 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.Insts 549904 # Number of instructions fetch has processed system.cpu0.fetch.MiscStallCycles 41 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.SquashCycles 1232 # Number of cycles fetch has spent squashing -system.cpu0.fetch.branchRate 0.393048 # Number of branch fetches per cycle -system.cpu0.fetch.icacheStallCycles 5264 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.predictedBranches 89278 # Number of branches that fetch has predicted taken -system.cpu0.fetch.rate 2.340770 # Number of inst fetches per cycle -system.cpu0.fetch.rateDist::samples 216884 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.536227 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.186778 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.SquashCycles 1222 # Number of cycles fetch has spent squashing +system.cpu0.fetch.branchRate 0.393100 # Number of branch fetches per cycle +system.cpu0.fetch.icacheStallCycles 5242 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.predictedBranches 89261 # Number of branches that fetch has predicted taken +system.cpu0.fetch.rate 2.341093 # Number of inst fetches per cycle +system.cpu0.fetch.rateDist::samples 216775 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.536750 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.186468 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 35355 16.30% 16.30% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 90192 41.59% 57.89% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 488 0.23% 58.11% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 808 0.37% 58.48% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 588 0.27% 58.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 86546 39.90% 98.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 826 0.38% 99.04% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 211 0.10% 99.14% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 1870 0.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 35288 16.28% 16.28% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 90175 41.60% 57.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 487 0.22% 58.10% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 807 0.37% 58.47% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 586 0.27% 58.74% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 86536 39.92% 98.66% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 826 0.38% 99.05% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 206 0.10% 99.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 1864 0.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 216884 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::total 216775 # Number of instructions fetched each cycle (Total) system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.icache.ReadReq_accesses 5264 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency 39056.216931 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 37012.315271 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits 4508 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 29526500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate 0.143617 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses 756 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_hits 147 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_miss_latency 22540500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate 0.115691 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_accesses 5242 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency 39013.262599 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 36995.894910 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits 4488 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 29416000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate 0.143838 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 754 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_hits 145 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_miss_latency 22530500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate 0.116177 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_misses 609 # number of ReadReq MSHR misses system.cpu0.icache.avg_blocked_cycles::no_mshrs 11000 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 7.414474 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 7.381579 # Average number of references to valid blocks. system.cpu0.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_mshrs 22000 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 5264 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency 39056.216931 # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 37012.315271 # average overall mshr miss latency -system.cpu0.icache.demand_hits 4508 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 29526500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate 0.143617 # miss rate for demand accesses -system.cpu0.icache.demand_misses 756 # number of demand (read+write) misses -system.cpu0.icache.demand_mshr_hits 147 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 22540500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate 0.115691 # mshr miss rate for demand accesses +system.cpu0.icache.demand_accesses 5242 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 39013.262599 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 36995.894910 # average overall mshr miss latency +system.cpu0.icache.demand_hits 4488 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 29416000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.143838 # miss rate for demand accesses +system.cpu0.icache.demand_misses 754 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 145 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 22530500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0.116177 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_misses 609 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.occ_%::0 0.502840 # Average percentage of cache occupancy -system.cpu0.icache.occ_blocks::0 257.454218 # Average occupied blocks per context -system.cpu0.icache.overall_accesses 5264 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency 39056.216931 # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 37012.315271 # average overall mshr miss latency +system.cpu0.icache.occ_%::0 0.502878 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::0 257.473705 # Average occupied blocks per context +system.cpu0.icache.overall_accesses 5242 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 39013.262599 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 36995.894910 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 4508 # number of overall hits -system.cpu0.icache.overall_miss_latency 29526500 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate 0.143617 # miss rate for overall accesses -system.cpu0.icache.overall_misses 756 # number of overall misses -system.cpu0.icache.overall_mshr_hits 147 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 22540500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate 0.115691 # mshr miss rate for overall accesses +system.cpu0.icache.overall_hits 4488 # number of overall hits +system.cpu0.icache.overall_miss_latency 29416000 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.143838 # miss rate for overall accesses +system.cpu0.icache.overall_misses 754 # number of overall misses +system.cpu0.icache.overall_mshr_hits 145 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 22530500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0.116177 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_misses 609 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.icache.replacements 307 # number of replacements system.cpu0.icache.sampled_refs 608 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 257.454218 # Cycle average of tags in use -system.cpu0.icache.total_refs 4508 # Total number of references to valid blocks. +system.cpu0.icache.tagsinuse 257.473705 # Cycle average of tags in use +system.cpu0.icache.total_refs 4488 # Total number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idleCycles 18110 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.iew.EXEC:branches 90363 # Number of branches executed -system.cpu0.iew.EXEC:nop 86742 # number of nop insts executed -system.cpu0.iew.EXEC:rate 1.932130 # Inst execution rate -system.cpu0.iew.EXEC:refs 263654 # number of memory reference insts executed -system.cpu0.iew.EXEC:stores 88201 # Number of stores executed +system.cpu0.idleCycles 18117 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.iew.EXEC:branches 90345 # Number of branches executed +system.cpu0.iew.EXEC:nop 86733 # number of nop insts executed +system.cpu0.iew.EXEC:rate 1.932437 # Inst execution rate +system.cpu0.iew.EXEC:refs 263598 # number of memory reference insts executed +system.cpu0.iew.EXEC:stores 88173 # Number of stores executed system.cpu0.iew.EXEC:swp 0 # number of swp insts executed -system.cpu0.iew.WB:consumers 270968 # num instructions consuming a value -system.cpu0.iew.WB:count 453412 # cumulative count of insts written-back -system.cpu0.iew.WB:fanout 0.992922 # average fanout of values written-back +system.cpu0.iew.WB:consumers 270902 # num instructions consuming a value +system.cpu0.iew.WB:count 453315 # cumulative count of insts written-back +system.cpu0.iew.WB:fanout 0.992949 # average fanout of values written-back system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.iew.WB:producers 269050 # num instructions producing a value -system.cpu0.iew.WB:rate 1.929462 # insts written-back per cycle -system.cpu0.iew.WB:sent 453657 # cumulative count of insts sent to commit -system.cpu0.iew.branchMispredicts 1246 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewBlockCycles 822 # Number of cycles IEW is blocking -system.cpu0.iew.iewDispLoadInsts 176000 # Number of dispatched load instructions -system.cpu0.iew.iewDispNonSpecInsts 727 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewDispSquashedInsts 482 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispStoreInsts 88746 # Number of dispatched store instructions -system.cpu0.iew.iewDispatchedInsts 544085 # Number of instructions dispatched to IQ -system.cpu0.iew.iewExecLoadInsts 175453 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 917 # Number of squashed instructions skipped in execute -system.cpu0.iew.iewExecutedInsts 454039 # Number of executed instructions +system.cpu0.iew.WB:producers 268992 # num instructions producing a value +system.cpu0.iew.WB:rate 1.929887 # insts written-back per cycle +system.cpu0.iew.WB:sent 453561 # cumulative count of insts sent to commit +system.cpu0.iew.branchMispredicts 1242 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewBlockCycles 823 # Number of cycles IEW is blocking +system.cpu0.iew.iewDispLoadInsts 175971 # Number of dispatched load instructions +system.cpu0.iew.iewDispNonSpecInsts 722 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewDispSquashedInsts 481 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispStoreInsts 88710 # Number of dispatched store instructions +system.cpu0.iew.iewDispatchedInsts 543927 # Number of instructions dispatched to IQ +system.cpu0.iew.iewExecLoadInsts 175425 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 910 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecutedInsts 453914 # Number of executed instructions system.cpu0.iew.iewIQFullEvents 24 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.iewSquashCycles 2062 # Number of cycles IEW is squashing +system.cpu0.iew.iewSquashCycles 2044 # Number of cycles IEW is squashing system.cpu0.iew.iewUnblockCycles 27 # Number of cycles IEW is unblocking system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread.0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked -system.cpu0.iew.lsq.thread.0.forwLoads 85889 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread.0.forwLoads 85880 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu0.iew.lsq.thread.0.memOrderViolation 74 # Number of memory ordering violations +system.cpu0.iew.lsq.thread.0.memOrderViolation 44 # Number of memory ordering violations system.cpu0.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread.0.squashedLoads 1682 # Number of loads squashed -system.cpu0.iew.lsq.thread.0.squashedStores 1081 # Number of stores squashed -system.cpu0.iew.memOrderViolationEvents 74 # Number of memory order violations -system.cpu0.iew.predictedNotTakenIncorrect 821 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.lsq.thread.0.squashedLoads 1671 # Number of loads squashed +system.cpu0.iew.lsq.thread.0.squashedStores 1054 # Number of stores squashed +system.cpu0.iew.memOrderViolationEvents 44 # Number of memory order violations +system.cpu0.iew.predictedNotTakenIncorrect 817 # Number of branches that were predicted not taken incorrectly system.cpu0.iew.predictedTakenIncorrect 425 # Number of branches that were predicted taken incorrectly -system.cpu0.int_regfile_reads 812944 # number of integer regfile reads -system.cpu0.int_regfile_writes 365773 # number of integer regfile writes -system.cpu0.ipc 1.907193 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.907193 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 812740 # number of integer regfile reads +system.cpu0.int_regfile_writes 365710 # number of integer regfile writes +system.cpu0.ipc 1.907830 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.907830 # IPC: Total IPC of All Threads system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntAlu 190895 41.96% 41.96% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntMult 0 0.00% 41.96% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 41.96% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 41.96% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 41.96% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 41.96% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 41.96% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 41.96% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 41.96% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 41.96% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 41.96% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 41.96% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 41.96% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 41.96% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 41.96% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 41.96% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 41.96% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 41.96% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 41.96% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 41.96% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 41.96% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 41.96% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 41.96% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 41.96% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 41.96% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 41.96% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 41.96% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 41.96% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 41.96% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemRead 175746 38.63% 80.59% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemWrite 88315 19.41% 100.00% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntAlu 190821 41.95% 41.95% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntMult 0 0.00% 41.95% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 41.95% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 41.95% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 41.95% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 41.95% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 41.95% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 41.95% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 41.95% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 41.95% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 41.95% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 41.95% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 41.95% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 41.95% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 41.95% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 41.95% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 41.95% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 41.95% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 41.95% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 41.95% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 41.95% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 41.95% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 41.95% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 41.95% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 41.95% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 41.95% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 41.95% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 41.95% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 41.95% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemRead 175718 38.63% 80.59% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemWrite 88285 19.41% 100.00% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::total 454956 # Type of FU issued -system.cpu0.iq.ISSUE:fu_busy_cnt 227 # FU busy when requested -system.cpu0.iq.ISSUE:fu_busy_rate 0.000499 # FU busy rate (busy events/executed inst) +system.cpu0.iq.ISSUE:FU_type_0::total 454824 # Type of FU issued +system.cpu0.iq.ISSUE:fu_busy_cnt 223 # FU busy when requested +system.cpu0.iq.ISSUE:fu_busy_rate 0.000490 # FU busy rate (busy events/executed inst) system.cpu0.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntAlu 33 14.54% 14.54% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 14.54% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 14.54% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 14.54% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 14.54% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 14.54% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 14.54% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 14.54% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 14.54% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdAdd 0 0.00% 14.54% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 14.54% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdAlu 0 0.00% 14.54% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdCmp 0 0.00% 14.54% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdCvt 0 0.00% 14.54% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdMisc 0 0.00% 14.54% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdMult 0 0.00% 14.54% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 14.54% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdShift 0 0.00% 14.54% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 14.54% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 14.54% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 14.54% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 14.54% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 14.54% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 14.54% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 14.54% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 14.54% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 14.54% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 14.54% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 14.54% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemRead 85 37.44% 51.98% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemWrite 109 48.02% 100.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntAlu 33 14.80% 14.80% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 14.80% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 14.80% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 14.80% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 14.80% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 14.80% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 14.80% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 14.80% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 14.80% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdAdd 0 0.00% 14.80% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 14.80% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdAlu 0 0.00% 14.80% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdCmp 0 0.00% 14.80% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdCvt 0 0.00% 14.80% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdMisc 0 0.00% 14.80% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdMult 0 0.00% 14.80% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 14.80% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdShift 0 0.00% 14.80% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 14.80% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 14.80% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 14.80% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 14.80% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 14.80% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 14.80% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 14.80% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 14.80% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 14.80% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 14.80% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 14.80% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemRead 81 36.32% 51.12% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemWrite 109 48.88% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:issued_per_cycle::samples 216884 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::mean 2.097693 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.057244 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::samples 216775 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::mean 2.098139 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.056899 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::0 33388 15.39% 15.39% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::1 5635 2.60% 17.99% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::2 88185 40.66% 58.65% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::3 87166 40.19% 98.84% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::4 1498 0.69% 99.53% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::5 719 0.33% 99.86% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::6 194 0.09% 99.95% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::0 33322 15.37% 15.37% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::1 5647 2.61% 17.98% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::2 88171 40.67% 58.65% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::3 87126 40.19% 98.84% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::4 1486 0.69% 99.53% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::5 733 0.34% 99.87% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::6 191 0.09% 99.95% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::7 90 0.04% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::8 9 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::total 216884 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:rate 1.936032 # Inst issue rate +system.cpu0.iq.ISSUE:issued_per_cycle::total 216775 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:rate 1.936311 # Inst issue rate system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes -system.cpu0.iq.int_alu_accesses 455183 # Number of integer alu accesses -system.cpu0.iq.int_inst_queue_reads 1127113 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_wakeup_accesses 453412 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.int_inst_queue_writes 465644 # Number of integer instruction queue writes -system.cpu0.iq.iqInstsAdded 456518 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqInstsIssued 454956 # Number of instructions issued -system.cpu0.iq.iqNonSpecInstsAdded 825 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqSquashedInstsExamined 8243 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.int_alu_accesses 455047 # Number of integer alu accesses +system.cpu0.iq.int_inst_queue_reads 1126736 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_wakeup_accesses 453315 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.int_inst_queue_writes 465372 # Number of integer instruction queue writes +system.cpu0.iq.iqInstsAdded 456374 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqInstsIssued 454824 # Number of instructions issued +system.cpu0.iq.iqNonSpecInstsAdded 820 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqSquashedInstsExamined 8136 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu0.iq.iqSquashedInstsIssued 90 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedNonSpecRemoved 266 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.iqSquashedOperandsExamined 6865 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.memDep0.conflictingLoads 86252 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 86102 # Number of conflicting stores. -system.cpu0.memDep0.insertedLoads 176000 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 88746 # Number of stores inserted to the mem dependence unit. -system.cpu0.misc_regfile_reads 265411 # number of misc regfile reads +system.cpu0.iq.iqSquashedNonSpecRemoved 261 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.iqSquashedOperandsExamined 6774 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.memDep0.conflictingLoads 86214 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 86089 # Number of conflicting stores. +system.cpu0.memDep0.insertedLoads 175971 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 88710 # Number of stores inserted to the mem dependence unit. +system.cpu0.misc_regfile_reads 265353 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.numCycles 234994 # number of cpu cycles simulated +system.cpu0.numCycles 234892 # number of cpu cycles simulated system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.rename.RENAME:BlockCycles 1211 # Number of cycles rename is blocking -system.cpu0.rename.RENAME:CommittedMaps 361468 # Number of HB maps that are committed +system.cpu0.rename.RENAME:BlockCycles 1209 # Number of cycles rename is blocking +system.cpu0.rename.RENAME:CommittedMaps 361432 # Number of HB maps that are committed system.cpu0.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu0.rename.RENAME:IdleCycles 20733 # Number of cycles rename is idle -system.cpu0.rename.RENAME:LSQFullEvents 291 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RENAME:RenameLookups 1089130 # Number of register rename lookups that rename has made -system.cpu0.rename.RENAME:RenamedInsts 545907 # Number of instructions processed by rename -system.cpu0.rename.RENAME:RenamedOperands 371790 # Number of destination operands rename has renamed -system.cpu0.rename.RENAME:RunCycles 180641 # Number of cycles rename is running -system.cpu0.rename.RENAME:SquashCycles 2062 # Number of cycles rename is squashing +system.cpu0.rename.RENAME:IdleCycles 20699 # Number of cycles rename is idle +system.cpu0.rename.RENAME:LSQFullEvents 289 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RENAME:RenameLookups 1088795 # Number of register rename lookups that rename has made +system.cpu0.rename.RENAME:RenamedInsts 545750 # Number of instructions processed by rename +system.cpu0.rename.RENAME:RenamedOperands 371672 # Number of destination operands rename has renamed +system.cpu0.rename.RENAME:RunCycles 180600 # Number of cycles rename is running +system.cpu0.rename.RENAME:SquashCycles 2044 # Number of cycles rename is squashing system.cpu0.rename.RENAME:UnblockCycles 697 # Number of cycles rename is unblocking -system.cpu0.rename.RENAME:UndoneMaps 10322 # Number of HB maps that are undone due to squashing -system.cpu0.rename.RENAME:int_rename_lookups 1089130 # Number of integer rename lookups -system.cpu0.rename.RENAME:serializeStallCycles 11540 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RENAME:serializingInsts 809 # count of serializing insts renamed -system.cpu0.rename.RENAME:skidInsts 4202 # count of insts added to the skid buffer -system.cpu0.rename.RENAME:tempSerializingInsts 812 # count of temporary serializing insts renamed -system.cpu0.rob.rob_reads 757548 # The number of ROB reads -system.cpu0.rob.rob_writes 1090250 # The number of ROB writes -system.cpu0.timesIdled 337 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.rename.RENAME:UndoneMaps 10240 # Number of HB maps that are undone due to squashing +system.cpu0.rename.RENAME:int_rename_lookups 1088795 # Number of integer rename lookups +system.cpu0.rename.RENAME:serializeStallCycles 11526 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RENAME:serializingInsts 803 # count of serializing insts renamed +system.cpu0.rename.RENAME:skidInsts 4179 # count of insts added to the skid buffer +system.cpu0.rename.RENAME:tempSerializingInsts 807 # count of temporary serializing insts renamed +system.cpu0.rob.rob_reads 757295 # The number of ROB reads +system.cpu0.rob.rob_writes 1089916 # The number of ROB writes +system.cpu0.timesIdled 338 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu0.workload.PROG:num_syscalls 89 # Number of system calls system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.BTBHits 41740 # Number of BTB hits -system.cpu1.BPredUnit.BTBLookups 43967 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 53298 # Number of BTB hits +system.cpu1.BPredUnit.BTBLookups 55521 # Number of BTB lookups system.cpu1.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu1.BPredUnit.condIncorrect 1106 # Number of conditional branches incorrect -system.cpu1.BPredUnit.condPredicted 44023 # Number of conditional branches predicted -system.cpu1.BPredUnit.lookups 44023 # Number of BP lookups +system.cpu1.BPredUnit.condIncorrect 1087 # Number of conditional branches incorrect +system.cpu1.BPredUnit.condPredicted 55616 # Number of conditional branches predicted +system.cpu1.BPredUnit.lookups 55616 # Number of BP lookups system.cpu1.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu1.commit.COM:branches 41195 # Number of branches committed -system.cpu1.commit.COM:bw_lim_events 485 # number cycles where commit BW limit reached +system.cpu1.commit.COM:branches 52878 # Number of branches committed +system.cpu1.commit.COM:bw_lim_events 488 # number cycles where commit BW limit reached system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.commit.COM:committed_per_cycle::samples 187667 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::mean 1.179936 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::stdev 1.750960 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::samples 188159 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::mean 1.583331 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::stdev 1.956493 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::0 100980 53.81% 53.81% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::1 41996 22.38% 76.19% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::2 7478 3.98% 80.17% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::3 10619 5.66% 85.83% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::4 2461 1.31% 87.14% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::5 23116 12.32% 99.46% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::6 402 0.21% 99.67% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::7 130 0.07% 99.74% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::8 485 0.26% 100.00% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::0 78134 41.53% 41.53% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::1 53655 28.52% 70.04% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::2 7488 3.98% 74.02% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::3 7425 3.95% 77.97% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::4 2454 1.30% 79.27% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::5 37926 20.16% 99.43% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::6 461 0.25% 99.67% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::7 128 0.07% 99.74% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::8 488 0.26% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::total 187667 # Number of insts commited each cycle -system.cpu1.commit.COM:count 221435 # Number of instructions committed +system.cpu1.commit.COM:committed_per_cycle::total 188159 # Number of insts commited each cycle +system.cpu1.commit.COM:count 297918 # Number of instructions committed system.cpu1.commit.COM:fp_insts 0 # Number of committed floating point instructions. system.cpu1.commit.COM:function_calls 0 # Number of function calls committed. -system.cpu1.commit.COM:int_insts 150322 # Number of committed integer instructions. -system.cpu1.commit.COM:loads 60856 # Number of loads committed -system.cpu1.commit.COM:membars 9088 # Number of memory barriers committed -system.cpu1.commit.COM:refs 87006 # Number of memory references committed +system.cpu1.commit.COM:int_insts 203433 # Number of committed integer instructions. +system.cpu1.commit.COM:loads 87419 # Number of loads committed +system.cpu1.commit.COM:membars 5903 # Number of memory barriers committed +system.cpu1.commit.COM:refs 128431 # Number of memory references committed system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.branchMispredicts 1106 # The number of times a branch was mispredicted -system.cpu1.commit.commitCommittedInsts 221435 # The number of committed instructions -system.cpu1.commit.commitNonSpecStalls 9806 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.commitSquashedInsts 8244 # The number of squashed insts skipped by commit -system.cpu1.committedInsts 180366 # Number of Instructions Simulated -system.cpu1.committedInsts_total 180366 # Number of Instructions Simulated -system.cpu1.cpi 1.108479 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.108479 # CPI: Total CPI of All Threads -system.cpu1.dcache.ReadReq_accesses 39263 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency 22504.819277 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 14511.904762 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_hits 38848 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 9339500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate 0.010570 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses 415 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_hits 247 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_miss_latency 2438000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate 0.004279 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 168 # number of ReadReq MSHR misses -system.cpu1.dcache.SwapReq_accesses 72 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_avg_miss_latency 25946.428571 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 22946.428571 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_hits 16 # number of SwapReq hits -system.cpu1.dcache.SwapReq_miss_latency 1453000 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_rate 0.777778 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_misses 56 # number of SwapReq misses -system.cpu1.dcache.SwapReq_mshr_miss_latency 1285000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_rate 0.777778 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_misses 56 # number of SwapReq MSHR misses -system.cpu1.dcache.WriteReq_accesses 26078 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency 24129.166667 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 15810 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_hits 25958 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 2895500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate 0.004602 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses 120 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_hits 20 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_miss_latency 1581000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate 0.003835 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 100 # number of WriteReq MSHR misses +system.cpu1.commit.branchMispredicts 1087 # The number of times a branch was mispredicted +system.cpu1.commit.commitCommittedInsts 297918 # The number of committed instructions +system.cpu1.commit.commitNonSpecStalls 6615 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.commitSquashedInsts 8048 # The number of squashed insts skipped by commit +system.cpu1.committedInsts 248345 # Number of Instructions Simulated +system.cpu1.committedInsts_total 248345 # Number of Instructions Simulated +system.cpu1.cpi 0.804816 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.804816 # CPI: Total CPI of All Threads +system.cpu1.dcache.ReadReq_accesses 51009 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency 20896.247241 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13877.358491 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_hits 50556 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 9466000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate 0.008881 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 453 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_hits 294 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_miss_latency 2206500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate 0.003117 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_misses 159 # number of ReadReq MSHR misses +system.cpu1.dcache.SwapReq_accesses 66 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_avg_miss_latency 25933.962264 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 22933.962264 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_hits 13 # number of SwapReq hits +system.cpu1.dcache.SwapReq_miss_latency 1374500 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_rate 0.803030 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_misses 53 # number of SwapReq misses +system.cpu1.dcache.SwapReq_mshr_miss_latency 1215500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_rate 0.803030 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_misses 53 # number of SwapReq MSHR misses +system.cpu1.dcache.WriteReq_accesses 40946 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency 23975.806452 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 15514.150943 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_hits 40822 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 2973000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate 0.003028 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 124 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_miss_latency 1644500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.002589 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_misses 106 # number of WriteReq MSHR misses system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 1063.866667 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 1612.206897 # Average number of references to valid blocks. system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses 65341 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency 22869.158879 # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 14996.268657 # average overall mshr miss latency -system.cpu1.dcache.demand_hits 64806 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 12235000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.008188 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 535 # number of demand (read+write) misses -system.cpu1.dcache.demand_mshr_hits 267 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 4019000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate 0.004102 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 268 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_accesses 91955 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 21558.058925 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 14532.075472 # average overall mshr miss latency +system.cpu1.dcache.demand_hits 91378 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 12439000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.006275 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 577 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 312 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 3851000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0.002882 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 265 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_%::0 0.047224 # Average percentage of cache occupancy -system.cpu1.dcache.occ_%::1 -0.015258 # Average percentage of cache occupancy -system.cpu1.dcache.occ_blocks::0 24.178499 # Average occupied blocks per context -system.cpu1.dcache.occ_blocks::1 -7.812139 # Average occupied blocks per context -system.cpu1.dcache.overall_accesses 65341 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency 22869.158879 # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 14996.268657 # average overall mshr miss latency +system.cpu1.dcache.occ_%::0 0.048953 # Average percentage of cache occupancy +system.cpu1.dcache.occ_%::1 -0.017597 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 25.063911 # Average occupied blocks per context +system.cpu1.dcache.occ_blocks::1 -9.009839 # Average occupied blocks per context +system.cpu1.dcache.overall_accesses 91955 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 21558.058925 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 14532.075472 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 64806 # number of overall hits -system.cpu1.dcache.overall_miss_latency 12235000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.008188 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 535 # number of overall misses -system.cpu1.dcache.overall_mshr_hits 267 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 4019000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate 0.004102 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 268 # number of overall MSHR misses +system.cpu1.dcache.overall_hits 91378 # number of overall hits +system.cpu1.dcache.overall_miss_latency 12439000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.006275 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 577 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 312 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 3851000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0.002882 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 265 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu1.dcache.replacements 2 # number of replacements -system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu1.dcache.sampled_refs 29 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 16.366360 # Cycle average of tags in use -system.cpu1.dcache.total_refs 31916 # Total number of references to valid blocks. +system.cpu1.dcache.tagsinuse 16.054072 # Cycle average of tags in use +system.cpu1.dcache.total_refs 46754 # Total number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.dcache.writebacks 1 # number of writebacks -system.cpu1.decode.DECODE:BlockedCycles 23978 # Number of cycles decode is blocked -system.cpu1.decode.DECODE:DecodedInsts 233739 # Number of instructions handled by decode -system.cpu1.decode.DECODE:IdleCycles 70922 # Number of cycles decode is idle -system.cpu1.decode.DECODE:RunCycles 84431 # Number of cycles decode is running -system.cpu1.decode.DECODE:SquashCycles 1784 # Number of cycles decode is squashing -system.cpu1.decode.DECODE:UnblockCycles 8335 # Number of cycles decode is unblocking -system.cpu1.fetch.Branches 44023 # Number of branches that fetch encountered -system.cpu1.fetch.CacheLines 27242 # Number of cache lines fetched -system.cpu1.fetch.Cycles 93139 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.IcacheSquashes 219 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.Insts 234880 # Number of instructions fetch has processed -system.cpu1.fetch.MiscStallCycles 23 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.SquashCycles 1183 # Number of cycles fetch has spent squashing -system.cpu1.fetch.branchRate 0.220190 # Number of branch fetches per cycle -system.cpu1.fetch.icacheStallCycles 27242 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.predictedBranches 41740 # Number of branches that fetch has predicted taken -system.cpu1.fetch.rate 1.174799 # Number of inst fetches per cycle -system.cpu1.fetch.rateDist::samples 196087 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.197836 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.836209 # Number of instructions fetched each cycle (Total) +system.cpu1.decode.DECODE:BlockedCycles 20803 # Number of cycles decode is blocked +system.cpu1.decode.DECODE:DecodedInsts 309923 # Number of instructions handled by decode +system.cpu1.decode.DECODE:IdleCycles 54694 # Number of cycles decode is idle +system.cpu1.decode.DECODE:RunCycles 107191 # Number of cycles decode is running +system.cpu1.decode.DECODE:SquashCycles 1741 # Number of cycles decode is squashing +system.cpu1.decode.DECODE:UnblockCycles 5470 # Number of cycles decode is unblocking +system.cpu1.fetch.Branches 55616 # Number of branches that fetch encountered +system.cpu1.fetch.CacheLines 20621 # Number of cache lines fetched +system.cpu1.fetch.Cycles 113033 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.IcacheSquashes 217 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.Insts 311054 # Number of instructions fetch has processed +system.cpu1.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.SquashCycles 1161 # Number of cycles fetch has spent squashing +system.cpu1.fetch.branchRate 0.278258 # Number of branch fetches per cycle +system.cpu1.fetch.icacheStallCycles 20621 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.predictedBranches 53298 # Number of branches that fetch has predicted taken +system.cpu1.fetch.rate 1.556266 # Number of inst fetches per cycle +system.cpu1.fetch.rateDist::samples 196498 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.582988 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.040174 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 102948 52.50% 52.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 49979 25.49% 77.99% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 10332 5.27% 83.26% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2701 1.38% 84.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1922 0.98% 85.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 23991 12.23% 97.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2480 1.26% 99.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 261 0.13% 99.25% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1473 0.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 83465 42.48% 42.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 58273 29.66% 72.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 7057 3.59% 75.72% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 2697 1.37% 77.10% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1913 0.97% 78.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 38892 19.79% 97.86% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2445 1.24% 99.11% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 254 0.13% 99.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1502 0.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 196087 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::total 196498 # Number of instructions fetched each cycle (Total) system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.icache.ReadReq_accesses 27242 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency 15144.329897 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12327.702703 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits 26757 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 7345000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate 0.017803 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses 485 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_hits 41 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_miss_latency 5473500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate 0.016298 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 444 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_accesses 20621 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency 15456.066946 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12612.500000 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits 20143 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 7388000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate 0.023180 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 478 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_hits 38 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_miss_latency 5549500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate 0.021337 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_misses 440 # number of ReadReq MSHR misses system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 60.263514 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 45.779545 # Average number of references to valid blocks. system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses 27242 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency 15144.329897 # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 12327.702703 # average overall mshr miss latency -system.cpu1.icache.demand_hits 26757 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 7345000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate 0.017803 # miss rate for demand accesses -system.cpu1.icache.demand_misses 485 # number of demand (read+write) misses -system.cpu1.icache.demand_mshr_hits 41 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 5473500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate 0.016298 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 444 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_accesses 20621 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 15456.066946 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 12612.500000 # average overall mshr miss latency +system.cpu1.icache.demand_hits 20143 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 7388000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.023180 # miss rate for demand accesses +system.cpu1.icache.demand_misses 478 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 38 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 5549500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0.021337 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 440 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.occ_%::0 0.166395 # Average percentage of cache occupancy -system.cpu1.icache.occ_blocks::0 85.194355 # Average occupied blocks per context -system.cpu1.icache.overall_accesses 27242 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency 15144.329897 # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 12327.702703 # average overall mshr miss latency +system.cpu1.icache.occ_%::0 0.172715 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 88.430285 # Average occupied blocks per context +system.cpu1.icache.overall_accesses 20621 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 15456.066946 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 12612.500000 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits 26757 # number of overall hits -system.cpu1.icache.overall_miss_latency 7345000 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate 0.017803 # miss rate for overall accesses -system.cpu1.icache.overall_misses 485 # number of overall misses -system.cpu1.icache.overall_mshr_hits 41 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 5473500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate 0.016298 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 444 # number of overall MSHR misses +system.cpu1.icache.overall_hits 20143 # number of overall hits +system.cpu1.icache.overall_miss_latency 7388000 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.023180 # miss rate for overall accesses +system.cpu1.icache.overall_misses 478 # number of overall misses +system.cpu1.icache.overall_mshr_hits 38 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 5549500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0.021337 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 440 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.replacements 332 # number of replacements -system.cpu1.icache.sampled_refs 444 # Sample count of references to valid blocks. +system.cpu1.icache.replacements 328 # number of replacements +system.cpu1.icache.sampled_refs 440 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 85.194355 # Cycle average of tags in use -system.cpu1.icache.total_refs 26757 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 88.430285 # Cycle average of tags in use +system.cpu1.icache.total_refs 20143 # Total number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.idleCycles 3845 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.iew.EXEC:branches 41746 # Number of branches executed -system.cpu1.iew.EXEC:nop 32789 # number of nop insts executed -system.cpu1.iew.EXEC:rate 0.965868 # Inst execution rate -system.cpu1.iew.EXEC:refs 88018 # number of memory reference insts executed -system.cpu1.iew.EXEC:stores 26481 # Number of stores executed +system.cpu1.idleCycles 3374 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.iew.EXEC:branches 53426 # Number of branches executed +system.cpu1.iew.EXEC:nop 44397 # number of nop insts executed +system.cpu1.iew.EXEC:rate 1.290846 # Inst execution rate +system.cpu1.iew.EXEC:refs 129529 # number of memory reference insts executed +system.cpu1.iew.EXEC:stores 41363 # Number of stores executed system.cpu1.iew.EXEC:swp 0 # number of swp insts executed -system.cpu1.iew.WB:consumers 108078 # num instructions consuming a value -system.cpu1.iew.WB:count 192754 # cumulative count of insts written-back -system.cpu1.iew.WB:fanout 0.966228 # average fanout of values written-back +system.cpu1.iew.WB:consumers 149591 # num instructions consuming a value +system.cpu1.iew.WB:count 257643 # cumulative count of insts written-back +system.cpu1.iew.WB:fanout 0.975567 # average fanout of values written-back system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.iew.WB:producers 104428 # num instructions producing a value -system.cpu1.iew.WB:rate 0.964098 # insts written-back per cycle -system.cpu1.iew.WB:sent 192883 # cumulative count of insts sent to commit -system.cpu1.iew.branchMispredicts 1199 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewBlockCycles 1512 # Number of cycles IEW is blocking -system.cpu1.iew.iewDispLoadInsts 62331 # Number of dispatched load instructions -system.cpu1.iew.iewDispNonSpecInsts 947 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewDispSquashedInsts 594 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispStoreInsts 26882 # Number of dispatched store instructions -system.cpu1.iew.iewDispatchedInsts 229712 # Number of instructions dispatched to IQ -system.cpu1.iew.iewExecLoadInsts 61537 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 953 # Number of squashed instructions skipped in execute -system.cpu1.iew.iewExecutedInsts 193108 # Number of executed instructions -system.cpu1.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.WB:producers 145936 # num instructions producing a value +system.cpu1.iew.WB:rate 1.289040 # insts written-back per cycle +system.cpu1.iew.WB:sent 257774 # cumulative count of insts sent to commit +system.cpu1.iew.branchMispredicts 1186 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewBlockCycles 1504 # Number of cycles IEW is blocking +system.cpu1.iew.iewDispLoadInsts 88859 # Number of dispatched load instructions +system.cpu1.iew.iewDispNonSpecInsts 932 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewDispSquashedInsts 535 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispStoreInsts 41782 # Number of dispatched store instructions +system.cpu1.iew.iewDispatchedInsts 305999 # Number of instructions dispatched to IQ +system.cpu1.iew.iewExecLoadInsts 88166 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 964 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewExecutedInsts 258004 # Number of executed instructions +system.cpu1.iew.iewIQFullEvents 47 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.iewSquashCycles 1784 # Number of cycles IEW is squashing -system.cpu1.iew.iewUnblockCycles 44 # Number of cycles IEW is unblocking +system.cpu1.iew.iewSquashCycles 1741 # Number of cycles IEW is squashing +system.cpu1.iew.iewUnblockCycles 54 # Number of cycles IEW is unblocking system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu1.iew.lsq.thread.0.forwLoads 22259 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread.0.forwLoads 37142 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu1.iew.lsq.thread.0.memOrderViolation 35 # Number of memory ordering violations +system.cpu1.iew.lsq.thread.0.memOrderViolation 29 # Number of memory ordering violations system.cpu1.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread.0.squashedLoads 1475 # Number of loads squashed -system.cpu1.iew.lsq.thread.0.squashedStores 732 # Number of stores squashed -system.cpu1.iew.memOrderViolationEvents 35 # Number of memory order violations -system.cpu1.iew.predictedNotTakenIncorrect 189 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.predictedTakenIncorrect 1010 # Number of branches that were predicted taken incorrectly -system.cpu1.int_regfile_reads 321648 # number of integer regfile reads -system.cpu1.int_regfile_writes 150288 # number of integer regfile writes -system.cpu1.ipc 0.902137 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.902137 # IPC: Total IPC of All Threads +system.cpu1.iew.lsq.thread.0.squashedLoads 1440 # Number of loads squashed +system.cpu1.iew.lsq.thread.0.squashedStores 770 # Number of stores squashed +system.cpu1.iew.memOrderViolationEvents 29 # Number of memory order violations +system.cpu1.iew.predictedNotTakenIncorrect 196 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.predictedTakenIncorrect 990 # Number of branches that were predicted taken incorrectly +system.cpu1.int_regfile_reads 446126 # number of integer regfile reads +system.cpu1.int_regfile_writes 206677 # number of integer regfile writes +system.cpu1.ipc 1.242520 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.242520 # IPC: Total IPC of All Threads system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntAlu 96746 49.85% 49.85% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntMult 0 0.00% 49.85% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 49.85% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 49.85% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 49.85% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 49.85% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 49.85% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 49.85% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 49.85% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 49.85% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 49.85% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 49.85% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 49.85% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 49.85% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 49.85% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 49.85% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 49.85% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 49.85% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 49.85% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 49.85% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 49.85% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 49.85% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 49.85% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 49.85% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 49.85% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 49.85% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 49.85% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 49.85% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 49.85% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemRead 70805 36.49% 86.34% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemWrite 26510 13.66% 100.00% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntAlu 123325 47.62% 47.62% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntMult 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 47.62% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemRead 94249 36.39% 84.02% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemWrite 41394 15.98% 100.00% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::total 194061 # Type of FU issued -system.cpu1.iq.ISSUE:fu_busy_cnt 185 # FU busy when requested -system.cpu1.iq.ISSUE:fu_busy_rate 0.000953 # FU busy rate (busy events/executed inst) +system.cpu1.iq.ISSUE:FU_type_0::total 258968 # Type of FU issued +system.cpu1.iq.ISSUE:fu_busy_cnt 195 # FU busy when requested +system.cpu1.iq.ISSUE:fu_busy_rate 0.000753 # FU busy rate (busy events/executed inst) system.cpu1.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntAlu 11 5.95% 5.95% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 5.95% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 5.95% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 5.95% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 5.95% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.95% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.95% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.95% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.95% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdAdd 0 0.00% 5.95% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 5.95% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdAlu 0 0.00% 5.95% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdCmp 0 0.00% 5.95% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdCvt 0 0.00% 5.95% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdMisc 0 0.00% 5.95% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdMult 0 0.00% 5.95% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 5.95% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdShift 0 0.00% 5.95% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 5.95% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 5.95% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 5.95% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 5.95% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 5.95% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 5.95% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 5.95% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 5.95% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 5.95% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 5.95% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 5.95% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemRead 43 23.24% 29.19% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemWrite 131 70.81% 100.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntAlu 11 5.64% 5.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 5.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 5.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 5.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 5.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdAdd 0 0.00% 5.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 5.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdAlu 0 0.00% 5.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdCmp 0 0.00% 5.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdCvt 0 0.00% 5.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdMisc 0 0.00% 5.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdMult 0 0.00% 5.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 5.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdShift 0 0.00% 5.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 5.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 5.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 5.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 5.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 5.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 5.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 5.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 5.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 5.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 5.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 5.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemRead 53 27.18% 32.82% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemWrite 131 67.18% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:issued_per_cycle::samples 196087 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.989668 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.215562 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::samples 196498 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::mean 1.317917 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.287238 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::0 99332 50.66% 50.66% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::1 36909 18.82% 69.48% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::2 28876 14.73% 84.21% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::3 26632 13.58% 97.79% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::4 2531 1.29% 99.08% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::5 1564 0.80% 99.88% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::6 151 0.08% 99.95% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::0 79641 40.53% 40.53% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::1 27330 13.91% 54.44% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::2 43586 22.18% 76.62% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::3 41460 21.10% 97.72% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::4 2668 1.36% 99.08% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::5 1566 0.80% 99.87% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::6 155 0.08% 99.95% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::7 82 0.04% 99.99% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::8 10 0.01% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::total 196087 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:rate 0.970635 # Inst issue rate +system.cpu1.iq.ISSUE:issued_per_cycle::total 196498 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:rate 1.295669 # Inst issue rate system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes -system.cpu1.iq.int_alu_accesses 194246 # Number of integer alu accesses -system.cpu1.iq.int_inst_queue_reads 584396 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_wakeup_accesses 192754 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.int_inst_queue_writes 203505 # Number of integer instruction queue writes -system.cpu1.iq.iqInstsAdded 186439 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqInstsIssued 194061 # Number of instructions issued -system.cpu1.iq.iqNonSpecInstsAdded 10484 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqSquashedInstsExamined 6548 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.int_alu_accesses 259163 # Number of integer alu accesses +system.cpu1.iq.int_inst_queue_reads 714631 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_wakeup_accesses 257643 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.int_inst_queue_writes 268053 # Number of integer instruction queue writes +system.cpu1.iq.iqInstsAdded 254426 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqInstsIssued 258968 # Number of instructions issued +system.cpu1.iq.iqNonSpecInstsAdded 7176 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqSquashedInstsExamined 6422 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu1.iq.iqSquashedInstsIssued 2 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedNonSpecRemoved 678 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.iqSquashedOperandsExamined 6090 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.memDep0.conflictingLoads 31889 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 22377 # Number of conflicting stores. -system.cpu1.memDep0.insertedLoads 62331 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 26882 # Number of stores inserted to the mem dependence unit. -system.cpu1.misc_regfile_reads 89554 # number of misc regfile reads +system.cpu1.iq.iqSquashedNonSpecRemoved 561 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.iqSquashedOperandsExamined 5912 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.memDep0.conflictingLoads 43433 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 37289 # Number of conflicting stores. +system.cpu1.memDep0.insertedLoads 88859 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 41782 # Number of stores inserted to the mem dependence unit. +system.cpu1.misc_regfile_reads 131065 # number of misc regfile reads system.cpu1.misc_regfile_writes 646 # number of misc regfile writes -system.cpu1.numCycles 199932 # number of cpu cycles simulated +system.cpu1.numCycles 199872 # number of cpu cycles simulated system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.rename.RENAME:BlockCycles 9891 # Number of cycles rename is blocking -system.cpu1.rename.RENAME:CommittedMaps 147748 # Number of HB maps that are committed -system.cpu1.rename.RENAME:IQFullEvents 48 # Number of times rename has blocked due to IQ full -system.cpu1.rename.RENAME:IdleCycles 71551 # Number of cycles rename is idle -system.cpu1.rename.RENAME:LSQFullEvents 40 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RENAME:RenameLookups 422855 # Number of register rename lookups that rename has made -system.cpu1.rename.RENAME:RenamedInsts 231943 # Number of instructions processed by rename -system.cpu1.rename.RENAME:RenamedOperands 155885 # Number of destination operands rename has renamed -system.cpu1.rename.RENAME:RunCycles 92302 # Number of cycles rename is running -system.cpu1.rename.RENAME:SquashCycles 1784 # Number of cycles rename is squashing -system.cpu1.rename.RENAME:UnblockCycles 562 # Number of cycles rename is unblocking -system.cpu1.rename.RENAME:UndoneMaps 8137 # Number of HB maps that are undone due to squashing -system.cpu1.rename.RENAME:int_rename_lookups 422855 # Number of integer rename lookups -system.cpu1.rename.RENAME:serializeStallCycles 13360 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RENAME:serializingInsts 970 # count of serializing insts renamed -system.cpu1.rename.RENAME:skidInsts 2743 # count of insts added to the skid buffer -system.cpu1.rename.RENAME:tempSerializingInsts 1022 # count of temporary serializing insts renamed -system.cpu1.rob.rob_reads 416274 # The number of ROB reads -system.cpu1.rob.rob_writes 461144 # The number of ROB writes -system.cpu1.timesIdled 297 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.rename.RENAME:BlockCycles 7004 # Number of cycles rename is blocking +system.cpu1.rename.RENAME:CommittedMaps 204047 # Number of HB maps that are committed +system.cpu1.rename.RENAME:IQFullEvents 57 # Number of times rename has blocked due to IQ full +system.cpu1.rename.RENAME:IdleCycles 55307 # Number of cycles rename is idle +system.cpu1.rename.RENAME:LSQFullEvents 48 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RENAME:RenameLookups 588542 # Number of register rename lookups that rename has made +system.cpu1.rename.RENAME:RenamedInsts 308173 # Number of instructions processed by rename +system.cpu1.rename.RENAME:RenamedOperands 212215 # Number of destination operands rename has renamed +system.cpu1.rename.RENAME:RunCycles 112201 # Number of cycles rename is running +system.cpu1.rename.RENAME:SquashCycles 1741 # Number of cycles rename is squashing +system.cpu1.rename.RENAME:UnblockCycles 589 # Number of cycles rename is unblocking +system.cpu1.rename.RENAME:UndoneMaps 8168 # Number of HB maps that are undone due to squashing +system.cpu1.rename.RENAME:int_rename_lookups 588542 # Number of integer rename lookups +system.cpu1.rename.RENAME:serializeStallCycles 13057 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RENAME:serializingInsts 954 # count of serializing insts renamed +system.cpu1.rename.RENAME:skidInsts 2780 # count of insts added to the skid buffer +system.cpu1.rename.RENAME:tempSerializingInsts 1009 # count of temporary serializing insts renamed +system.cpu1.rob.rob_reads 493050 # The number of ROB reads +system.cpu1.rob.rob_writes 613675 # The number of ROB writes +system.cpu1.timesIdled 291 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.BPredUnit.BTBHits 58194 # Number of BTB hits -system.cpu2.BPredUnit.BTBLookups 60389 # Number of BTB lookups +system.cpu2.BPredUnit.BTBHits 55906 # Number of BTB hits +system.cpu2.BPredUnit.BTBLookups 58100 # Number of BTB lookups system.cpu2.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu2.BPredUnit.condIncorrect 1085 # Number of conditional branches incorrect -system.cpu2.BPredUnit.condPredicted 60491 # Number of conditional branches predicted -system.cpu2.BPredUnit.lookups 60491 # Number of BP lookups +system.cpu2.BPredUnit.condIncorrect 1096 # Number of conditional branches incorrect +system.cpu2.BPredUnit.condPredicted 58228 # Number of conditional branches predicted +system.cpu2.BPredUnit.lookups 58228 # Number of BP lookups system.cpu2.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu2.commit.COM:branches 57782 # Number of branches committed -system.cpu2.commit.COM:bw_lim_events 501 # number cycles where commit BW limit reached +system.cpu2.commit.COM:branches 55433 # Number of branches committed +system.cpu2.commit.COM:bw_lim_events 499 # number cycles where commit BW limit reached system.cpu2.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.commit.COM:committed_per_cycle::samples 185916 # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::mean 1.779174 # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::stdev 2.020750 # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::samples 185729 # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::mean 1.698900 # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::stdev 1.997080 # Number of insts commited each cycle system.cpu2.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::0 66151 35.58% 35.58% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::1 58504 31.47% 67.05% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::2 7458 4.01% 71.06% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::3 5724 3.08% 74.14% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::4 2452 1.32% 75.46% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::5 44514 23.94% 99.40% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::6 485 0.26% 99.66% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::7 127 0.07% 99.73% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::8 501 0.27% 100.00% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::0 70586 38.00% 38.00% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::1 56238 30.28% 68.28% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::2 7477 4.03% 72.31% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::3 6262 3.37% 75.68% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::4 2451 1.32% 77.00% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::5 41665 22.43% 99.43% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::6 421 0.23% 99.66% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::7 130 0.07% 99.73% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::8 499 0.27% 100.00% # Number of insts commited each cycle system.cpu2.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::total 185916 # Number of insts commited each cycle -system.cpu2.commit.COM:count 330777 # Number of instructions committed +system.cpu2.commit.COM:committed_per_cycle::total 185729 # Number of insts commited each cycle +system.cpu2.commit.COM:count 315535 # Number of instructions committed system.cpu2.commit.COM:fp_insts 0 # Number of committed floating point instructions. system.cpu2.commit.COM:function_calls 0 # Number of function calls committed. -system.cpu2.commit.COM:int_insts 226484 # Number of committed integer instructions. -system.cpu2.commit.COM:loads 98945 # Number of loads committed -system.cpu2.commit.COM:membars 4183 # Number of memory barriers committed -system.cpu2.commit.COM:refs 146579 # Number of memory references committed +system.cpu2.commit.COM:int_insts 215944 # Number of committed integer instructions. +system.cpu2.commit.COM:loads 93671 # Number of loads committed +system.cpu2.commit.COM:membars 4747 # Number of memory barriers committed +system.cpu2.commit.COM:refs 138392 # Number of memory references committed system.cpu2.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.branchMispredicts 1085 # The number of times a branch was mispredicted -system.cpu2.commit.commitCommittedInsts 330777 # The number of committed instructions -system.cpu2.commit.commitNonSpecStalls 4895 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.commitSquashedInsts 8092 # The number of squashed insts skipped by commit -system.cpu2.committedInsts 278020 # Number of Instructions Simulated -system.cpu2.committedInsts_total 278020 # Number of Instructions Simulated -system.cpu2.cpi 0.718078 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.718078 # CPI: Total CPI of All Threads -system.cpu2.dcache.ReadReq_accesses 55923 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_avg_miss_latency 22046.336207 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 14829.113924 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_hits 55459 # number of ReadReq hits -system.cpu2.dcache.ReadReq_miss_latency 10229500 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_rate 0.008297 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_misses 464 # number of ReadReq misses -system.cpu2.dcache.ReadReq_mshr_hits 306 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_miss_latency 2343000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate 0.002825 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_misses 158 # number of ReadReq MSHR misses -system.cpu2.dcache.SwapReq_accesses 66 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_avg_miss_latency 24990.740741 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 21990.740741 # average SwapReq mshr miss latency +system.cpu2.commit.branchMispredicts 1096 # The number of times a branch was mispredicted +system.cpu2.commit.commitCommittedInsts 315535 # The number of committed instructions +system.cpu2.commit.commitNonSpecStalls 5463 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.commitSquashedInsts 8360 # The number of squashed insts skipped by commit +system.cpu2.committedInsts 264567 # Number of Instructions Simulated +system.cpu2.committedInsts_total 264567 # Number of Instructions Simulated +system.cpu2.cpi 0.754365 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.754365 # CPI: Total CPI of All Threads +system.cpu2.dcache.ReadReq_accesses 53583 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_avg_miss_latency 22410.944206 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 15243.827160 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_hits 53117 # number of ReadReq hits +system.cpu2.dcache.ReadReq_miss_latency 10443500 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_rate 0.008697 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_misses 466 # number of ReadReq misses +system.cpu2.dcache.ReadReq_mshr_hits 304 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_miss_latency 2469500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate 0.003023 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_misses 162 # number of ReadReq MSHR misses +system.cpu2.dcache.SwapReq_accesses 70 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_avg_miss_latency 24534.482759 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 21534.482759 # average SwapReq mshr miss latency system.cpu2.dcache.SwapReq_hits 12 # number of SwapReq hits -system.cpu2.dcache.SwapReq_miss_latency 1349500 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_rate 0.818182 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_misses 54 # number of SwapReq misses -system.cpu2.dcache.SwapReq_mshr_miss_latency 1187500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_rate 0.818182 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_misses 54 # number of SwapReq MSHR misses -system.cpu2.dcache.WriteReq_accesses 47568 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_avg_miss_latency 23770.161290 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 15316.037736 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_hits 47444 # number of WriteReq hits -system.cpu2.dcache.WriteReq_miss_latency 2947500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_rate 0.002607 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_misses 124 # number of WriteReq misses +system.cpu2.dcache.SwapReq_miss_latency 1423000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_rate 0.828571 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_misses 58 # number of SwapReq misses +system.cpu2.dcache.SwapReq_mshr_miss_latency 1249000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_rate 0.828571 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_misses 58 # number of SwapReq MSHR misses +system.cpu2.dcache.WriteReq_accesses 44651 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_avg_miss_latency 23987.804878 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 15485.714286 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_hits 44528 # number of WriteReq hits +system.cpu2.dcache.WriteReq_miss_latency 2950500 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_rate 0.002755 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_misses 123 # number of WriteReq misses system.cpu2.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_miss_latency 1623500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_rate 0.002228 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_misses 106 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_miss_latency 1626000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_rate 0.002352 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_misses 105 # number of WriteReq MSHR misses system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu2.dcache.avg_refs 1779.400000 # Average number of references to valid blocks. +system.cpu2.dcache.avg_refs 1682.766667 # Average number of references to valid blocks. system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.demand_accesses 103491 # number of demand (read+write) accesses -system.cpu2.dcache.demand_avg_miss_latency 22409.863946 # average overall miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency 15024.621212 # average overall mshr miss latency -system.cpu2.dcache.demand_hits 102903 # number of demand (read+write) hits -system.cpu2.dcache.demand_miss_latency 13177000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_rate 0.005682 # miss rate for demand accesses -system.cpu2.dcache.demand_misses 588 # number of demand (read+write) misses -system.cpu2.dcache.demand_mshr_hits 324 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_miss_latency 3966500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_rate 0.002551 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_misses 264 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_accesses 98234 # number of demand (read+write) accesses +system.cpu2.dcache.demand_avg_miss_latency 22740.237691 # average overall miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency 15338.951311 # average overall mshr miss latency +system.cpu2.dcache.demand_hits 97645 # number of demand (read+write) hits +system.cpu2.dcache.demand_miss_latency 13394000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_rate 0.005996 # miss rate for demand accesses +system.cpu2.dcache.demand_misses 589 # number of demand (read+write) misses +system.cpu2.dcache.demand_mshr_hits 322 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_miss_latency 4095500 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_rate 0.002718 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_misses 267 # number of demand (read+write) MSHR misses system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.occ_%::0 0.052851 # Average percentage of cache occupancy -system.cpu2.dcache.occ_%::1 -0.017878 # Average percentage of cache occupancy -system.cpu2.dcache.occ_blocks::0 27.059534 # Average occupied blocks per context -system.cpu2.dcache.occ_blocks::1 -9.153554 # Average occupied blocks per context -system.cpu2.dcache.overall_accesses 103491 # number of overall (read+write) accesses -system.cpu2.dcache.overall_avg_miss_latency 22409.863946 # average overall miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency 15024.621212 # average overall mshr miss latency +system.cpu2.dcache.occ_%::0 0.052897 # Average percentage of cache occupancy +system.cpu2.dcache.occ_%::1 -0.018338 # Average percentage of cache occupancy +system.cpu2.dcache.occ_blocks::0 27.083354 # Average occupied blocks per context +system.cpu2.dcache.occ_blocks::1 -9.389236 # Average occupied blocks per context +system.cpu2.dcache.overall_accesses 98234 # number of overall (read+write) accesses +system.cpu2.dcache.overall_avg_miss_latency 22740.237691 # average overall miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency 15338.951311 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.dcache.overall_hits 102903 # number of overall hits -system.cpu2.dcache.overall_miss_latency 13177000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_rate 0.005682 # miss rate for overall accesses -system.cpu2.dcache.overall_misses 588 # number of overall misses -system.cpu2.dcache.overall_mshr_hits 324 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_miss_latency 3966500 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_rate 0.002551 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_misses 264 # number of overall MSHR misses +system.cpu2.dcache.overall_hits 97645 # number of overall hits +system.cpu2.dcache.overall_miss_latency 13394000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_rate 0.005996 # miss rate for overall accesses +system.cpu2.dcache.overall_misses 589 # number of overall misses +system.cpu2.dcache.overall_mshr_hits 322 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_miss_latency 4095500 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_rate 0.002718 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_misses 267 # number of overall MSHR misses system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu2.dcache.replacements 2 # number of replacements system.cpu2.dcache.sampled_refs 30 # Sample count of references to valid blocks. system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.dcache.tagsinuse 17.905980 # Cycle average of tags in use -system.cpu2.dcache.total_refs 53382 # Total number of references to valid blocks. +system.cpu2.dcache.tagsinuse 17.694118 # Cycle average of tags in use +system.cpu2.dcache.total_refs 50483 # Total number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.dcache.writebacks 1 # number of writebacks -system.cpu2.decode.DECODE:BlockedCycles 19187 # Number of cycles decode is blocked -system.cpu2.decode.DECODE:DecodedInsts 342711 # Number of instructions handled by decode -system.cpu2.decode.DECODE:IdleCycles 46061 # Number of cycles decode is idle -system.cpu2.decode.DECODE:RunCycles 116769 # Number of cycles decode is running -system.cpu2.decode.DECODE:SquashCycles 1740 # Number of cycles decode is squashing -system.cpu2.decode.DECODE:UnblockCycles 3898 # Number of cycles decode is unblocking -system.cpu2.fetch.Branches 60491 # Number of branches that fetch encountered -system.cpu2.fetch.CacheLines 17027 # Number of cache lines fetched -system.cpu2.fetch.Cycles 121028 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.IcacheSquashes 224 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.Insts 343825 # Number of instructions fetch has processed -system.cpu2.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.SquashCycles 1162 # Number of cycles fetch has spent squashing -system.cpu2.fetch.branchRate 0.303000 # Number of branch fetches per cycle -system.cpu2.fetch.icacheStallCycles 17027 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.predictedBranches 58194 # Number of branches that fetch has predicted taken -system.cpu2.fetch.rate 1.722225 # Number of inst fetches per cycle -system.cpu2.fetch.rateDist::samples 194280 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.769740 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.108066 # Number of instructions fetched each cycle (Total) +system.cpu2.decode.DECODE:BlockedCycles 20050 # Number of cycles decode is blocked +system.cpu2.decode.DECODE:DecodedInsts 327820 # Number of instructions handled by decode +system.cpu2.decode.DECODE:IdleCycles 49005 # Number of cycles decode is idle +system.cpu2.decode.DECODE:RunCycles 112255 # Number of cycles decode is running +system.cpu2.decode.DECODE:SquashCycles 1781 # Number of cycles decode is squashing +system.cpu2.decode.DECODE:UnblockCycles 4418 # Number of cycles decode is unblocking +system.cpu2.fetch.Branches 58228 # Number of branches that fetch encountered +system.cpu2.fetch.CacheLines 18194 # Number of cache lines fetched +system.cpu2.fetch.Cycles 117037 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.IcacheSquashes 225 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.Insts 328955 # Number of instructions fetch has processed +system.cpu2.fetch.MiscStallCycles 30 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.SquashCycles 1170 # Number of cycles fetch has spent squashing +system.cpu2.fetch.branchRate 0.291753 # Number of branch fetches per cycle +system.cpu2.fetch.icacheStallCycles 18194 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.predictedBranches 55906 # Number of branches that fetch has predicted taken +system.cpu2.fetch.rate 1.648236 # Number of inst fetches per cycle +system.cpu2.fetch.rateDist::samples 194114 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.694649 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.084542 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 73252 37.70% 37.70% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 61385 31.60% 69.30% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 5275 2.72% 72.02% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 2733 1.41% 73.42% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 1902 0.98% 74.40% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 45539 23.44% 97.84% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 2450 1.26% 99.10% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 264 0.14% 99.24% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1480 0.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 77077 39.71% 39.71% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 59674 30.74% 70.45% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 5837 3.01% 73.46% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 2794 1.44% 74.90% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 1893 0.98% 75.87% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 42627 21.96% 97.83% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 2458 1.27% 99.10% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 262 0.13% 99.23% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1492 0.77% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 194280 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::total 194114 # Number of instructions fetched each cycle (Total) system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.icache.ReadReq_accesses 17027 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_avg_miss_latency 21608.921162 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency 18272.935780 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_hits 16545 # number of ReadReq hits -system.cpu2.icache.ReadReq_miss_latency 10415500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_rate 0.028308 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_misses 482 # number of ReadReq misses -system.cpu2.icache.ReadReq_mshr_hits 46 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_miss_latency 7967000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate 0.025606 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_misses 436 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_accesses 18194 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_avg_miss_latency 21635.330579 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency 18220.454545 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_hits 17710 # number of ReadReq hits +system.cpu2.icache.ReadReq_miss_latency 10471500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_rate 0.026602 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_misses 484 # number of ReadReq misses +system.cpu2.icache.ReadReq_mshr_hits 44 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_miss_latency 8017000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate 0.024184 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_misses 440 # number of ReadReq MSHR misses system.cpu2.icache.avg_blocked_cycles::no_mshrs 18250 # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu2.icache.avg_refs 37.947248 # Average number of references to valid blocks. +system.cpu2.icache.avg_refs 40.250000 # Average number of references to valid blocks. system.cpu2.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_mshrs 36500 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.demand_accesses 17027 # number of demand (read+write) accesses -system.cpu2.icache.demand_avg_miss_latency 21608.921162 # average overall miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency 18272.935780 # average overall mshr miss latency -system.cpu2.icache.demand_hits 16545 # number of demand (read+write) hits -system.cpu2.icache.demand_miss_latency 10415500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_rate 0.028308 # miss rate for demand accesses -system.cpu2.icache.demand_misses 482 # number of demand (read+write) misses -system.cpu2.icache.demand_mshr_hits 46 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_miss_latency 7967000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_rate 0.025606 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_misses 436 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_accesses 18194 # number of demand (read+write) accesses +system.cpu2.icache.demand_avg_miss_latency 21635.330579 # average overall miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency 18220.454545 # average overall mshr miss latency +system.cpu2.icache.demand_hits 17710 # number of demand (read+write) hits +system.cpu2.icache.demand_miss_latency 10471500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_rate 0.026602 # miss rate for demand accesses +system.cpu2.icache.demand_misses 484 # number of demand (read+write) misses +system.cpu2.icache.demand_mshr_hits 44 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_miss_latency 8017000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_rate 0.024184 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_misses 440 # number of demand (read+write) MSHR misses system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.icache.occ_%::0 0.176617 # Average percentage of cache occupancy -system.cpu2.icache.occ_blocks::0 90.427890 # Average occupied blocks per context -system.cpu2.icache.overall_accesses 17027 # number of overall (read+write) accesses -system.cpu2.icache.overall_avg_miss_latency 21608.921162 # average overall miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency 18272.935780 # average overall mshr miss latency +system.cpu2.icache.occ_%::0 0.176645 # Average percentage of cache occupancy +system.cpu2.icache.occ_blocks::0 90.442244 # Average occupied blocks per context +system.cpu2.icache.overall_accesses 18194 # number of overall (read+write) accesses +system.cpu2.icache.overall_avg_miss_latency 21635.330579 # average overall miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency 18220.454545 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.icache.overall_hits 16545 # number of overall hits -system.cpu2.icache.overall_miss_latency 10415500 # number of overall miss cycles -system.cpu2.icache.overall_miss_rate 0.028308 # miss rate for overall accesses -system.cpu2.icache.overall_misses 482 # number of overall misses -system.cpu2.icache.overall_mshr_hits 46 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_miss_latency 7967000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_rate 0.025606 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_misses 436 # number of overall MSHR misses +system.cpu2.icache.overall_hits 17710 # number of overall hits +system.cpu2.icache.overall_miss_latency 10471500 # number of overall miss cycles +system.cpu2.icache.overall_miss_rate 0.026602 # miss rate for overall accesses +system.cpu2.icache.overall_misses 484 # number of overall misses +system.cpu2.icache.overall_mshr_hits 44 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_miss_latency 8017000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_rate 0.024184 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_misses 440 # number of overall MSHR misses system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.icache.replacements 326 # number of replacements -system.cpu2.icache.sampled_refs 436 # Sample count of references to valid blocks. +system.cpu2.icache.replacements 330 # number of replacements +system.cpu2.icache.sampled_refs 440 # Sample count of references to valid blocks. system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.icache.tagsinuse 90.427890 # Cycle average of tags in use -system.cpu2.icache.total_refs 16545 # Total number of references to valid blocks. +system.cpu2.icache.tagsinuse 90.442244 # Cycle average of tags in use +system.cpu2.icache.total_refs 17710 # Total number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.icache.writebacks 0 # number of writebacks -system.cpu2.idleCycles 5360 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.iew.EXEC:branches 58330 # Number of branches executed -system.cpu2.iew.EXEC:nop 49308 # number of nop insts executed -system.cpu2.iew.EXEC:rate 1.432328 # Inst execution rate -system.cpu2.iew.EXEC:refs 147694 # number of memory reference insts executed -system.cpu2.iew.EXEC:stores 47984 # Number of stores executed +system.cpu2.idleCycles 5466 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.iew.EXEC:branches 55984 # Number of branches executed +system.cpu2.iew.EXEC:nop 47025 # number of nop insts executed +system.cpu2.iew.EXEC:rate 1.368298 # Inst execution rate +system.cpu2.iew.EXEC:refs 139522 # number of memory reference insts executed +system.cpu2.iew.EXEC:stores 45069 # Number of stores executed system.cpu2.iew.EXEC:swp 0 # number of swp insts executed -system.cpu2.iew.WB:consumers 167735 # num instructions consuming a value -system.cpu2.iew.WB:count 285574 # cumulative count of insts written-back -system.cpu2.iew.WB:fanout 0.978186 # average fanout of values written-back +system.cpu2.iew.WB:consumers 159565 # num instructions consuming a value +system.cpu2.iew.WB:count 272710 # cumulative count of insts written-back +system.cpu2.iew.WB:fanout 0.977063 # average fanout of values written-back system.cpu2.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu2.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.iew.WB:producers 164076 # num instructions producing a value -system.cpu2.iew.WB:rate 1.430445 # insts written-back per cycle -system.cpu2.iew.WB:sent 285706 # cumulative count of insts sent to commit -system.cpu2.iew.branchMispredicts 1190 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewBlockCycles 1666 # Number of cycles IEW is blocking -system.cpu2.iew.iewDispLoadInsts 100435 # Number of dispatched load instructions -system.cpu2.iew.iewDispNonSpecInsts 918 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewDispSquashedInsts 521 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispStoreInsts 48400 # Number of dispatched store instructions -system.cpu2.iew.iewDispatchedInsts 338900 # Number of instructions dispatched to IQ -system.cpu2.iew.iewExecLoadInsts 99710 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 966 # Number of squashed instructions skipped in execute -system.cpu2.iew.iewExecutedInsts 285950 # Number of executed instructions -system.cpu2.iew.iewIQFullEvents 50 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.WB:producers 155905 # num instructions producing a value +system.cpu2.iew.WB:rate 1.366419 # insts written-back per cycle +system.cpu2.iew.WB:sent 272842 # cumulative count of insts sent to commit +system.cpu2.iew.branchMispredicts 1198 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewBlockCycles 1731 # Number of cycles IEW is blocking +system.cpu2.iew.iewDispLoadInsts 95225 # Number of dispatched load instructions +system.cpu2.iew.iewDispNonSpecInsts 927 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewDispSquashedInsts 555 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispStoreInsts 45493 # Number of dispatched store instructions +system.cpu2.iew.iewDispatchedInsts 323925 # Number of instructions dispatched to IQ +system.cpu2.iew.iewExecLoadInsts 94453 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 959 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewExecutedInsts 273085 # Number of executed instructions +system.cpu2.iew.iewIQFullEvents 57 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.iewSquashCycles 1740 # Number of cycles IEW is squashing -system.cpu2.iew.iewUnblockCycles 60 # Number of cycles IEW is unblocking +system.cpu2.iew.iewSquashCycles 1781 # Number of cycles IEW is squashing +system.cpu2.iew.iewUnblockCycles 67 # Number of cycles IEW is unblocking system.cpu2.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu2.iew.lsq.thread.0.forwLoads 43769 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread.0.forwLoads 40852 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu2.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu2.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu2.iew.lsq.thread.0.memOrderViolation 35 # Number of memory ordering violations +system.cpu2.iew.lsq.thread.0.memOrderViolation 29 # Number of memory ordering violations system.cpu2.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread.0.squashedLoads 1490 # Number of loads squashed -system.cpu2.iew.lsq.thread.0.squashedStores 766 # Number of stores squashed -system.cpu2.iew.memOrderViolationEvents 35 # Number of memory order violations -system.cpu2.iew.predictedNotTakenIncorrect 199 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.predictedTakenIncorrect 991 # Number of branches that were predicted taken incorrectly -system.cpu2.int_regfile_reads 500577 # number of integer regfile reads -system.cpu2.int_regfile_writes 231428 # number of integer regfile writes -system.cpu2.ipc 1.392607 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.392607 # IPC: Total IPC of All Threads +system.cpu2.iew.lsq.thread.0.squashedLoads 1554 # Number of loads squashed +system.cpu2.iew.lsq.thread.0.squashedStores 772 # Number of stores squashed +system.cpu2.iew.memOrderViolationEvents 29 # Number of memory order violations +system.cpu2.iew.predictedNotTakenIncorrect 202 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.predictedTakenIncorrect 996 # Number of branches that were predicted taken incorrectly +system.cpu2.int_regfile_reads 476036 # number of integer regfile reads +system.cpu2.int_regfile_writes 220349 # number of integer regfile writes +system.cpu2.ipc 1.325619 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.325619 # IPC: Total IPC of All Threads system.cpu2.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::IntAlu 134825 46.99% 46.99% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::IntMult 0 0.00% 46.99% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 46.99% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 46.99% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 46.99% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 46.99% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 46.99% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 46.99% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 46.99% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 46.99% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 46.99% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 46.99% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 46.99% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 46.99% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 46.99% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 46.99% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 46.99% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 46.99% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 46.99% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 46.99% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 46.99% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 46.99% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 46.99% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 46.99% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 46.99% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 46.99% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 46.99% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 46.99% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 46.99% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::MemRead 104076 36.27% 83.27% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::MemWrite 48015 16.73% 100.00% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::IntAlu 129561 47.28% 47.28% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::IntMult 0 0.00% 47.28% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 47.28% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 47.28% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 47.28% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 47.28% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 47.28% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 47.28% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 47.28% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 47.28% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 47.28% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 47.28% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 47.28% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 47.28% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 47.28% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 47.28% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 47.28% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 47.28% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 47.28% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 47.28% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 47.28% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 47.28% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 47.28% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 47.28% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 47.28% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 47.28% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 47.28% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 47.28% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 47.28% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::MemRead 99383 36.27% 83.54% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::MemWrite 45100 16.46% 100.00% # Type of FU issued system.cpu2.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::total 286916 # Type of FU issued -system.cpu2.iq.ISSUE:fu_busy_cnt 198 # FU busy when requested -system.cpu2.iq.ISSUE:fu_busy_rate 0.000690 # FU busy rate (busy events/executed inst) +system.cpu2.iq.ISSUE:FU_type_0::total 274044 # Type of FU issued +system.cpu2.iq.ISSUE:fu_busy_cnt 205 # FU busy when requested +system.cpu2.iq.ISSUE:fu_busy_rate 0.000748 # FU busy rate (busy events/executed inst) system.cpu2.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::IntAlu 12 6.06% 6.06% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::IntMult 0 0.00% 6.06% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::IntDiv 0 0.00% 6.06% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::FloatAdd 0 0.00% 6.06% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::FloatCmp 0 0.00% 6.06% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::FloatCvt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::FloatMult 0 0.00% 6.06% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::FloatDiv 0 0.00% 6.06% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdAdd 0 0.00% 6.06% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdAlu 0 0.00% 6.06% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdCmp 0 0.00% 6.06% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdCvt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdMisc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdMult 0 0.00% 6.06% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdShift 0 0.00% 6.06% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 6.06% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 6.06% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 6.06% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 6.06% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 6.06% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::MemRead 55 27.78% 33.84% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::MemWrite 131 66.16% 100.00% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::IntAlu 12 5.85% 5.85% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::IntMult 0 0.00% 5.85% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::IntDiv 0 0.00% 5.85% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::FloatAdd 0 0.00% 5.85% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::FloatCmp 0 0.00% 5.85% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.85% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.85% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.85% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.85% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdAdd 0 0.00% 5.85% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 5.85% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdAlu 0 0.00% 5.85% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdCmp 0 0.00% 5.85% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdCvt 0 0.00% 5.85% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdMisc 0 0.00% 5.85% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdMult 0 0.00% 5.85% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 5.85% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdShift 0 0.00% 5.85% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 5.85% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 5.85% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 5.85% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 5.85% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 5.85% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 5.85% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 5.85% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 5.85% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 5.85% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 5.85% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 5.85% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::MemRead 62 30.24% 36.10% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::MemWrite 131 63.90% 100.00% # attempts to use FU when none available system.cpu2.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.ISSUE:issued_per_cycle::samples 194280 # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::mean 1.476817 # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::stdev 1.291045 # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::samples 194114 # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::mean 1.411768 # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::stdev 1.293131 # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::0 69262 35.65% 35.65% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::1 22249 11.45% 47.10% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::2 50270 25.88% 72.98% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::3 48052 24.73% 97.71% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::4 2627 1.35% 99.06% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::5 1560 0.80% 99.87% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::6 166 0.09% 99.95% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::0 73286 37.75% 37.75% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::1 23867 12.30% 50.05% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::2 47309 24.37% 74.42% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::3 45216 23.29% 97.71% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::4 2634 1.36% 99.07% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::5 1540 0.79% 99.87% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::6 168 0.09% 99.95% # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::7 85 0.04% 100.00% # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::8 9 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::total 194280 # Number of insts issued each cycle -system.cpu2.iq.ISSUE:rate 1.437167 # Inst issue rate +system.cpu2.iq.ISSUE:issued_per_cycle::total 194114 # Number of insts issued each cycle +system.cpu2.iq.ISSUE:rate 1.373104 # Inst issue rate system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes -system.cpu2.iq.int_alu_accesses 287114 # Number of integer alu accesses -system.cpu2.iq.int_inst_queue_reads 768311 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_wakeup_accesses 285574 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.int_inst_queue_writes 296099 # Number of integer instruction queue writes -system.cpu2.iq.iqInstsAdded 284164 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqInstsIssued 286916 # Number of instructions issued -system.cpu2.iq.iqNonSpecInstsAdded 5428 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqSquashedInstsExamined 6474 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.int_alu_accesses 274249 # Number of integer alu accesses +system.cpu2.iq.int_inst_queue_reads 742408 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_wakeup_accesses 272710 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.int_inst_queue_writes 283590 # Number of integer instruction queue writes +system.cpu2.iq.iqInstsAdded 270836 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqInstsIssued 274044 # Number of instructions issued +system.cpu2.iq.iqNonSpecInstsAdded 6064 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqSquashedInstsExamined 6661 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu2.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedNonSpecRemoved 533 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.iqSquashedOperandsExamined 6110 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.memDep0.conflictingLoads 48437 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 43927 # Number of conflicting stores. -system.cpu2.memDep0.insertedLoads 100435 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 48400 # Number of stores inserted to the mem dependence unit. -system.cpu2.misc_regfile_reads 149234 # number of misc regfile reads +system.cpu2.iq.iqSquashedNonSpecRemoved 601 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.iqSquashedOperandsExamined 6335 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.memDep0.conflictingLoads 46039 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 41011 # Number of conflicting stores. +system.cpu2.memDep0.insertedLoads 95225 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 45493 # Number of stores inserted to the mem dependence unit. +system.cpu2.misc_regfile_reads 141060 # number of misc regfile reads system.cpu2.misc_regfile_writes 646 # number of misc regfile writes -system.cpu2.numCycles 199640 # number of cpu cycles simulated +system.cpu2.numCycles 199580 # number of cpu cycles simulated system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu2.rename.RENAME:BlockCycles 5634 # Number of cycles rename is blocking -system.cpu2.rename.RENAME:CommittedMaps 228819 # Number of HB maps that are committed -system.cpu2.rename.RENAME:IQFullEvents 67 # Number of times rename has blocked due to IQ full -system.cpu2.rename.RENAME:IdleCycles 46667 # Number of cycles rename is idle -system.cpu2.rename.RENAME:LSQFullEvents 60 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RENAME:RenameLookups 661216 # Number of register rename lookups that rename has made -system.cpu2.rename.RENAME:RenamedInsts 341037 # Number of instructions processed by rename -system.cpu2.rename.RENAME:RenamedOperands 237006 # Number of destination operands rename has renamed -system.cpu2.rename.RENAME:RunCycles 120203 # Number of cycles rename is running -system.cpu2.rename.RENAME:SquashCycles 1740 # Number of cycles rename is squashing -system.cpu2.rename.RENAME:UnblockCycles 620 # Number of cycles rename is unblocking -system.cpu2.rename.RENAME:UndoneMaps 8187 # Number of HB maps that are undone due to squashing -system.cpu2.rename.RENAME:int_rename_lookups 661216 # Number of integer rename lookups -system.cpu2.rename.RENAME:serializeStallCycles 12791 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RENAME:serializingInsts 940 # count of serializing insts renamed -system.cpu2.rename.RENAME:skidInsts 2775 # count of insts added to the skid buffer -system.cpu2.rename.RENAME:tempSerializingInsts 995 # count of temporary serializing insts renamed -system.cpu2.rob.rob_reads 523697 # The number of ROB reads -system.cpu2.rob.rob_writes 679481 # The number of ROB writes -system.cpu2.timesIdled 296 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.rename.RENAME:BlockCycles 6241 # Number of cycles rename is blocking +system.cpu2.rename.RENAME:CommittedMaps 217715 # Number of HB maps that are committed +system.cpu2.rename.RENAME:IQFullEvents 58 # Number of times rename has blocked due to IQ full +system.cpu2.rename.RENAME:IdleCycles 49628 # Number of cycles rename is idle +system.cpu2.rename.RENAME:LSQFullEvents 58 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RENAME:RenameLookups 628783 # Number of register rename lookups that rename has made +system.cpu2.rename.RENAME:RenamedInsts 326092 # Number of instructions processed by rename +system.cpu2.rename.RENAME:RenamedOperands 225995 # Number of destination operands rename has renamed +system.cpu2.rename.RENAME:RunCycles 116192 # Number of cycles rename is running +system.cpu2.rename.RENAME:SquashCycles 1781 # Number of cycles rename is squashing +system.cpu2.rename.RENAME:UnblockCycles 614 # Number of cycles rename is unblocking +system.cpu2.rename.RENAME:UndoneMaps 8280 # Number of HB maps that are undone due to squashing +system.cpu2.rename.RENAME:int_rename_lookups 628783 # Number of integer rename lookups +system.cpu2.rename.RENAME:serializeStallCycles 13053 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RENAME:serializingInsts 948 # count of serializing insts renamed +system.cpu2.rename.RENAME:skidInsts 2856 # count of insts added to the skid buffer +system.cpu2.rename.RENAME:tempSerializingInsts 1003 # count of temporary serializing insts renamed +system.cpu2.rob.rob_reads 508538 # The number of ROB reads +system.cpu2.rob.rob_writes 649574 # The number of ROB writes +system.cpu2.timesIdled 302 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.BPredUnit.BTBHits 53101 # Number of BTB hits -system.cpu3.BPredUnit.BTBLookups 55313 # Number of BTB lookups +system.cpu3.BPredUnit.BTBHits 43772 # Number of BTB hits +system.cpu3.BPredUnit.BTBLookups 45981 # Number of BTB lookups system.cpu3.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu3.BPredUnit.condIncorrect 1094 # Number of conditional branches incorrect -system.cpu3.BPredUnit.condPredicted 55399 # Number of conditional branches predicted -system.cpu3.BPredUnit.lookups 55399 # Number of BP lookups +system.cpu3.BPredUnit.condIncorrect 1096 # Number of conditional branches incorrect +system.cpu3.BPredUnit.condPredicted 46026 # Number of conditional branches predicted +system.cpu3.BPredUnit.lookups 46026 # Number of BP lookups system.cpu3.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu3.commit.COM:branches 52563 # Number of branches committed +system.cpu3.commit.COM:branches 43201 # Number of branches committed system.cpu3.commit.COM:bw_lim_events 486 # number cycles where commit BW limit reached system.cpu3.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.commit.COM:committed_per_cycle::samples 187872 # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::mean 1.575583 # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::stdev 1.953160 # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::samples 187492 # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::mean 1.251248 # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::stdev 1.795283 # Number of insts commited each cycle system.cpu3.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::0 78438 41.75% 41.75% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::1 53385 28.42% 70.17% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::2 7469 3.98% 74.14% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::3 7434 3.96% 78.10% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::4 2454 1.31% 79.41% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::5 37686 20.06% 99.46% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::6 391 0.21% 99.67% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::7 129 0.07% 99.74% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::0 96787 51.62% 51.62% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::1 44013 23.47% 75.10% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::2 7489 3.99% 79.09% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::3 10030 5.35% 84.44% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::4 2457 1.31% 85.75% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::5 25706 13.71% 99.46% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::6 396 0.21% 99.67% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::7 128 0.07% 99.74% # Number of insts commited each cycle system.cpu3.commit.COM:committed_per_cycle::8 486 0.26% 100.00% # Number of insts commited each cycle system.cpu3.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::total 187872 # Number of insts commited each cycle -system.cpu3.commit.COM:count 296008 # Number of instructions committed +system.cpu3.commit.COM:committed_per_cycle::total 187492 # Number of insts commited each cycle +system.cpu3.commit.COM:count 234599 # Number of instructions committed system.cpu3.commit.COM:fp_insts 0 # Number of committed floating point instructions. system.cpu3.commit.COM:function_calls 0 # Number of function calls committed. -system.cpu3.commit.COM:int_insts 202157 # Number of committed integer instructions. -system.cpu3.commit.COM:loads 86777 # Number of loads committed -system.cpu3.commit.COM:membars 5899 # Number of memory barriers committed -system.cpu3.commit.COM:refs 127476 # Number of memory references committed +system.cpu3.commit.COM:int_insts 159474 # Number of committed integer instructions. +system.cpu3.commit.COM:loads 65432 # Number of loads committed +system.cpu3.commit.COM:membars 8520 # Number of memory barriers committed +system.cpu3.commit.COM:refs 94154 # Number of memory references committed system.cpu3.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.branchMispredicts 1094 # The number of times a branch was mispredicted -system.cpu3.commit.commitCommittedInsts 296008 # The number of committed instructions -system.cpu3.commit.commitNonSpecStalls 6615 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.commitSquashedInsts 8397 # The number of squashed insts skipped by commit -system.cpu3.committedInsts 246758 # Number of Instructions Simulated -system.cpu3.committedInsts_total 246758 # Number of Instructions Simulated -system.cpu3.cpi 0.807958 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.807958 # CPI: Total CPI of All Threads -system.cpu3.dcache.ReadReq_accesses 50677 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_avg_miss_latency 21660.356347 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 13875 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_hits 50228 # number of ReadReq hits -system.cpu3.dcache.ReadReq_miss_latency 9725500 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_rate 0.008860 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_misses 449 # number of ReadReq misses -system.cpu3.dcache.ReadReq_mshr_hits 289 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_miss_latency 2220000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate 0.003157 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_misses 160 # number of ReadReq MSHR misses -system.cpu3.dcache.SwapReq_accesses 70 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_avg_miss_latency 26068.965517 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 23068.965517 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_hits 12 # number of SwapReq hits -system.cpu3.dcache.SwapReq_miss_latency 1512000 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_rate 0.828571 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_misses 58 # number of SwapReq misses -system.cpu3.dcache.SwapReq_mshr_miss_latency 1338000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_rate 0.828571 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_misses 58 # number of SwapReq MSHR misses -system.cpu3.dcache.WriteReq_accesses 40629 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_avg_miss_latency 23540.650407 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 15301.886792 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_hits 40506 # number of WriteReq hits -system.cpu3.dcache.WriteReq_miss_latency 2895500 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_rate 0.003027 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_misses 123 # number of WriteReq misses -system.cpu3.dcache.WriteReq_mshr_hits 17 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_miss_latency 1622000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_rate 0.002609 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_misses 106 # number of WriteReq MSHR misses +system.cpu3.commit.branchMispredicts 1096 # The number of times a branch was mispredicted +system.cpu3.commit.commitCommittedInsts 234599 # The number of committed instructions +system.cpu3.commit.commitNonSpecStalls 9238 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.commitSquashedInsts 8312 # The number of squashed insts skipped by commit +system.cpu3.committedInsts 192092 # Number of Instructions Simulated +system.cpu3.committedInsts_total 192092 # Number of Instructions Simulated +system.cpu3.cpi 1.037576 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.037576 # CPI: Total CPI of All Threads +system.cpu3.dcache.ReadReq_accesses 41296 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_avg_miss_latency 22460.431655 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 14148.484848 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_hits 40879 # number of ReadReq hits +system.cpu3.dcache.ReadReq_miss_latency 9366000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_rate 0.010098 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_misses 417 # number of ReadReq misses +system.cpu3.dcache.ReadReq_mshr_hits 252 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_miss_latency 2334500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate 0.003996 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_misses 165 # number of ReadReq MSHR misses +system.cpu3.dcache.SwapReq_accesses 72 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_avg_miss_latency 26552.631579 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 23552.631579 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_hits 15 # number of SwapReq hits +system.cpu3.dcache.SwapReq_miss_latency 1513500 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_rate 0.791667 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_misses 57 # number of SwapReq misses +system.cpu3.dcache.SwapReq_mshr_miss_latency 1342500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_rate 0.791667 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_misses 57 # number of SwapReq MSHR misses +system.cpu3.dcache.WriteReq_accesses 28650 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_avg_miss_latency 23359.504132 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 15274.509804 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_hits 28529 # number of WriteReq hits +system.cpu3.dcache.WriteReq_miss_latency 2826500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_rate 0.004223 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_misses 121 # number of WriteReq misses +system.cpu3.dcache.WriteReq_mshr_hits 19 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_miss_latency 1558000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_rate 0.003560 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu3.dcache.avg_refs 1601.034483 # Average number of references to valid blocks. +system.cpu3.dcache.avg_refs 1150.100000 # Average number of references to valid blocks. system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.demand_accesses 91306 # number of demand (read+write) accesses -system.cpu3.dcache.demand_avg_miss_latency 22064.685315 # average overall miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency 14443.609023 # average overall mshr miss latency -system.cpu3.dcache.demand_hits 90734 # number of demand (read+write) hits -system.cpu3.dcache.demand_miss_latency 12621000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_rate 0.006265 # miss rate for demand accesses -system.cpu3.dcache.demand_misses 572 # number of demand (read+write) misses -system.cpu3.dcache.demand_mshr_hits 306 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_miss_latency 3842000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_rate 0.002913 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_misses 266 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_accesses 69946 # number of demand (read+write) accesses +system.cpu3.dcache.demand_avg_miss_latency 22662.639405 # average overall miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency 14578.651685 # average overall mshr miss latency +system.cpu3.dcache.demand_hits 69408 # number of demand (read+write) hits +system.cpu3.dcache.demand_miss_latency 12192500 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_rate 0.007692 # miss rate for demand accesses +system.cpu3.dcache.demand_misses 538 # number of demand (read+write) misses +system.cpu3.dcache.demand_mshr_hits 271 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_miss_latency 3892500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_rate 0.003817 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_misses 267 # number of demand (read+write) MSHR misses system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.occ_%::0 0.048988 # Average percentage of cache occupancy -system.cpu3.dcache.occ_%::1 -0.020365 # Average percentage of cache occupancy -system.cpu3.dcache.occ_blocks::0 25.081960 # Average occupied blocks per context -system.cpu3.dcache.occ_blocks::1 -10.426668 # Average occupied blocks per context -system.cpu3.dcache.overall_accesses 91306 # number of overall (read+write) accesses -system.cpu3.dcache.overall_avg_miss_latency 22064.685315 # average overall miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency 14443.609023 # average overall mshr miss latency +system.cpu3.dcache.occ_%::0 0.047232 # Average percentage of cache occupancy +system.cpu3.dcache.occ_%::1 -0.016274 # Average percentage of cache occupancy +system.cpu3.dcache.occ_blocks::0 24.182757 # Average occupied blocks per context +system.cpu3.dcache.occ_blocks::1 -8.332061 # Average occupied blocks per context +system.cpu3.dcache.overall_accesses 69946 # number of overall (read+write) accesses +system.cpu3.dcache.overall_avg_miss_latency 22662.639405 # average overall miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency 14578.651685 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.dcache.overall_hits 90734 # number of overall hits -system.cpu3.dcache.overall_miss_latency 12621000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_rate 0.006265 # miss rate for overall accesses -system.cpu3.dcache.overall_misses 572 # number of overall misses -system.cpu3.dcache.overall_mshr_hits 306 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_miss_latency 3842000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_rate 0.002913 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_misses 266 # number of overall MSHR misses +system.cpu3.dcache.overall_hits 69408 # number of overall hits +system.cpu3.dcache.overall_miss_latency 12192500 # number of overall miss cycles +system.cpu3.dcache.overall_miss_rate 0.007692 # miss rate for overall accesses +system.cpu3.dcache.overall_misses 538 # number of overall misses +system.cpu3.dcache.overall_mshr_hits 271 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_miss_latency 3892500 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_rate 0.003817 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_misses 267 # number of overall MSHR misses system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu3.dcache.replacements 2 # number of replacements -system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu3.dcache.sampled_refs 30 # Sample count of references to valid blocks. system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.dcache.tagsinuse 14.655292 # Cycle average of tags in use -system.cpu3.dcache.total_refs 46430 # Total number of references to valid blocks. +system.cpu3.dcache.tagsinuse 15.850697 # Cycle average of tags in use +system.cpu3.dcache.total_refs 34503 # Total number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.dcache.writebacks 1 # number of writebacks -system.cpu3.decode.DECODE:BlockedCycles 21089 # Number of cycles decode is blocked -system.cpu3.decode.DECODE:DecodedInsts 308413 # Number of instructions handled by decode -system.cpu3.decode.DECODE:IdleCycles 54614 # Number of cycles decode is idle -system.cpu3.decode.DECODE:RunCycles 106676 # Number of cycles decode is running -system.cpu3.decode.DECODE:SquashCycles 1792 # Number of cycles decode is squashing -system.cpu3.decode.DECODE:UnblockCycles 5492 # Number of cycles decode is unblocking -system.cpu3.fetch.Branches 55399 # Number of branches that fetch encountered -system.cpu3.fetch.CacheLines 20572 # Number of cache lines fetched -system.cpu3.fetch.Cycles 112541 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.IcacheSquashes 221 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.Insts 309543 # Number of instructions fetch has processed -system.cpu3.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.decode.DECODE:BlockedCycles 23404 # Number of cycles decode is blocked +system.cpu3.decode.DECODE:DecodedInsts 246917 # Number of instructions handled by decode +system.cpu3.decode.DECODE:IdleCycles 67894 # Number of cycles decode is idle +system.cpu3.decode.DECODE:RunCycles 88329 # Number of cycles decode is running +system.cpu3.decode.DECODE:SquashCycles 1781 # Number of cycles decode is squashing +system.cpu3.decode.DECODE:UnblockCycles 7864 # Number of cycles decode is unblocking +system.cpu3.fetch.Branches 46026 # Number of branches that fetch encountered +system.cpu3.fetch.CacheLines 26017 # Number of cache lines fetched +system.cpu3.fetch.Cycles 96566 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.IcacheSquashes 224 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.Insts 248038 # Number of instructions fetch has processed +system.cpu3.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu3.fetch.SquashCycles 1170 # Number of cycles fetch has spent squashing -system.cpu3.fetch.branchRate 0.277870 # Number of branch fetches per cycle -system.cpu3.fetch.icacheStallCycles 20572 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.predictedBranches 53101 # Number of branches that fetch has predicted taken -system.cpu3.fetch.rate 1.552606 # Number of inst fetches per cycle -system.cpu3.fetch.rateDist::samples 196296 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.576920 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.037630 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.230927 # Number of branch fetches per cycle +system.cpu3.fetch.icacheStallCycles 26017 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.predictedBranches 43772 # Number of branches that fetch has predicted taken +system.cpu3.fetch.rate 1.244483 # Number of inst fetches per cycle +system.cpu3.fetch.rateDist::samples 195889 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.266217 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 1.878921 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 83755 42.67% 42.67% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 58002 29.55% 72.22% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 7019 3.58% 75.79% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 2809 1.43% 77.22% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 1911 0.97% 78.20% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 38598 19.66% 97.86% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 2463 1.25% 99.11% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 248 0.13% 99.24% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 1491 0.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 99323 50.70% 50.70% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 51378 26.23% 76.93% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 9749 4.98% 81.91% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 2746 1.40% 83.31% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 1924 0.98% 84.29% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 26575 13.57% 97.86% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 2472 1.26% 99.12% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 255 0.13% 99.25% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 1467 0.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 196296 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::total 195889 # Number of instructions fetched each cycle (Total) system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.icache.ReadReq_accesses 20572 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_avg_miss_latency 14541.928721 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11822.799097 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_hits 20095 # number of ReadReq hits -system.cpu3.icache.ReadReq_miss_latency 6936500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_rate 0.023187 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_misses 477 # number of ReadReq misses -system.cpu3.icache.ReadReq_mshr_hits 34 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_miss_latency 5237500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate 0.021534 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_accesses 26017 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_avg_miss_latency 14208.939709 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11549.661400 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_hits 25536 # number of ReadReq hits +system.cpu3.icache.ReadReq_miss_latency 6834500 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_rate 0.018488 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_misses 481 # number of ReadReq misses +system.cpu3.icache.ReadReq_mshr_hits 38 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_miss_latency 5116500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate 0.017027 # mshr miss rate for ReadReq accesses system.cpu3.icache.ReadReq_mshr_misses 443 # number of ReadReq MSHR misses system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu3.icache.avg_refs 45.361174 # Average number of references to valid blocks. +system.cpu3.icache.avg_refs 57.643341 # Average number of references to valid blocks. system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.demand_accesses 20572 # number of demand (read+write) accesses -system.cpu3.icache.demand_avg_miss_latency 14541.928721 # average overall miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency 11822.799097 # average overall mshr miss latency -system.cpu3.icache.demand_hits 20095 # number of demand (read+write) hits -system.cpu3.icache.demand_miss_latency 6936500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_rate 0.023187 # miss rate for demand accesses -system.cpu3.icache.demand_misses 477 # number of demand (read+write) misses -system.cpu3.icache.demand_mshr_hits 34 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_miss_latency 5237500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_rate 0.021534 # mshr miss rate for demand accesses +system.cpu3.icache.demand_accesses 26017 # number of demand (read+write) accesses +system.cpu3.icache.demand_avg_miss_latency 14208.939709 # average overall miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency 11549.661400 # average overall mshr miss latency +system.cpu3.icache.demand_hits 25536 # number of demand (read+write) hits +system.cpu3.icache.demand_miss_latency 6834500 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_rate 0.018488 # miss rate for demand accesses +system.cpu3.icache.demand_misses 481 # number of demand (read+write) misses +system.cpu3.icache.demand_mshr_hits 38 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_miss_latency 5116500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_rate 0.017027 # mshr miss rate for demand accesses system.cpu3.icache.demand_mshr_misses 443 # number of demand (read+write) MSHR misses system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.icache.occ_%::0 0.172973 # Average percentage of cache occupancy -system.cpu3.icache.occ_blocks::0 88.562021 # Average occupied blocks per context -system.cpu3.icache.overall_accesses 20572 # number of overall (read+write) accesses -system.cpu3.icache.overall_avg_miss_latency 14541.928721 # average overall miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency 11822.799097 # average overall mshr miss latency +system.cpu3.icache.occ_%::0 0.166919 # Average percentage of cache occupancy +system.cpu3.icache.occ_blocks::0 85.462768 # Average occupied blocks per context +system.cpu3.icache.overall_accesses 26017 # number of overall (read+write) accesses +system.cpu3.icache.overall_avg_miss_latency 14208.939709 # average overall miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency 11549.661400 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.icache.overall_hits 20095 # number of overall hits -system.cpu3.icache.overall_miss_latency 6936500 # number of overall miss cycles -system.cpu3.icache.overall_miss_rate 0.023187 # miss rate for overall accesses -system.cpu3.icache.overall_misses 477 # number of overall misses -system.cpu3.icache.overall_mshr_hits 34 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_miss_latency 5237500 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_rate 0.021534 # mshr miss rate for overall accesses +system.cpu3.icache.overall_hits 25536 # number of overall hits +system.cpu3.icache.overall_miss_latency 6834500 # number of overall miss cycles +system.cpu3.icache.overall_miss_rate 0.018488 # miss rate for overall accesses +system.cpu3.icache.overall_misses 481 # number of overall misses +system.cpu3.icache.overall_mshr_hits 38 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_miss_latency 5116500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_rate 0.017027 # mshr miss rate for overall accesses system.cpu3.icache.overall_mshr_misses 443 # number of overall MSHR misses system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu3.icache.replacements 331 # number of replacements system.cpu3.icache.sampled_refs 443 # Sample count of references to valid blocks. system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.icache.tagsinuse 88.562021 # Cycle average of tags in use -system.cpu3.icache.total_refs 20095 # Total number of references to valid blocks. +system.cpu3.icache.tagsinuse 85.462768 # Cycle average of tags in use +system.cpu3.icache.total_refs 25536 # Total number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.icache.writebacks 0 # number of writebacks -system.cpu3.idleCycles 3074 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.iew.EXEC:branches 53119 # Number of branches executed -system.cpu3.iew.EXEC:nop 44175 # number of nop insts executed -system.cpu3.iew.EXEC:rate 1.285981 # Inst execution rate -system.cpu3.iew.EXEC:refs 128575 # number of memory reference insts executed -system.cpu3.iew.EXEC:stores 41051 # Number of stores executed +system.cpu3.idleCycles 3421 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.iew.EXEC:branches 43744 # Number of branches executed +system.cpu3.iew.EXEC:nop 34814 # number of nop insts executed +system.cpu3.iew.EXEC:rate 1.024765 # Inst execution rate +system.cpu3.iew.EXEC:refs 95207 # number of memory reference insts executed +system.cpu3.iew.EXEC:stores 29059 # Number of stores executed system.cpu3.iew.EXEC:swp 0 # number of swp insts executed -system.cpu3.iew.WB:consumers 148618 # num instructions consuming a value -system.cpu3.iew.WB:count 256019 # cumulative count of insts written-back -system.cpu3.iew.WB:fanout 0.975407 # average fanout of values written-back +system.cpu3.iew.WB:consumers 115240 # num instructions consuming a value +system.cpu3.iew.WB:count 203888 # cumulative count of insts written-back +system.cpu3.iew.WB:fanout 0.968327 # average fanout of values written-back system.cpu3.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu3.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.iew.WB:producers 144963 # num instructions producing a value -system.cpu3.iew.WB:rate 1.284140 # insts written-back per cycle -system.cpu3.iew.WB:sent 256153 # cumulative count of insts sent to commit -system.cpu3.iew.branchMispredicts 1196 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewBlockCycles 1671 # Number of cycles IEW is blocking -system.cpu3.iew.iewDispLoadInsts 88323 # Number of dispatched load instructions -system.cpu3.iew.iewDispNonSpecInsts 935 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewDispSquashedInsts 564 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispStoreInsts 41481 # Number of dispatched store instructions -system.cpu3.iew.iewDispatchedInsts 304435 # Number of instructions dispatched to IQ -system.cpu3.iew.iewExecLoadInsts 87524 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 961 # Number of squashed instructions skipped in execute -system.cpu3.iew.iewExecutedInsts 256386 # Number of executed instructions -system.cpu3.iew.iewIQFullEvents 55 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.WB:producers 111590 # num instructions producing a value +system.cpu3.iew.WB:rate 1.022969 # insts written-back per cycle +system.cpu3.iew.WB:sent 204019 # cumulative count of insts sent to commit +system.cpu3.iew.branchMispredicts 1193 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewBlockCycles 1619 # Number of cycles IEW is blocking +system.cpu3.iew.iewDispLoadInsts 66949 # Number of dispatched load instructions +system.cpu3.iew.iewDispNonSpecInsts 934 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewDispSquashedInsts 572 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispStoreInsts 29464 # Number of dispatched store instructions +system.cpu3.iew.iewDispatchedInsts 242942 # Number of instructions dispatched to IQ +system.cpu3.iew.iewExecLoadInsts 66148 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 960 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewExecutedInsts 204246 # Number of executed instructions +system.cpu3.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.iewSquashCycles 1792 # Number of cycles IEW is squashing -system.cpu3.iew.iewUnblockCycles 64 # Number of cycles IEW is unblocking +system.cpu3.iew.iewSquashCycles 1781 # Number of cycles IEW is squashing +system.cpu3.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking system.cpu3.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu3.iew.lsq.thread.0.forwLoads 36829 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread.0.forwLoads 24834 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu3.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu3.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu3.iew.lsq.thread.0.memOrderViolation 34 # Number of memory ordering violations +system.cpu3.iew.lsq.thread.0.memOrderViolation 29 # Number of memory ordering violations system.cpu3.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread.0.squashedLoads 1546 # Number of loads squashed -system.cpu3.iew.lsq.thread.0.squashedStores 782 # Number of stores squashed -system.cpu3.iew.memOrderViolationEvents 34 # Number of memory order violations -system.cpu3.iew.predictedNotTakenIncorrect 194 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.predictedTakenIncorrect 1002 # Number of branches that were predicted taken incorrectly -system.cpu3.int_regfile_reads 443221 # number of integer regfile reads -system.cpu3.int_regfile_writes 205359 # number of integer regfile writes -system.cpu3.ipc 1.237689 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.237689 # IPC: Total IPC of All Threads +system.cpu3.iew.lsq.thread.0.squashedLoads 1517 # Number of loads squashed +system.cpu3.iew.lsq.thread.0.squashedStores 742 # Number of stores squashed +system.cpu3.iew.memOrderViolationEvents 29 # Number of memory order violations +system.cpu3.iew.predictedNotTakenIncorrect 182 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.predictedTakenIncorrect 1011 # Number of branches that were predicted taken incorrectly +system.cpu3.int_regfile_reads 343072 # number of integer regfile reads +system.cpu3.int_regfile_writes 159978 # number of integer regfile writes +system.cpu3.ipc 0.963785 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.963785 # IPC: Total IPC of All Threads system.cpu3.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::IntAlu 122656 47.66% 47.66% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::IntMult 0 0.00% 47.66% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 47.66% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 47.66% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 47.66% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 47.66% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 47.66% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 47.66% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 47.66% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 47.66% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 47.66% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 47.66% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 47.66% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 47.66% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 47.66% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 47.66% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 47.66% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 47.66% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 47.66% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 47.66% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 47.66% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 47.66% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 47.66% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 47.66% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 47.66% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 47.66% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 47.66% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 47.66% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 47.66% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::MemRead 93608 36.37% 84.04% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::MemWrite 41083 15.96% 100.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::IntAlu 101269 49.35% 49.35% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::IntMult 0 0.00% 49.35% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 49.35% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 49.35% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 49.35% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 49.35% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 49.35% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 49.35% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 49.35% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 49.35% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 49.35% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 49.35% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 49.35% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 49.35% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 49.35% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 49.35% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 49.35% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 49.35% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 49.35% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 49.35% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 49.35% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 49.35% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 49.35% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 49.35% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 49.35% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 49.35% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 49.35% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 49.35% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 49.35% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::MemRead 74848 36.47% 85.82% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::MemWrite 29089 14.18% 100.00% # Type of FU issued system.cpu3.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::total 257347 # Type of FU issued -system.cpu3.iq.ISSUE:fu_busy_cnt 199 # FU busy when requested -system.cpu3.iq.ISSUE:fu_busy_rate 0.000773 # FU busy rate (busy events/executed inst) +system.cpu3.iq.ISSUE:FU_type_0::total 205206 # Type of FU issued +system.cpu3.iq.ISSUE:fu_busy_cnt 188 # FU busy when requested +system.cpu3.iq.ISSUE:fu_busy_rate 0.000916 # FU busy rate (busy events/executed inst) system.cpu3.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::IntAlu 11 5.53% 5.53% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::IntMult 0 0.00% 5.53% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::IntDiv 0 0.00% 5.53% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::FloatAdd 0 0.00% 5.53% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::FloatCmp 0 0.00% 5.53% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.53% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.53% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.53% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.53% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdAdd 0 0.00% 5.53% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 5.53% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdAlu 0 0.00% 5.53% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdCmp 0 0.00% 5.53% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdCvt 0 0.00% 5.53% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdMisc 0 0.00% 5.53% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdMult 0 0.00% 5.53% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 5.53% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdShift 0 0.00% 5.53% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 5.53% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 5.53% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 5.53% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 5.53% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 5.53% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 5.53% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 5.53% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 5.53% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 5.53% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 5.53% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 5.53% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::MemRead 57 28.64% 34.17% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::MemWrite 131 65.83% 100.00% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::IntAlu 11 5.85% 5.85% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::IntMult 0 0.00% 5.85% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::IntDiv 0 0.00% 5.85% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatAdd 0 0.00% 5.85% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatCmp 0 0.00% 5.85% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.85% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.85% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.85% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.85% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdAdd 0 0.00% 5.85% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 5.85% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdAlu 0 0.00% 5.85% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdCmp 0 0.00% 5.85% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdCvt 0 0.00% 5.85% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdMisc 0 0.00% 5.85% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdMult 0 0.00% 5.85% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 5.85% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdShift 0 0.00% 5.85% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 5.85% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 5.85% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 5.85% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 5.85% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 5.85% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 5.85% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 5.85% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 5.85% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 5.85% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 5.85% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 5.85% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::MemRead 46 24.47% 30.32% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::MemWrite 131 69.68% 100.00% # attempts to use FU when none available system.cpu3.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu3.iq.ISSUE:issued_per_cycle::samples 196296 # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::mean 1.311015 # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::stdev 1.285531 # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::samples 195889 # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::mean 1.047563 # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::stdev 1.235617 # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::0 79991 40.75% 40.75% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::1 27327 13.92% 54.67% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::2 43412 22.12% 76.79% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::3 41220 21.00% 97.79% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::4 2543 1.30% 99.08% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::5 1556 0.79% 99.87% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::6 155 0.08% 99.95% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::0 95806 48.91% 48.91% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::1 35106 17.92% 66.83% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::2 31374 16.02% 82.85% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::3 29208 14.91% 97.76% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::4 2591 1.32% 99.08% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::5 1562 0.80% 99.88% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::6 150 0.08% 99.95% # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::7 82 0.04% 99.99% # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::8 10 0.01% 100.00% # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::total 196296 # Number of insts issued each cycle -system.cpu3.iq.ISSUE:rate 1.290801 # Inst issue rate +system.cpu3.iq.ISSUE:issued_per_cycle::total 195889 # Number of insts issued each cycle +system.cpu3.iq.ISSUE:rate 1.029582 # Inst issue rate system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes -system.cpu3.iq.int_alu_accesses 257546 # Number of integer alu accesses -system.cpu3.iq.int_inst_queue_reads 711191 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_wakeup_accesses 256019 # Number of integer instruction queue wakeup accesses -system.cpu3.iq.int_inst_queue_writes 266954 # Number of integer instruction queue writes -system.cpu3.iq.iqInstsAdded 253019 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqInstsIssued 257347 # Number of instructions issued -system.cpu3.iq.iqNonSpecInstsAdded 7241 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqSquashedInstsExamined 6661 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.int_alu_accesses 205394 # Number of integer alu accesses +system.cpu3.iq.int_inst_queue_reads 606491 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_wakeup_accesses 203888 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.int_inst_queue_writes 214747 # Number of integer instruction queue writes +system.cpu3.iq.iqInstsAdded 198217 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqInstsIssued 205206 # Number of instructions issued +system.cpu3.iq.iqNonSpecInstsAdded 9911 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqSquashedInstsExamined 6590 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu3.iq.iqSquashedInstsIssued 2 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedNonSpecRemoved 626 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.iqSquashedOperandsExamined 6379 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.memDep0.conflictingLoads 43278 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 36990 # Number of conflicting stores. -system.cpu3.memDep0.insertedLoads 88323 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 41481 # Number of stores inserted to the mem dependence unit. -system.cpu3.misc_regfile_reads 130106 # number of misc regfile reads +system.cpu3.iq.iqSquashedNonSpecRemoved 673 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.iqSquashedOperandsExamined 6253 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.memDep0.conflictingLoads 33826 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 24974 # Number of conflicting stores. +system.cpu3.memDep0.insertedLoads 66949 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 29464 # Number of stores inserted to the mem dependence unit. +system.cpu3.misc_regfile_reads 96736 # number of misc regfile reads system.cpu3.misc_regfile_writes 646 # number of misc regfile writes -system.cpu3.numCycles 199370 # number of cpu cycles simulated +system.cpu3.numCycles 199310 # number of cpu cycles simulated system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu3.rename.RENAME:BlockCycles 7226 # Number of cycles rename is blocking -system.cpu3.rename.RENAME:CommittedMaps 202775 # Number of HB maps that are committed -system.cpu3.rename.RENAME:IQFullEvents 58 # Number of times rename has blocked due to IQ full -system.cpu3.rename.RENAME:IdleCycles 55235 # Number of cycles rename is idle -system.cpu3.rename.RENAME:LSQFullEvents 44 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RENAME:RenameLookups 585183 # Number of register rename lookups that rename has made -system.cpu3.rename.RENAME:RenamedInsts 306652 # Number of instructions processed by rename -system.cpu3.rename.RENAME:RenamedOperands 211061 # Number of destination operands rename has renamed -system.cpu3.rename.RENAME:RunCycles 111693 # Number of cycles rename is running -system.cpu3.rename.RENAME:SquashCycles 1792 # Number of cycles rename is squashing -system.cpu3.rename.RENAME:UnblockCycles 593 # Number of cycles rename is unblocking -system.cpu3.rename.RENAME:UndoneMaps 8286 # Number of HB maps that are undone due to squashing -system.cpu3.rename.RENAME:int_rename_lookups 585183 # Number of integer rename lookups -system.cpu3.rename.RENAME:serializeStallCycles 13124 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RENAME:serializingInsts 957 # count of serializing insts renamed -system.cpu3.rename.RENAME:skidInsts 2808 # count of insts added to the skid buffer +system.cpu3.rename.RENAME:BlockCycles 9536 # Number of cycles rename is blocking +system.cpu3.rename.RENAME:CommittedMaps 157468 # Number of HB maps that are committed +system.cpu3.rename.RENAME:IQFullEvents 52 # Number of times rename has blocked due to IQ full +system.cpu3.rename.RENAME:IdleCycles 68516 # Number of cycles rename is idle +system.cpu3.rename.RENAME:LSQFullEvents 39 # Number of times rename has blocked due to LSQ full +system.cpu3.rename.RENAME:RenameLookups 451555 # Number of register rename lookups that rename has made +system.cpu3.rename.RENAME:RenamedInsts 245166 # Number of instructions processed by rename +system.cpu3.rename.RENAME:RenamedOperands 165603 # Number of destination operands rename has renamed +system.cpu3.rename.RENAME:RunCycles 95731 # Number of cycles rename is running +system.cpu3.rename.RENAME:SquashCycles 1781 # Number of cycles rename is squashing +system.cpu3.rename.RENAME:UnblockCycles 570 # Number of cycles rename is unblocking +system.cpu3.rename.RENAME:UndoneMaps 8135 # Number of HB maps that are undone due to squashing +system.cpu3.rename.RENAME:int_rename_lookups 451555 # Number of integer rename lookups +system.cpu3.rename.RENAME:serializeStallCycles 13138 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RENAME:serializingInsts 958 # count of serializing insts renamed +system.cpu3.rename.RENAME:skidInsts 2735 # count of insts added to the skid buffer system.cpu3.rename.RENAME:tempSerializingInsts 1009 # count of temporary serializing insts renamed -system.cpu3.rob.rob_reads 491204 # The number of ROB reads -system.cpu3.rob.rob_writes 610604 # The number of ROB writes -system.cpu3.timesIdled 290 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.rob.rob_reads 429330 # The number of ROB reads +system.cpu3.rob.rob_writes 487605 # The number of ROB writes +system.cpu3.timesIdled 294 # Number of times that the entire CPU went into an idle state and unscheduled itself system.l2c.ReadExReq_accesses::0 94 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::1 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::2 13 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::3 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 73159.574468 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 573083.333333 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::2 529000 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::3 573083.333333 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 1748326.241135 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40290.076336 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 6877000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_avg_miss_latency::0 73164.893617 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 573125 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::2 529038.461538 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::3 573125 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 1748453.355155 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40293.893130 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 6877500 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses @@ -1607,7 +1607,7 @@ system.l2c.ReadExReq_misses::1 12 # nu system.l2c.ReadExReq_misses::2 13 # number of ReadExReq misses system.l2c.ReadExReq_misses::3 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 5278000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5278500 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_rate::0 1.393617 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 10.916667 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 10.076923 # mshr miss rate for ReadExReq accesses @@ -1615,49 +1615,49 @@ system.l2c.ReadExReq_mshr_miss_rate::3 10.916667 # ms system.l2c.ReadExReq_mshr_miss_rate::total 33.303873 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_misses 131 # number of ReadExReq MSHR misses system.l2c.ReadReq_accesses::0 689 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 457 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::2 450 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 453 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::2 454 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::3 456 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 2052 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 63653.674833 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 2381708.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::2 348542.682927 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::3 4082928.571429 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 6876833.262522 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40001.841621 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_miss_latency::0 63645.879733 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 1905133.333333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::2 348500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::3 7144250 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 9461529.213066 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_hits::0 240 # number of ReadReq hits -system.l2c.ReadReq_hits::1 445 # number of ReadReq hits -system.l2c.ReadReq_hits::2 368 # number of ReadReq hits -system.l2c.ReadReq_hits::3 449 # number of ReadReq hits +system.l2c.ReadReq_hits::1 438 # number of ReadReq hits +system.l2c.ReadReq_hits::2 372 # number of ReadReq hits +system.l2c.ReadReq_hits::3 452 # number of ReadReq hits system.l2c.ReadReq_hits::total 1502 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 28580500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency 28577000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_rate::0 0.651669 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.026258 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::2 0.182222 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::3 0.015351 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.875500 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.033113 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::2 0.180617 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::3 0.008772 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.874170 # miss rate for ReadReq accesses system.l2c.ReadReq_misses::0 449 # number of ReadReq misses -system.l2c.ReadReq_misses::1 12 # number of ReadReq misses +system.l2c.ReadReq_misses::1 15 # number of ReadReq misses system.l2c.ReadReq_misses::2 82 # number of ReadReq misses -system.l2c.ReadReq_misses::3 7 # number of ReadReq misses +system.l2c.ReadReq_misses::3 4 # number of ReadReq misses system.l2c.ReadReq_misses::total 550 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 21721000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency 21720000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_rate::0 0.788099 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 1.188184 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::2 1.206667 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 1.198675 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::2 1.196035 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::3 1.190789 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 4.373739 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 4.373599 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_misses 543 # number of ReadReq MSHR misses system.l2c.UpgradeReq_accesses::0 29 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 21 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 24 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::2 23 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::3 24 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::3 21 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 97 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_avg_miss_latency::0 6000 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 7428.571429 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 6500 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 6782.608696 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::3 6500 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::3 7428.571429 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total 26711.180124 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_hits::0 3 # number of UpgradeReq hits @@ -1669,15 +1669,15 @@ system.l2c.UpgradeReq_miss_rate::2 1 # mi system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 3.896552 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_misses::0 26 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 21 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 24 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::2 23 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::3 24 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::3 21 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 94 # number of UpgradeReq misses system.l2c.UpgradeReq_mshr_miss_latency 3760000 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate::0 3.241379 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 4.476190 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 3.916667 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::2 4.086957 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::3 3.916667 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::3 4.476190 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 15.721193 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_misses 94 # number of UpgradeReq MSHR misses system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses) @@ -1693,95 +1693,95 @@ system.l2c.blocked_cycles::no_mshrs 0 # nu system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed system.l2c.demand_accesses::0 783 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 469 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 463 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 465 # number of demand (read+write) accesses +system.l2c.demand_accesses::2 467 # number of demand (read+write) accesses system.l2c.demand_accesses::3 468 # number of demand (read+write) accesses system.l2c.demand_accesses::total 2183 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 65299.263352 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 1477395.833333 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 373236.842105 # average overall miss latency -system.l2c.demand_avg_miss_latency::3 1866184.210526 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 3782116.149317 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40057.863501 # average overall mshr miss latency +system.l2c.demand_avg_miss_latency::0 65293.738490 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 1313129.629630 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 373205.263158 # average overall miss latency +system.l2c.demand_avg_miss_latency::3 2215906.250000 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 3967534.881277 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40057.121662 # average overall mshr miss latency system.l2c.demand_hits::0 240 # number of demand (read+write) hits -system.l2c.demand_hits::1 445 # number of demand (read+write) hits -system.l2c.demand_hits::2 368 # number of demand (read+write) hits -system.l2c.demand_hits::3 449 # number of demand (read+write) hits +system.l2c.demand_hits::1 438 # number of demand (read+write) hits +system.l2c.demand_hits::2 372 # number of demand (read+write) hits +system.l2c.demand_hits::3 452 # number of demand (read+write) hits system.l2c.demand_hits::total 1502 # number of demand (read+write) hits -system.l2c.demand_miss_latency 35457500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency 35454500 # number of demand (read+write) miss cycles system.l2c.demand_miss_rate::0 0.693487 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.051173 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 0.205184 # miss rate for demand accesses -system.l2c.demand_miss_rate::3 0.040598 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.990441 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.058065 # miss rate for demand accesses +system.l2c.demand_miss_rate::2 0.203426 # miss rate for demand accesses +system.l2c.demand_miss_rate::3 0.034188 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.989165 # miss rate for demand accesses system.l2c.demand_misses::0 543 # number of demand (read+write) misses -system.l2c.demand_misses::1 24 # number of demand (read+write) misses +system.l2c.demand_misses::1 27 # number of demand (read+write) misses system.l2c.demand_misses::2 95 # number of demand (read+write) misses -system.l2c.demand_misses::3 19 # number of demand (read+write) misses +system.l2c.demand_misses::3 16 # number of demand (read+write) misses system.l2c.demand_misses::total 681 # number of demand (read+write) misses system.l2c.demand_mshr_hits 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 26999000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency 26998500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_rate::0 0.860792 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.437100 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::2 1.455724 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.449462 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::2 1.443255 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::3 1.440171 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 5.193787 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 5.193680 # mshr miss rate for demand accesses system.l2c.demand_mshr_misses 674 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.005561 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.000141 # Average percentage of cache occupancy +system.l2c.occ_%::0 0.005562 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.000156 # Average percentage of cache occupancy system.l2c.occ_%::2 0.000959 # Average percentage of cache occupancy -system.l2c.occ_%::3 0.000053 # Average percentage of cache occupancy +system.l2c.occ_%::3 0.000038 # Average percentage of cache occupancy system.l2c.occ_%::4 0.000079 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 364.466495 # Average occupied blocks per context -system.l2c.occ_blocks::1 9.271638 # Average occupied blocks per context -system.l2c.occ_blocks::2 62.868915 # Average occupied blocks per context -system.l2c.occ_blocks::3 3.440920 # Average occupied blocks per context -system.l2c.occ_blocks::4 5.201108 # Average occupied blocks per context +system.l2c.occ_blocks::0 364.492731 # Average occupied blocks per context +system.l2c.occ_blocks::1 10.237276 # Average occupied blocks per context +system.l2c.occ_blocks::2 62.878855 # Average occupied blocks per context +system.l2c.occ_blocks::3 2.477387 # Average occupied blocks per context +system.l2c.occ_blocks::4 5.202251 # Average occupied blocks per context system.l2c.overall_accesses::0 783 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 469 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 463 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 465 # number of overall (read+write) accesses +system.l2c.overall_accesses::2 467 # number of overall (read+write) accesses system.l2c.overall_accesses::3 468 # number of overall (read+write) accesses system.l2c.overall_accesses::total 2183 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 65299.263352 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 1477395.833333 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 373236.842105 # average overall miss latency -system.l2c.overall_avg_miss_latency::3 1866184.210526 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 3782116.149317 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40057.863501 # average overall mshr miss latency +system.l2c.overall_avg_miss_latency::0 65293.738490 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 1313129.629630 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 373205.263158 # average overall miss latency +system.l2c.overall_avg_miss_latency::3 2215906.250000 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 3967534.881277 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40057.121662 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.l2c.overall_hits::0 240 # number of overall hits -system.l2c.overall_hits::1 445 # number of overall hits -system.l2c.overall_hits::2 368 # number of overall hits -system.l2c.overall_hits::3 449 # number of overall hits +system.l2c.overall_hits::1 438 # number of overall hits +system.l2c.overall_hits::2 372 # number of overall hits +system.l2c.overall_hits::3 452 # number of overall hits system.l2c.overall_hits::total 1502 # number of overall hits -system.l2c.overall_miss_latency 35457500 # number of overall miss cycles +system.l2c.overall_miss_latency 35454500 # number of overall miss cycles system.l2c.overall_miss_rate::0 0.693487 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.051173 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 0.205184 # miss rate for overall accesses -system.l2c.overall_miss_rate::3 0.040598 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.990441 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.058065 # miss rate for overall accesses +system.l2c.overall_miss_rate::2 0.203426 # miss rate for overall accesses +system.l2c.overall_miss_rate::3 0.034188 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.989165 # miss rate for overall accesses system.l2c.overall_misses::0 543 # number of overall misses -system.l2c.overall_misses::1 24 # number of overall misses +system.l2c.overall_misses::1 27 # number of overall misses system.l2c.overall_misses::2 95 # number of overall misses -system.l2c.overall_misses::3 19 # number of overall misses +system.l2c.overall_misses::3 16 # number of overall misses system.l2c.overall_misses::total 681 # number of overall misses system.l2c.overall_mshr_hits 7 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 26999000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency 26998500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_rate::0 0.860792 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.437100 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::2 1.455724 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.449462 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::2 1.443255 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::3 1.440171 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 5.193787 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 5.193680 # mshr miss rate for overall accesses system.l2c.overall_mshr_misses 674 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.replacements 0 # number of replacements system.l2c.sampled_refs 545 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 445.249076 # Cycle average of tags in use +system.l2c.tagsinuse 445.288501 # Cycle average of tags in use system.l2c.total_refs 1499 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.writebacks 0 # number of writebacks |