diff options
| author | Steve Reinhardt <stever@gmail.com> | 2008-02-16 14:58:37 -0500 |
|---|---|---|
| committer | Steve Reinhardt <stever@gmail.com> | 2008-02-16 14:58:37 -0500 |
| commit | 3204f968091d32846a59c0666157c6c8946842d1 (patch) | |
| tree | 497c84fa2634b7bcd6c0a5ab03e6d602c264fd07 /tests/quick | |
| parent | 4597a71cef808969c442fca73ae662efe75550d7 (diff) | |
| download | gem5-3204f968091d32846a59c0666157c6c8946842d1.tar.xz | |
Update stats for new writeback behavior.
--HG--
extra : convert_revision : 3e932b5773f5fb9a119822d5bf497f61e9409c14
Diffstat (limited to 'tests/quick')
15 files changed, 1454 insertions, 1471 deletions
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt index 079bec809..df1b8566f 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt @@ -1,44 +1,44 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2182924 # Simulator instruction rate (inst/s) -host_mem_usage 325992 # Number of bytes of host memory used -host_seconds 28.91 # Real time elapsed on the host -host_tick_rate 64688316336 # Simulator tick rate (ticks/s) +host_inst_rate 1110947 # Simulator instruction rate (inst/s) +host_mem_usage 261416 # Number of bytes of host memory used +host_seconds 56.81 # Real time elapsed on the host +host_tick_rate 32921847339 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 63114079 # Number of instructions simulated +sim_insts 63114046 # Number of instructions simulated sim_seconds 1.870335 # Number of seconds simulated -sim_ticks 1870335101500 # Number of ticks simulated +sim_ticks 1870335151500 # Number of ticks simulated system.cpu0.dcache.LoadLockedReq_accesses 188283 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_hits 172122 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_miss_rate 0.085834 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_misses 16161 # number of LoadLockedReq misses -system.cpu0.dcache.ReadReq_accesses 8975658 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_hits 7292076 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_rate 0.187572 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 1683582 # number of ReadReq misses +system.cpu0.dcache.ReadReq_accesses 8975647 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_hits 7292074 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_rate 0.187571 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 1683573 # number of ReadReq misses system.cpu0.dcache.StoreCondReq_accesses 187323 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_hits 159819 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_rate 0.146827 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_misses 27504 # number of StoreCondReq misses -system.cpu0.dcache.WriteReq_accesses 5746073 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_hits 5372266 # number of WriteReq hits +system.cpu0.dcache.StoreCondReq_hits 159821 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_rate 0.146816 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses 27502 # number of StoreCondReq misses +system.cpu0.dcache.WriteReq_accesses 5746071 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_hits 5372265 # number of WriteReq hits system.cpu0.dcache.WriteReq_miss_rate 0.065054 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 373807 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses 373806 # number of WriteReq misses system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 6.625567 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 6.625595 # Average number of references to valid blocks. system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 14721731 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses 14721718 # number of demand (read+write) accesses system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu0.dcache.demand_hits 12664342 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits 12664339 # number of demand (read+write) hits system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.139752 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 2057389 # number of demand (read+write) misses +system.cpu0.dcache.demand_miss_rate 0.139751 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 2057379 # number of demand (read+write) misses system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -46,14 +46,14 @@ system.cpu0.dcache.demand_mshr_misses 0 # nu system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.overall_accesses 14721731 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses 14721718 # number of overall (read+write) accesses system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 12664342 # number of overall hits +system.cpu0.dcache.overall_hits 12664339 # number of overall hits system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.139752 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 2057389 # number of overall misses +system.cpu0.dcache.overall_miss_rate 0.139751 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 2057379 # number of overall misses system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -69,44 +69,44 @@ system.cpu0.dcache.prefetcher.num_hwpf_issued 0 system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.dcache.replacements 1978980 # number of replacements -system.cpu0.dcache.sampled_refs 1979492 # Sample count of references to valid blocks. +system.cpu0.dcache.replacements 1978971 # number of replacements +system.cpu0.dcache.sampled_refs 1979483 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 504.827576 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13115256 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 504.827578 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13115252 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 396796 # number of writebacks +system.cpu0.dcache.writebacks 396793 # number of writebacks system.cpu0.dtb.accesses 698037 # DTB accesses system.cpu0.dtb.acv 251 # DTB access violations -system.cpu0.dtb.hits 15082969 # DTB hits +system.cpu0.dtb.hits 15082956 # DTB hits system.cpu0.dtb.misses 7805 # DTB misses system.cpu0.dtb.read_accesses 508987 # DTB read accesses system.cpu0.dtb.read_acv 152 # DTB read access violations -system.cpu0.dtb.read_hits 9148390 # DTB read hits +system.cpu0.dtb.read_hits 9148379 # DTB read hits system.cpu0.dtb.read_misses 7079 # DTB read misses system.cpu0.dtb.write_accesses 189050 # DTB write accesses system.cpu0.dtb.write_acv 99 # DTB write access violations -system.cpu0.dtb.write_hits 5934579 # DTB write hits +system.cpu0.dtb.write_hits 5934577 # DTB write hits system.cpu0.dtb.write_misses 726 # DTB write misses -system.cpu0.icache.ReadReq_accesses 57190172 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_hits 56305300 # number of ReadReq hits +system.cpu0.icache.ReadReq_accesses 57190139 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_hits 56305276 # number of ReadReq hits system.cpu0.icache.ReadReq_miss_rate 0.015472 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses 884872 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses 884863 # number of ReadReq misses system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 63.637052 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 63.637672 # Average number of references to valid blocks. system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 57190172 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses 57190139 # number of demand (read+write) accesses system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency system.cpu0.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu0.icache.demand_hits 56305300 # number of demand (read+write) hits +system.cpu0.icache.demand_hits 56305276 # number of demand (read+write) hits system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu0.icache.demand_miss_rate 0.015472 # miss rate for demand accesses -system.cpu0.icache.demand_misses 884872 # number of demand (read+write) misses +system.cpu0.icache.demand_misses 884863 # number of demand (read+write) misses system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -114,14 +114,14 @@ system.cpu0.icache.demand_mshr_misses 0 # nu system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.overall_accesses 57190172 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses 57190139 # number of overall (read+write) accesses system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu0.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 56305300 # number of overall hits +system.cpu0.icache.overall_hits 56305276 # number of overall hits system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles system.cpu0.icache.overall_miss_rate 0.015472 # miss rate for overall accesses -system.cpu0.icache.overall_misses 884872 # number of overall misses +system.cpu0.icache.overall_misses 884863 # number of overall misses system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -137,19 +137,19 @@ system.cpu0.icache.prefetcher.num_hwpf_issued 0 system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.icache.replacements 884276 # number of replacements -system.cpu0.icache.sampled_refs 884788 # Sample count of references to valid blocks. +system.cpu0.icache.replacements 884267 # number of replacements +system.cpu0.icache.sampled_refs 884779 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu0.icache.tagsinuse 511.244752 # Cycle average of tags in use -system.cpu0.icache.total_refs 56305300 # Total number of references to valid blocks. +system.cpu0.icache.total_refs 56305276 # Total number of references to valid blocks. system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles -system.cpu0.itb.accesses 3858835 # ITB accesses +system.cpu0.itb.accesses 3858846 # ITB accesses system.cpu0.itb.acv 127 # ITB acv -system.cpu0.itb.hits 3855350 # ITB hits +system.cpu0.itb.hits 3855361 # ITB hits system.cpu0.itb.misses 3485 # ITB misses -system.cpu0.kern.callpal 183272 # number of callpals executed +system.cpu0.kern.callpal 183273 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal_wripir 110 0.06% 0.06% # number of callpals executed system.cpu0.kern.callpal_wrmces 1 0.00% 0.06% # number of callpals executed @@ -158,7 +158,7 @@ system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.06% # nu system.cpu0.kern.callpal_swpctx 3761 2.05% 2.11% # number of callpals executed system.cpu0.kern.callpal_tbi 38 0.02% 2.14% # number of callpals executed system.cpu0.kern.callpal_wrent 7 0.00% 2.14% # number of callpals executed -system.cpu0.kern.callpal_swpipl 168017 91.68% 93.82% # number of callpals executed +system.cpu0.kern.callpal_swpipl 168018 91.68% 93.82% # number of callpals executed system.cpu0.kern.callpal_rdps 6150 3.36% 97.17% # number of callpals executed system.cpu0.kern.callpal_wrkgp 1 0.00% 97.17% # number of callpals executed system.cpu0.kern.callpal_wrusp 3 0.00% 97.17% # number of callpals executed @@ -168,43 +168,43 @@ system.cpu0.kern.callpal_rti 4673 2.55% 99.73% # nu system.cpu0.kern.callpal_callsys 357 0.19% 99.92% # number of callpals executed system.cpu0.kern.callpal_imb 142 0.08% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 197101 # number of hwrei instructions executed +system.cpu0.kern.inst.hwrei 197102 # number of hwrei instructions executed system.cpu0.kern.inst.quiesce 6167 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 174850 # number of times we switched to this ipl +system.cpu0.kern.ipl_count 174851 # number of times we switched to this ipl system.cpu0.kern.ipl_count_0 70996 40.60% 40.60% # number of times we switched to this ipl system.cpu0.kern.ipl_count_21 243 0.14% 40.74% # number of times we switched to this ipl system.cpu0.kern.ipl_count_22 1908 1.09% 41.83% # number of times we switched to this ipl system.cpu0.kern.ipl_count_30 8 0.00% 41.84% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 101695 58.16% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_31 101696 58.16% 100.00% # number of times we switched to this ipl system.cpu0.kern.ipl_good 141409 # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_0 69629 49.24% 49.24% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_31 69621 49.23% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 1870334894000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 1853125122500 99.08% 99.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks 1870334944000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 1853125190500 99.08% 99.08% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks_21 20110000 0.00% 99.08% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks_22 82044000 0.00% 99.09% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks_30 949500 0.00% 99.09% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 17106668000 0.91% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 17106650000 0.91% 100.00% # number of cycles we spent at this ipl system.cpu0.kern.ipl_used_0 0.980745 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.684606 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1155 -system.cpu0.kern.mode_good_user 1156 +system.cpu0.kern.ipl_used_31 0.684599 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1156 +system.cpu0.kern.mode_good_user 1157 system.cpu0.kern.mode_good_idle 0 system.cpu0.kern.mode_switch_kernel 7090 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1156 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1157 # number of protection mode switches system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches system.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.162906 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.163047 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 1869377894000 99.95% 99.95% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 956999000 0.05% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_kernel 1869377939000 99.95% 99.95% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 957004000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3762 # number of times the context was actually changed system.cpu0.kern.syscall 226 # number of syscalls executed @@ -239,9 +239,9 @@ system.cpu0.kern.syscall_132 2 0.88% 98.23% # nu system.cpu0.kern.syscall_144 2 0.88% 99.12% # number of syscalls executed system.cpu0.kern.syscall_147 2 0.88% 100.00% # number of syscalls executed system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles -system.cpu0.numCycles 3740670091 # number of cpu cycles simulated -system.cpu0.num_insts 57182116 # Number of instructions executed -system.cpu0.num_refs 15322419 # Number of memory references +system.cpu0.numCycles 3740670191 # number of cpu cycles simulated +system.cpu0.num_insts 57182083 # Number of instructions executed +system.cpu0.num_refs 15322406 # Number of memory references system.cpu1.dcache.LoadLockedReq_accesses 16418 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_hits 15129 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_miss_rate 0.078511 # miss rate for LoadLockedReq accesses @@ -374,9 +374,9 @@ system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu1.icache.replacements 103097 # number of replacements system.cpu1.icache.sampled_refs 103609 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 427.126314 # Cycle average of tags in use +system.cpu1.icache.tagsinuse 427.126316 # Cycle average of tags in use system.cpu1.icache.total_refs 5832135 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1868932669000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.warmup_cycle 1868932699000 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles system.cpu1.itb.accesses 1469938 # ITB accesses @@ -414,8 +414,8 @@ system.cpu1.kern.ipl_good_0 10318 45.77% 45.77% # nu system.cpu1.kern.ipl_good_22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good_30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good_31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 1870124006000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 1859122587500 99.41% 99.41% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks 1870124056000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 1859122637500 99.41% 99.41% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks_22 82001000 0.00% 99.42% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks_30 14064500 0.00% 99.42% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks_31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl @@ -435,7 +435,7 @@ system.cpu1.kern.mode_switch_good_user 1 # fr system.cpu1.kern.mode_switch_good_idle 0.015640 # fraction of useful protection mode switches system.cpu1.kern.mode_ticks_kernel 1373909000 0.07% 0.07% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks_user 508289000 0.03% 0.10% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 1868002156500 99.90% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 1868002186500 99.90% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 471 # number of times the context was actually changed system.cpu1.kern.syscall 100 # number of syscalls executed system.cpu1.kern.syscall_2 2 2.00% 2.00% # number of syscalls executed @@ -456,7 +456,7 @@ system.cpu1.kern.syscall_74 8 8.00% 97.00% # nu system.cpu1.kern.syscall_90 1 1.00% 98.00% # number of syscalls executed system.cpu1.kern.syscall_132 2 2.00% 100.00% # number of syscalls executed system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles -system.cpu1.numCycles 3740248039 # number of cpu cycles simulated +system.cpu1.numCycles 3740248139 # number of cpu cycles simulated system.cpu1.num_insts 5931963 # Number of instructions executed system.cpu1.num_refs 1926645 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -525,38 +525,37 @@ system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 system.iocache.replacements 41695 # number of replacements system.iocache.sampled_refs 41711 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 0.435433 # Cycle average of tags in use +system.iocache.tagsinuse 0.435434 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41520 # number of writebacks system.l2c.ReadExReq_accesses 306246 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_misses 306246 # number of ReadExReq misses -system.l2c.ReadReq_accesses 2724166 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits 1625506 # number of ReadReq hits -system.l2c.ReadReq_miss_rate 0.403301 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 1098660 # number of ReadReq misses -system.l2c.UpgradeReq_accesses 125013 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadReq_accesses 2724148 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits 1759614 # number of ReadReq hits +system.l2c.ReadReq_miss_rate 0.354068 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 964534 # number of ReadReq misses +system.l2c.UpgradeReq_accesses 125010 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 125013 # number of UpgradeReq misses -system.l2c.Writeback_accesses 427646 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.l2c.Writeback_misses 427646 # number of Writeback misses +system.l2c.UpgradeReq_misses 125010 # number of UpgradeReq misses +system.l2c.Writeback_accesses 427643 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 427643 # number of Writeback hits system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_refs 1.720013 # Average number of references to valid blocks. +system.l2c.avg_refs 1.789371 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 3030412 # number of demand (read+write) accesses +system.l2c.demand_accesses 3030394 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency 0 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.l2c.demand_hits 1625506 # number of demand (read+write) hits +system.l2c.demand_hits 1759614 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.463602 # miss rate for demand accesses -system.l2c.demand_misses 1404906 # number of demand (read+write) misses +system.l2c.demand_miss_rate 0.419345 # miss rate for demand accesses +system.l2c.demand_misses 1270780 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -564,14 +563,14 @@ system.l2c.demand_mshr_misses 0 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 3030412 # number of overall (read+write) accesses +system.l2c.overall_accesses 3030394 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency 0 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.l2c.overall_hits 1625506 # number of overall hits +system.l2c.overall_hits 1759614 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate 0.463602 # miss rate for overall accesses -system.l2c.overall_misses 1404906 # number of overall misses +system.l2c.overall_miss_rate 0.419345 # miss rate for overall accesses +system.l2c.overall_misses 1270780 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -587,13 +586,13 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 947869 # number of replacements -system.l2c.sampled_refs 966791 # Sample count of references to valid blocks. +system.l2c.replacements 1056801 # number of replacements +system.l2c.sampled_refs 1091450 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 15587.342424 # Cycle average of tags in use -system.l2c.total_refs 1662893 # Total number of references to valid blocks. +system.l2c.tagsinuse 30522.435313 # Cycle average of tags in use +system.l2c.total_refs 1953009 # Total number of references to valid blocks. system.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 0 # number of writebacks +system.l2c.writebacks 123879 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr index 85bd66f32..4e60f8a9d 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr @@ -1,3 +1,4 @@ +warn: kernel located at: /dist/m5/system/binaries/vmlinux Listening for system connection on port 3456 0: system.remote_gdb.listener: listening for remote gdb on port 7000 0: system.remote_gdb.listener: listening for remote gdb on port 7001 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout index 007c73bfe..5f45dab42 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 14 2007 18:18:39 -M5 started Tue Aug 14 18:19:09 2007 -M5 executing on nacho +M5 compiled Feb 13 2008 00:33:19 +M5 started Wed Feb 13 00:38:27 2008 +M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1870335101500 because m5_exit instruction encountered +Exiting @ tick 1870335151500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt index 0780c3207..082e17724 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt @@ -1,21 +1,21 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2454439 # Simulator instruction rate (inst/s) -host_mem_usage 324968 # Number of bytes of host memory used -host_seconds 24.44 # Real time elapsed on the host -host_tick_rate 74797977378 # Simulator tick rate (ticks/s) +host_inst_rate 1474278 # Simulator instruction rate (inst/s) +host_mem_usage 260680 # Number of bytes of host memory used +host_seconds 40.70 # Real time elapsed on the host +host_tick_rate 44928072322 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 59995479 # Number of instructions simulated sim_seconds 1.828355 # Number of seconds simulated -sim_ticks 1828355476000 # Number of ticks simulated +sim_ticks 1828355496000 # Number of ticks simulated system.cpu.dcache.LoadLockedReq_accesses 200279 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 183119 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_miss_rate 0.085680 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_misses 17160 # number of LoadLockedReq misses system.cpu.dcache.ReadReq_accesses 9523054 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_hits 7801377 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 7801378 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_rate 0.180790 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1721677 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses 1721676 # number of ReadReq misses system.cpu.dcache.StoreCondReq_accesses 199258 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_hits 169392 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_miss_rate 0.149886 # miss rate for StoreCondReq accesses @@ -26,7 +26,7 @@ system.cpu.dcache.WriteReq_miss_rate 0.064944 # mi system.cpu.dcache.WriteReq_misses 399417 # number of WriteReq misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 6.866558 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 6.866562 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked @@ -35,10 +35,10 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.demand_accesses 15673243 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 0 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.dcache.demand_hits 13552149 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 13552150 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.135332 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2121094 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 2121093 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -50,10 +50,10 @@ system.cpu.dcache.overall_accesses 15673243 # nu system.cpu.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 13552149 # number of overall hits +system.cpu.dcache.overall_hits 13552150 # number of overall hits system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.135332 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2121094 # number of overall misses +system.cpu.dcache.overall_misses 2121093 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -69,11 +69,11 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 2042666 # number of replacements -system.cpu.dcache.sampled_refs 2043178 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 2042665 # number of replacements +system.cpu.dcache.sampled_refs 2043177 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 511.997801 # Cycle average of tags in use -system.cpu.dcache.total_refs 14029601 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 14029602 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 428885 # number of writebacks system.cpu.dtb.accesses 1020787 # DTB accesses @@ -89,12 +89,12 @@ system.cpu.dtb.write_acv 157 # DT system.cpu.dtb.write_hits 6349968 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.icache.ReadReq_accesses 60007317 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_hits 59087260 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 59087262 # number of ReadReq hits system.cpu.icache.ReadReq_miss_rate 0.015332 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 920057 # number of ReadReq misses +system.cpu.icache.ReadReq_misses 920055 # number of ReadReq misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 64.229332 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 64.229474 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked @@ -103,10 +103,10 @@ system.cpu.icache.cache_copies 0 # nu system.cpu.icache.demand_accesses 60007317 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 0 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.icache.demand_hits 59087260 # number of demand (read+write) hits +system.cpu.icache.demand_hits 59087262 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.015332 # miss rate for demand accesses -system.cpu.icache.demand_misses 920057 # number of demand (read+write) misses +system.cpu.icache.demand_misses 920055 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -118,10 +118,10 @@ system.cpu.icache.overall_accesses 60007317 # nu system.cpu.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 59087260 # number of overall hits +system.cpu.icache.overall_hits 59087262 # number of overall hits system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.015332 # miss rate for overall accesses -system.cpu.icache.overall_misses 920057 # number of overall misses +system.cpu.icache.overall_misses 920055 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -137,11 +137,11 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 919430 # number of replacements -system.cpu.icache.sampled_refs 919942 # Sample count of references to valid blocks. +system.cpu.icache.replacements 919428 # number of replacements +system.cpu.icache.sampled_refs 919940 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.tagsinuse 511.214820 # Cycle average of tags in use -system.cpu.icache.total_refs 59087260 # Total number of references to valid blocks. +system.cpu.icache.total_refs 59087262 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0.983588 # Percentage of idle cycles @@ -179,8 +179,8 @@ system.cpu.kern.ipl_good_0 73448 49.29% 49.29% # nu system.cpu.kern.ipl_good_21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_22 1865 1.25% 50.71% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_31 73448 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 1828355268500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 1811087537500 99.06% 99.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks 1828355288500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 1811087557500 99.06% 99.06% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks_21 20110000 0.00% 99.06% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks_22 80195000 0.00% 99.06% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks_31 17167426000 0.94% 100.00% # number of cycles we spent at this ipl @@ -200,7 +200,7 @@ system.cpu.kern.mode_switch_good_user 1 # fr system.cpu.kern.mode_switch_good_idle 0.081545 # fraction of useful protection mode switches system.cpu.kern.mode_ticks_kernel 26834026500 1.47% 1.47% # number of ticks spent at the given mode system.cpu.kern.mode_ticks_user 1465069000 0.08% 1.55% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 1800056172000 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 1800056192000 98.45% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.cpu.kern.syscall 326 # number of syscalls executed system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed @@ -234,7 +234,7 @@ system.cpu.kern.syscall_132 4 1.23% 98.77% # nu system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed system.cpu.not_idle_fraction 0.016412 # Percentage of non-idle cycles -system.cpu.numCycles 3656710843 # number of cpu cycles simulated +system.cpu.numCycles 3656710883 # number of cpu cycles simulated system.cpu.num_insts 59995479 # Number of instructions executed system.cpu.num_refs 16302129 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -310,31 +310,30 @@ system.iocache.writebacks 41512 # nu system.l2c.ReadExReq_accesses 304342 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_misses 304342 # number of ReadExReq misses -system.l2c.ReadReq_accesses 2658877 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits 1558398 # number of ReadReq hits -system.l2c.ReadReq_miss_rate 0.413889 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 1100479 # number of ReadReq misses +system.l2c.ReadReq_accesses 2658874 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits 1696454 # number of ReadReq hits +system.l2c.ReadReq_miss_rate 0.361965 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 962420 # number of ReadReq misses system.l2c.UpgradeReq_accesses 124941 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_misses 124941 # number of UpgradeReq misses system.l2c.Writeback_accesses 428885 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.l2c.Writeback_misses 428885 # number of Writeback misses +system.l2c.Writeback_hits 428885 # number of Writeback hits system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_refs 1.644070 # Average number of references to valid blocks. +system.l2c.avg_refs 1.726821 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2963219 # number of demand (read+write) accesses +system.l2c.demand_accesses 2963216 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency 0 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.l2c.demand_hits 1558398 # number of demand (read+write) hits +system.l2c.demand_hits 1696454 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.474086 # miss rate for demand accesses -system.l2c.demand_misses 1404821 # number of demand (read+write) misses +system.l2c.demand_miss_rate 0.427496 # miss rate for demand accesses +system.l2c.demand_misses 1266762 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -342,14 +341,14 @@ system.l2c.demand_mshr_misses 0 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 2963219 # number of overall (read+write) accesses +system.l2c.overall_accesses 2963216 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency 0 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.l2c.overall_hits 1558398 # number of overall hits +system.l2c.overall_hits 1696454 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate 0.474086 # miss rate for overall accesses -system.l2c.overall_misses 1404821 # number of overall misses +system.l2c.overall_miss_rate 0.427496 # miss rate for overall accesses +system.l2c.overall_misses 1266762 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -365,13 +364,13 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 947436 # number of replacements -system.l2c.sampled_refs 965232 # Sample count of references to valid blocks. +system.l2c.replacements 1050727 # number of replacements +system.l2c.sampled_refs 1081066 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 15309.548937 # Cycle average of tags in use -system.l2c.total_refs 1586909 # Total number of references to valid blocks. -system.l2c.warmup_cycle 789998500 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 0 # number of writebacks +system.l2c.tagsinuse 30223.986648 # Cycle average of tags in use +system.l2c.total_refs 1866807 # Total number of references to valid blocks. +system.l2c.warmup_cycle 765422500 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 119145 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr index 072cb6c8c..7e35fafed 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr @@ -1,3 +1,4 @@ +warn: kernel located at: /dist/m5/system/binaries/vmlinux Listening for system connection on port 3456 0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout index 45d7ecef6..830f4d057 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 14 2007 18:18:39 -M5 started Tue Aug 14 18:18:41 2007 -M5 executing on nacho +M5 compiled Feb 13 2008 00:33:19 +M5 started Wed Feb 13 00:37:45 2008 +M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1828355476000 because m5_exit instruction encountered +Exiting @ tick 1828355496000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt index e6200df10..c18975d3b 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt @@ -1,92 +1,92 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1027363 # Simulator instruction rate (inst/s) -host_mem_usage 295468 # Number of bytes of host memory used -host_seconds 63.08 # Real time elapsed on the host -host_tick_rate 31207407187 # Simulator tick rate (ticks/s) +host_inst_rate 648626 # Simulator instruction rate (inst/s) +host_mem_usage 258032 # Number of bytes of host memory used +host_seconds 99.90 # Real time elapsed on the host +host_tick_rate 19695199685 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 64810685 # Number of instructions simulated -sim_seconds 1.968714 # Number of seconds simulated -sim_ticks 1968713509000 # Number of ticks simulated -system.cpu0.dcache.LoadLockedReq_accesses 151114 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_avg_miss_latency 19061.903705 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 17061.903705 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_hits 137593 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_miss_latency 257736000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_rate 0.089475 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_misses 13521 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 230694000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.089475 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_misses 13521 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.ReadReq_accesses 7907510 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency 20735.722621 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 18735.695271 # average ReadReq mshr miss latency +sim_insts 64798015 # Number of instructions simulated +sim_seconds 1.967565 # Number of seconds simulated +sim_ticks 1967564570000 # Number of ticks simulated +system.cpu0.dcache.LoadLockedReq_accesses 152955 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_avg_miss_latency 10704.654422 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 8704.654422 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_hits 139398 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_miss_latency 145123000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_rate 0.088634 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses 13557 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 118009000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.088634 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_misses 13557 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.ReadReq_accesses 7963598 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency 20070.335067 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 18070.307129 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_hits 6317022 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 32979918000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate 0.201136 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 1590488 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 29798898500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate 0.201136 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 1590488 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 851250000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_accesses 150580 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_avg_miss_latency 21081.002979 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 19081.002979 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_hits 128087 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_latency 474175000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_rate 0.149376 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_misses 22493 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 429189000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.149376 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_misses 22493 # number of StoreCondReq MSHR misses -system.cpu0.dcache.WriteReq_accesses 4787550 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency 24603.629534 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 22603.629534 # average WriteReq mshr miss latency +system.cpu0.dcache.ReadReq_hits 6370751 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 31968973000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate 0.200016 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 1592847 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_miss_latency 28783234500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate 0.200016 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_misses 1592847 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 851983000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_accesses 152411 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_avg_miss_latency 21138.488499 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 19138.488499 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_hits 129586 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_latency 482486000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_rate 0.149760 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses 22825 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 436836000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.149760 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_misses 22825 # number of StoreCondReq MSHR misses +system.cpu0.dcache.WriteReq_accesses 4879916 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency 24612.653120 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 22612.653120 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_hits 4476601 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 7650474000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate 0.064950 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 310949 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_miss_latency 7028576000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate 0.064950 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 310949 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1305238500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_hits 4559987 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 7874301500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate 0.065560 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 319929 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_miss_latency 7234443500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.065560 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_misses 319929 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1309796000 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 6.113033 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 6.157894 # Average number of references to valid blocks. system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 12695060 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency 21368.255693 # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 19368.232815 # average overall mshr miss latency -system.cpu0.dcache.demand_hits 10793623 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 40630392000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.149778 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 1901437 # number of demand (read+write) misses +system.cpu0.dcache.demand_accesses 12843514 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 20830.078640 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 18830.055375 # average overall mshr miss latency +system.cpu0.dcache.demand_hits 10930738 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 39843274500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.148929 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 1912776 # number of demand (read+write) misses system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 36827474500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate 0.149778 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 1901437 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_miss_latency 36017678000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0.148929 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 1912776 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.overall_accesses 12695060 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency 21368.255693 # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 19368.232815 # average overall mshr miss latency +system.cpu0.dcache.overall_accesses 12843514 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 20830.078640 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 18830.055375 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 10793623 # number of overall hits -system.cpu0.dcache.overall_miss_latency 40630392000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.149778 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 1901437 # number of overall misses +system.cpu0.dcache.overall_hits 10930738 # number of overall hits +system.cpu0.dcache.overall_miss_latency 39843274500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.148929 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 1912776 # number of overall misses system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 36827474500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate 0.149778 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 1901437 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_latency 2156488500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_miss_latency 36017678000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0.148929 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 1912776 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 2161779000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -97,69 +97,69 @@ system.cpu0.dcache.prefetcher.num_hwpf_issued 0 system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.dcache.replacements 1823135 # number of replacements -system.cpu0.dcache.sampled_refs 1823507 # Sample count of references to valid blocks. +system.cpu0.dcache.replacements 1833934 # number of replacements +system.cpu0.dcache.sampled_refs 1834336 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 497.865470 # Cycle average of tags in use -system.cpu0.dcache.total_refs 11147158 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 497.817837 # Cycle average of tags in use +system.cpu0.dcache.total_refs 11295646 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 64994000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 318658 # number of writebacks -system.cpu0.dtb.accesses 670326 # DTB accesses -system.cpu0.dtb.acv 284 # DTB access violations -system.cpu0.dtb.hits 12987845 # DTB hits -system.cpu0.dtb.misses 8007 # DTB misses -system.cpu0.dtb.read_accesses 490175 # DTB read accesses -system.cpu0.dtb.read_acv 174 # DTB read access violations -system.cpu0.dtb.read_hits 8046787 # DTB read hits -system.cpu0.dtb.read_misses 7315 # DTB read misses -system.cpu0.dtb.write_accesses 180151 # DTB write accesses -system.cpu0.dtb.write_acv 110 # DTB write access violations -system.cpu0.dtb.write_hits 4941058 # DTB write hits -system.cpu0.dtb.write_misses 692 # DTB write misses -system.cpu0.icache.ReadReq_accesses 50999228 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency 13252.142852 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11250.854306 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits 50311243 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 9117275500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate 0.013490 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses 687985 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_miss_latency 7740419000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate 0.013490 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 687985 # number of ReadReq MSHR misses +system.cpu0.dcache.writebacks 327909 # number of writebacks +system.cpu0.dtb.accesses 678125 # DTB accesses +system.cpu0.dtb.acv 344 # DTB access violations +system.cpu0.dtb.hits 13139275 # DTB hits +system.cpu0.dtb.misses 8256 # DTB misses +system.cpu0.dtb.read_accesses 490673 # DTB read accesses +system.cpu0.dtb.read_acv 210 # DTB read access violations +system.cpu0.dtb.read_hits 8104054 # DTB read hits +system.cpu0.dtb.read_misses 7443 # DTB read misses +system.cpu0.dtb.write_accesses 187452 # DTB write accesses +system.cpu0.dtb.write_acv 134 # DTB write access violations +system.cpu0.dtb.write_hits 5035221 # DTB write hits +system.cpu0.dtb.write_misses 813 # DTB write misses +system.cpu0.icache.ReadReq_accesses 51427836 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency 13266.248960 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11264.967295 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits 50734207 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 9201855000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate 0.013487 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 693629 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_miss_latency 7813708000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate 0.013487 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_misses 693629 # number of ReadReq MSHR misses system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 73.142328 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 73.155696 # Average number of references to valid blocks. system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 50999228 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency 13252.142852 # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 11250.854306 # average overall mshr miss latency -system.cpu0.icache.demand_hits 50311243 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 9117275500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate 0.013490 # miss rate for demand accesses -system.cpu0.icache.demand_misses 687985 # number of demand (read+write) misses +system.cpu0.icache.demand_accesses 51427836 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 13266.248960 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 11264.967295 # average overall mshr miss latency +system.cpu0.icache.demand_hits 50734207 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 9201855000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.013487 # miss rate for demand accesses +system.cpu0.icache.demand_misses 693629 # number of demand (read+write) misses system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 7740419000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate 0.013490 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 687985 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_miss_latency 7813708000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0.013487 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 693629 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.overall_accesses 50999228 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency 13252.142852 # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 11250.854306 # average overall mshr miss latency +system.cpu0.icache.overall_accesses 51427836 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 13266.248960 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 11264.967295 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 50311243 # number of overall hits -system.cpu0.icache.overall_miss_latency 9117275500 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate 0.013490 # miss rate for overall accesses -system.cpu0.icache.overall_misses 687985 # number of overall misses +system.cpu0.icache.overall_hits 50734207 # number of overall hits +system.cpu0.icache.overall_miss_latency 9201855000 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.013487 # miss rate for overall accesses +system.cpu0.icache.overall_misses 693629 # number of overall misses system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 7740419000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate 0.013490 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 687985 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_miss_latency 7813708000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0.013487 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 693629 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -171,190 +171,189 @@ system.cpu0.icache.prefetcher.num_hwpf_issued 0 system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.icache.replacements 687342 # number of replacements -system.cpu0.icache.sampled_refs 687854 # Sample count of references to valid blocks. +system.cpu0.icache.replacements 692998 # number of replacements +system.cpu0.icache.sampled_refs 693510 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 507.625820 # Cycle average of tags in use -system.cpu0.icache.total_refs 50311243 # Total number of references to valid blocks. -system.cpu0.icache.warmup_cycle 47300854000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tagsinuse 507.634004 # Cycle average of tags in use +system.cpu0.icache.total_refs 50734207 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 46911365000 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idle_fraction 0.942071 # Percentage of idle cycles -system.cpu0.itb.accesses 3425789 # ITB accesses -system.cpu0.itb.acv 143 # ITB acv -system.cpu0.itb.hits 3422100 # ITB hits -system.cpu0.itb.misses 3689 # ITB misses -system.cpu0.kern.callpal 147422 # number of callpals executed +system.cpu0.idle_fraction 0.942159 # Percentage of idle cycles +system.cpu0.itb.accesses 3496262 # ITB accesses +system.cpu0.itb.acv 184 # ITB acv +system.cpu0.itb.hits 3492391 # ITB hits +system.cpu0.itb.misses 3871 # ITB misses +system.cpu0.kern.callpal 148751 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal_wripir 513 0.35% 0.35% # number of callpals executed +system.cpu0.kern.callpal_wripir 513 0.34% 0.35% # number of callpals executed system.cpu0.kern.callpal_wrmces 1 0.00% 0.35% # number of callpals executed system.cpu0.kern.callpal_wrfen 1 0.00% 0.35% # number of callpals executed system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.35% # number of callpals executed -system.cpu0.kern.callpal_swpctx 2975 2.02% 2.37% # number of callpals executed -system.cpu0.kern.callpal_tbi 44 0.03% 2.40% # number of callpals executed -system.cpu0.kern.callpal_wrent 7 0.00% 2.40% # number of callpals executed -system.cpu0.kern.callpal_swpipl 132539 89.90% 92.31% # number of callpals executed -system.cpu0.kern.callpal_rdps 6657 4.52% 96.82% # number of callpals executed -system.cpu0.kern.callpal_wrkgp 1 0.00% 96.82% # number of callpals executed -system.cpu0.kern.callpal_wrusp 3 0.00% 96.83% # number of callpals executed -system.cpu0.kern.callpal_rdusp 7 0.00% 96.83% # number of callpals executed -system.cpu0.kern.callpal_whami 2 0.00% 96.83% # number of callpals executed -system.cpu0.kern.callpal_rti 4182 2.84% 99.67% # number of callpals executed -system.cpu0.kern.callpal_callsys 341 0.23% 99.90% # number of callpals executed -system.cpu0.kern.callpal_imb 147 0.10% 100.00% # number of callpals executed +system.cpu0.kern.callpal_swpctx 3046 2.05% 2.40% # number of callpals executed +system.cpu0.kern.callpal_tbi 51 0.03% 2.43% # number of callpals executed +system.cpu0.kern.callpal_wrent 7 0.00% 2.43% # number of callpals executed +system.cpu0.kern.callpal_swpipl 133601 89.82% 92.25% # number of callpals executed +system.cpu0.kern.callpal_rdps 6671 4.48% 96.73% # number of callpals executed +system.cpu0.kern.callpal_wrkgp 1 0.00% 96.73% # number of callpals executed +system.cpu0.kern.callpal_wrusp 3 0.00% 96.74% # number of callpals executed +system.cpu0.kern.callpal_rdusp 9 0.01% 96.74% # number of callpals executed +system.cpu0.kern.callpal_whami 2 0.00% 96.74% # number of callpals executed +system.cpu0.kern.callpal_rti 4326 2.91% 99.65% # number of callpals executed +system.cpu0.kern.callpal_callsys 381 0.26% 99.91% # number of callpals executed +system.cpu0.kern.callpal_imb 136 0.09% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 162080 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 6601 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 139255 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 55824 40.09% 40.09% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_21 133 0.10% 40.18% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_22 1975 1.42% 41.60% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_30 427 0.31% 41.91% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 80896 58.09% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 112706 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 55298 49.06% 49.06% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_21 133 0.12% 49.18% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_22 1975 1.75% 50.93% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_30 427 0.38% 51.31% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 54873 48.69% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 1967810431000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 1902069649000 96.66% 96.66% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 84751000 0.00% 96.66% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 557432500 0.03% 96.69% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 285148500 0.01% 96.71% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 64813450000 3.29% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used_0 0.990578 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.hwrei 163942 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6592 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 140462 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 56424 40.17% 40.17% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_21 131 0.09% 40.26% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_22 1973 1.40% 41.67% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_30 430 0.31% 41.97% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_31 81504 58.03% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 113912 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 55904 49.08% 49.08% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_22 1973 1.73% 50.92% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_30 430 0.38% 51.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_31 55474 48.70% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 1966802467000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 1901463113000 96.68% 96.68% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 84103500 0.00% 96.68% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 556720500 0.03% 96.71% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 288292000 0.01% 96.73% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 64410238000 3.27% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used_0 0.990784 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.678315 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1135 -system.cpu0.kern.mode_good_user 1135 +system.cpu0.kern.ipl_used_31 0.680629 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1282 +system.cpu0.kern.mode_good_user 1282 system.cpu0.kern.mode_good_idle 0 -system.cpu0.kern.mode_switch_kernel 6655 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1135 # number of protection mode switches +system.cpu0.kern.mode_switch_kernel 6876 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1282 # number of protection mode switches system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches system.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.170548 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.186446 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 1963744351000 99.84% 99.84% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 3182753000 0.16% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_kernel 1963425353000 99.84% 99.84% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 3220853000 0.16% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2976 # number of times the context was actually changed -system.cpu0.kern.syscall 212 # number of syscalls executed -system.cpu0.kern.syscall_2 6 2.83% 2.83% # number of syscalls executed -system.cpu0.kern.syscall_3 18 8.49% 11.32% # number of syscalls executed -system.cpu0.kern.syscall_4 3 1.42% 12.74% # number of syscalls executed -system.cpu0.kern.syscall_6 29 13.68% 26.42% # number of syscalls executed -system.cpu0.kern.syscall_12 1 0.47% 26.89% # number of syscalls executed -system.cpu0.kern.syscall_15 1 0.47% 27.36% # number of syscalls executed -system.cpu0.kern.syscall_17 9 4.25% 31.60% # number of syscalls executed -system.cpu0.kern.syscall_19 6 2.83% 34.43% # number of syscalls executed -system.cpu0.kern.syscall_20 4 1.89% 36.32% # number of syscalls executed -system.cpu0.kern.syscall_23 2 0.94% 37.26% # number of syscalls executed -system.cpu0.kern.syscall_24 4 1.89% 39.15% # number of syscalls executed -system.cpu0.kern.syscall_33 7 3.30% 42.45% # number of syscalls executed -system.cpu0.kern.syscall_41 2 0.94% 43.40% # number of syscalls executed -system.cpu0.kern.syscall_45 36 16.98% 60.38% # number of syscalls executed -system.cpu0.kern.syscall_47 4 1.89% 62.26% # number of syscalls executed -system.cpu0.kern.syscall_48 7 3.30% 65.57% # number of syscalls executed -system.cpu0.kern.syscall_54 9 4.25% 69.81% # number of syscalls executed -system.cpu0.kern.syscall_58 1 0.47% 70.28% # number of syscalls executed -system.cpu0.kern.syscall_59 5 2.36% 72.64% # number of syscalls executed -system.cpu0.kern.syscall_71 28 13.21% 85.85% # number of syscalls executed -system.cpu0.kern.syscall_73 3 1.42% 87.26% # number of syscalls executed -system.cpu0.kern.syscall_74 8 3.77% 91.04% # number of syscalls executed -system.cpu0.kern.syscall_87 1 0.47% 91.51% # number of syscalls executed -system.cpu0.kern.syscall_90 2 0.94% 92.45% # number of syscalls executed -system.cpu0.kern.syscall_92 7 3.30% 95.75% # number of syscalls executed -system.cpu0.kern.syscall_97 2 0.94% 96.70% # number of syscalls executed -system.cpu0.kern.syscall_98 2 0.94% 97.64% # number of syscalls executed -system.cpu0.kern.syscall_132 2 0.94% 98.58% # number of syscalls executed -system.cpu0.kern.syscall_144 1 0.47% 99.06% # number of syscalls executed -system.cpu0.kern.syscall_147 2 0.94% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.057929 # Percentage of non-idle cycles -system.cpu0.numCycles 3935620922 # number of cpu cycles simulated -system.cpu0.num_insts 50990937 # Number of instructions executed -system.cpu0.num_refs 13220047 # Number of memory references -system.cpu1.dcache.LoadLockedReq_accesses 60083 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_avg_miss_latency 15361.860059 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 13361.860059 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_hits 50922 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_miss_latency 140730000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_rate 0.152472 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_misses 9161 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 122408000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate 0.152472 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_misses 9161 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.ReadReq_accesses 2467630 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency 15346.569238 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13346.533103 # average ReadReq mshr miss latency +system.cpu0.kern.swap_context 3047 # number of times the context was actually changed +system.cpu0.kern.syscall 222 # number of syscalls executed +system.cpu0.kern.syscall_2 8 3.60% 3.60% # number of syscalls executed +system.cpu0.kern.syscall_3 19 8.56% 12.16% # number of syscalls executed +system.cpu0.kern.syscall_4 4 1.80% 13.96% # number of syscalls executed +system.cpu0.kern.syscall_6 32 14.41% 28.38% # number of syscalls executed +system.cpu0.kern.syscall_12 1 0.45% 28.83% # number of syscalls executed +system.cpu0.kern.syscall_17 9 4.05% 32.88% # number of syscalls executed +system.cpu0.kern.syscall_19 10 4.50% 37.39% # number of syscalls executed +system.cpu0.kern.syscall_20 6 2.70% 40.09% # number of syscalls executed +system.cpu0.kern.syscall_23 1 0.45% 40.54% # number of syscalls executed +system.cpu0.kern.syscall_24 3 1.35% 41.89% # number of syscalls executed +system.cpu0.kern.syscall_33 7 3.15% 45.05% # number of syscalls executed +system.cpu0.kern.syscall_41 2 0.90% 45.95% # number of syscalls executed +system.cpu0.kern.syscall_45 36 16.22% 62.16% # number of syscalls executed +system.cpu0.kern.syscall_47 3 1.35% 63.51% # number of syscalls executed +system.cpu0.kern.syscall_48 10 4.50% 68.02% # number of syscalls executed +system.cpu0.kern.syscall_54 10 4.50% 72.52% # number of syscalls executed +system.cpu0.kern.syscall_58 1 0.45% 72.97% # number of syscalls executed +system.cpu0.kern.syscall_59 6 2.70% 75.68% # number of syscalls executed +system.cpu0.kern.syscall_71 23 10.36% 86.04% # number of syscalls executed +system.cpu0.kern.syscall_73 3 1.35% 87.39% # number of syscalls executed +system.cpu0.kern.syscall_74 6 2.70% 90.09% # number of syscalls executed +system.cpu0.kern.syscall_87 1 0.45% 90.54% # number of syscalls executed +system.cpu0.kern.syscall_90 3 1.35% 91.89% # number of syscalls executed +system.cpu0.kern.syscall_92 9 4.05% 95.95% # number of syscalls executed +system.cpu0.kern.syscall_97 2 0.90% 96.85% # number of syscalls executed +system.cpu0.kern.syscall_98 2 0.90% 97.75% # number of syscalls executed +system.cpu0.kern.syscall_132 1 0.45% 98.20% # number of syscalls executed +system.cpu0.kern.syscall_144 2 0.90% 99.10% # number of syscalls executed +system.cpu0.kern.syscall_147 2 0.90% 100.00% # number of syscalls executed +system.cpu0.not_idle_fraction 0.057841 # Percentage of non-idle cycles +system.cpu0.numCycles 3933604994 # number of cpu cycles simulated +system.cpu0.num_insts 51419236 # Number of instructions executed +system.cpu0.num_refs 13372686 # Number of memory references +system.cpu1.dcache.LoadLockedReq_accesses 58218 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_avg_miss_latency 9171.136514 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 7171.136514 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_hits 49120 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_miss_latency 83439000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_rate 0.156275 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_misses 9098 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 65243000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate 0.156275 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_misses 9098 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.ReadReq_accesses 2411466 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency 12361.271462 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 10361.242681 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_hits 2343095 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 1911185000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate 0.050467 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses 124535 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 1662110500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate 0.050467 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 124535 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 13285500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.StoreCondReq_accesses 59592 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_avg_miss_latency 18194.204729 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 16194.204729 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_hits 45339 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_miss_latency 259322000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_rate 0.239176 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_misses 14253 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 230816000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.239176 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_misses 14253 # number of StoreCondReq MSHR misses -system.cpu1.dcache.WriteReq_accesses 1828255 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency 23673.821566 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 21673.821566 # average WriteReq mshr miss latency +system.cpu1.dcache.ReadReq_hits 2289858 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 1503229500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate 0.050429 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 121608 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_miss_latency 1260010000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate 0.050429 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_misses 121608 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 11809500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.StoreCondReq_accesses 57736 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_avg_miss_latency 18004.399567 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 16004.399567 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_hits 43871 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_miss_latency 249631000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_rate 0.240145 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses 13865 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 221901000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.240145 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_misses 13865 # number of StoreCondReq MSHR misses +system.cpu1.dcache.WriteReq_accesses 1733520 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency 23546.439804 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 21546.439804 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_hits 1730583 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 2312269500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate 0.053424 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses 97672 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_miss_latency 2116925500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate 0.053424 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 97672 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 405997000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_hits 1645449 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 2073758500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate 0.050805 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 88071 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_miss_latency 1897616500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.050805 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_misses 88071 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 401567500 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 22.844005 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 23.594558 # Average number of references to valid blocks. system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses 4295885 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency 19006.847219 # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 17006.826968 # average overall mshr miss latency -system.cpu1.dcache.demand_hits 4073678 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 4223454500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.051726 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 222207 # number of demand (read+write) misses +system.cpu1.dcache.demand_accesses 4144986 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 17059.352629 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 15059.335937 # average overall mshr miss latency +system.cpu1.dcache.demand_hits 3935307 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 3576988000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.050586 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 209679 # number of demand (read+write) misses system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 3779036000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate 0.051726 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 222207 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_miss_latency 3157626500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0.050586 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 209679 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.overall_accesses 4295885 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency 19006.847219 # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 17006.826968 # average overall mshr miss latency +system.cpu1.dcache.overall_accesses 4144986 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 17059.352629 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 15059.335937 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 4073678 # number of overall hits -system.cpu1.dcache.overall_miss_latency 4223454500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.051726 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 222207 # number of overall misses +system.cpu1.dcache.overall_hits 3935307 # number of overall hits +system.cpu1.dcache.overall_miss_latency 3576988000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.050586 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 209679 # number of overall misses system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 3779036000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate 0.051726 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 222207 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_latency 419282500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_miss_latency 3157626500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0.050586 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 209679 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 413377000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -365,69 +364,69 @@ system.cpu1.dcache.prefetcher.num_hwpf_issued 0 system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.dcache.replacements 184039 # number of replacements -system.cpu1.dcache.sampled_refs 184551 # Sample count of references to valid blocks. +system.cpu1.dcache.replacements 172122 # number of replacements +system.cpu1.dcache.sampled_refs 172634 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 467.870479 # Cycle average of tags in use -system.cpu1.dcache.total_refs 4215884 # Total number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1952085320000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 99034 # number of writebacks -system.cpu1.dtb.accesses 352410 # DTB accesses -system.cpu1.dtb.acv 89 # DTB access violations -system.cpu1.dtb.hits 4401543 # DTB hits -system.cpu1.dtb.misses 3585 # DTB misses -system.cpu1.dtb.read_accesses 239862 # DTB read accesses -system.cpu1.dtb.read_acv 36 # DTB read access violations -system.cpu1.dtb.read_hits 2515664 # DTB read hits -system.cpu1.dtb.read_misses 3123 # DTB read misses -system.cpu1.dtb.write_accesses 112548 # DTB write accesses -system.cpu1.dtb.write_acv 53 # DTB write access violations -system.cpu1.dtb.write_hits 1885879 # DTB write hits -system.cpu1.dtb.write_misses 462 # DTB write misses -system.cpu1.icache.ReadReq_accesses 13823423 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency 13058.245594 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11058.114859 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits 13494514 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 4294974500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate 0.023794 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses 328909 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_miss_latency 3637113500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate 0.023794 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 328909 # number of ReadReq MSHR misses +system.cpu1.dcache.tagsinuse 469.368007 # Cycle average of tags in use +system.cpu1.dcache.total_refs 4073223 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1951036839000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 89024 # number of writebacks +system.cpu1.dtb.accesses 344610 # DTB accesses +system.cpu1.dtb.acv 29 # DTB access violations +system.cpu1.dtb.hits 4247594 # DTB hits +system.cpu1.dtb.misses 3333 # DTB misses +system.cpu1.dtb.read_accesses 239363 # DTB read accesses +system.cpu1.dtb.read_acv 0 # DTB read access violations +system.cpu1.dtb.read_hits 2458285 # DTB read hits +system.cpu1.dtb.read_misses 2992 # DTB read misses +system.cpu1.dtb.write_accesses 105247 # DTB write accesses +system.cpu1.dtb.write_acv 29 # DTB write access violations +system.cpu1.dtb.write_hits 1789309 # DTB write hits +system.cpu1.dtb.write_misses 341 # DTB write misses +system.cpu1.icache.ReadReq_accesses 13382142 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency 13055.545234 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11055.430670 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits 13059180 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 4216445000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate 0.024134 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 322962 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_miss_latency 3570484000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate 0.024134 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_misses 322962 # number of ReadReq MSHR misses system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 41.031476 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 40.439912 # Average number of references to valid blocks. system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses 13823423 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency 13058.245594 # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11058.114859 # average overall mshr miss latency -system.cpu1.icache.demand_hits 13494514 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 4294974500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate 0.023794 # miss rate for demand accesses -system.cpu1.icache.demand_misses 328909 # number of demand (read+write) misses +system.cpu1.icache.demand_accesses 13382142 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 13055.545234 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11055.430670 # average overall mshr miss latency +system.cpu1.icache.demand_hits 13059180 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 4216445000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.024134 # miss rate for demand accesses +system.cpu1.icache.demand_misses 322962 # number of demand (read+write) misses system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 3637113500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate 0.023794 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 328909 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_miss_latency 3570484000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0.024134 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 322962 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.overall_accesses 13823423 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency 13058.245594 # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11058.114859 # average overall mshr miss latency +system.cpu1.icache.overall_accesses 13382142 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 13055.545234 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11055.430670 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits 13494514 # number of overall hits -system.cpu1.icache.overall_miss_latency 4294974500 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate 0.023794 # miss rate for overall accesses -system.cpu1.icache.overall_misses 328909 # number of overall misses +system.cpu1.icache.overall_hits 13059180 # number of overall hits +system.cpu1.icache.overall_miss_latency 4216445000 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.024134 # miss rate for overall accesses +system.cpu1.icache.overall_misses 322962 # number of overall misses system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 3637113500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate 0.023794 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 328909 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_miss_latency 3570484000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0.024134 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 322962 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -439,98 +438,89 @@ system.cpu1.icache.prefetcher.num_hwpf_issued 0 system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.icache.replacements 328370 # number of replacements -system.cpu1.icache.sampled_refs 328882 # Sample count of references to valid blocks. +system.cpu1.icache.replacements 322416 # number of replacements +system.cpu1.icache.sampled_refs 322928 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 445.144140 # Cycle average of tags in use -system.cpu1.icache.total_refs 13494514 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1965066529000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tagsinuse 445.335052 # Cycle average of tags in use +system.cpu1.icache.total_refs 13059180 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1965624447000 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.idle_fraction 0.986280 # Percentage of idle cycles -system.cpu1.itb.accesses 2047720 # ITB accesses -system.cpu1.itb.acv 41 # ITB acv -system.cpu1.itb.hits 2046322 # ITB hits -system.cpu1.itb.misses 1398 # ITB misses -system.cpu1.kern.callpal 73914 # number of callpals executed +system.cpu1.idle_fraction 0.986971 # Percentage of idle cycles +system.cpu1.itb.accesses 1976959 # ITB accesses +system.cpu1.itb.acv 0 # ITB acv +system.cpu1.itb.hits 1975743 # ITB hits +system.cpu1.itb.misses 1216 # ITB misses +system.cpu1.kern.callpal 72548 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal_wripir 427 0.58% 0.58% # number of callpals executed -system.cpu1.kern.callpal_wrmces 1 0.00% 0.58% # number of callpals executed -system.cpu1.kern.callpal_wrfen 1 0.00% 0.58% # number of callpals executed -system.cpu1.kern.callpal_swpctx 2101 2.84% 3.42% # number of callpals executed -system.cpu1.kern.callpal_tbi 10 0.01% 3.44% # number of callpals executed -system.cpu1.kern.callpal_wrent 7 0.01% 3.45% # number of callpals executed -system.cpu1.kern.callpal_swpipl 65013 87.96% 91.40% # number of callpals executed -system.cpu1.kern.callpal_rdps 2189 2.96% 94.37% # number of callpals executed -system.cpu1.kern.callpal_wrkgp 1 0.00% 94.37% # number of callpals executed -system.cpu1.kern.callpal_wrusp 4 0.01% 94.37% # number of callpals executed -system.cpu1.kern.callpal_rdusp 2 0.00% 94.38% # number of callpals executed -system.cpu1.kern.callpal_whami 3 0.00% 94.38% # number of callpals executed -system.cpu1.kern.callpal_rti 3944 5.34% 99.72% # number of callpals executed -system.cpu1.kern.callpal_callsys 176 0.24% 99.95% # number of callpals executed -system.cpu1.kern.callpal_imb 33 0.04% 100.00% # number of callpals executed +system.cpu1.kern.callpal_wripir 430 0.59% 0.59% # number of callpals executed +system.cpu1.kern.callpal_wrmces 1 0.00% 0.60% # number of callpals executed +system.cpu1.kern.callpal_wrfen 1 0.00% 0.60% # number of callpals executed +system.cpu1.kern.callpal_swpctx 2033 2.80% 3.40% # number of callpals executed +system.cpu1.kern.callpal_tbi 3 0.00% 3.40% # number of callpals executed +system.cpu1.kern.callpal_wrent 7 0.01% 3.41% # number of callpals executed +system.cpu1.kern.callpal_swpipl 63908 88.09% 91.50% # number of callpals executed +system.cpu1.kern.callpal_rdps 2174 3.00% 94.50% # number of callpals executed +system.cpu1.kern.callpal_wrkgp 1 0.00% 94.50% # number of callpals executed +system.cpu1.kern.callpal_wrusp 4 0.01% 94.51% # number of callpals executed +system.cpu1.kern.callpal_whami 3 0.00% 94.51% # number of callpals executed +system.cpu1.kern.callpal_rti 3801 5.24% 99.75% # number of callpals executed +system.cpu1.kern.callpal_callsys 136 0.19% 99.94% # number of callpals executed +system.cpu1.kern.callpal_imb 44 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 81510 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 2786 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 71439 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 27567 38.59% 38.59% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_22 1968 2.75% 41.34% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_30 513 0.72% 42.06% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 41391 57.94% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 55400 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 26716 48.22% 48.22% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_22 1968 3.55% 51.78% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_30 513 0.93% 52.70% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 26203 47.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 1968712763000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 1909929590000 97.01% 97.01% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 504028500 0.03% 97.04% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_30 338306500 0.02% 97.06% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 57940838000 2.94% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used_0 0.969130 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.hwrei 79609 # number of hwrei instructions executed +system.cpu1.kern.inst.quiesce 2775 # number of quiesce instructions executed +system.cpu1.kern.ipl_count 70191 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 26969 38.42% 38.42% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_22 1968 2.80% 41.23% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_30 513 0.73% 41.96% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_31 40741 58.04% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 54192 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 26112 48.18% 48.18% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_22 1968 3.63% 51.82% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_30 513 0.95% 52.76% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_31 25599 47.24% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 1967563848000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 1909498960500 97.05% 97.05% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 504062500 0.03% 97.07% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_30 337556000 0.02% 97.09% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 57223269000 2.91% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used_0 0.968223 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.633060 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good_kernel 1049 -system.cpu1.kern.mode_good_user 612 +system.cpu1.kern.ipl_used_31 0.628335 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good_kernel 900 +system.cpu1.kern.mode_good_user 463 system.cpu1.kern.mode_good_idle 437 -system.cpu1.kern.mode_switch_kernel 2309 # number of protection mode switches -system.cpu1.kern.mode_switch_user 612 # number of protection mode switches -system.cpu1.kern.mode_switch_idle 2896 # number of protection mode switches -system.cpu1.kern.mode_switch_good 1.605207 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_kernel 0.454309 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_kernel 2093 # number of protection mode switches +system.cpu1.kern.mode_switch_user 463 # number of protection mode switches +system.cpu1.kern.mode_switch_idle 2895 # number of protection mode switches +system.cpu1.kern.mode_switch_good 1.580955 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_kernel 0.430005 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_idle 0.150898 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 20134441000 1.02% 1.02% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 1860335000 0.09% 1.12% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 1946717985000 98.88% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2102 # number of times the context was actually changed -system.cpu1.kern.syscall 114 # number of syscalls executed -system.cpu1.kern.syscall_2 2 1.75% 1.75% # number of syscalls executed -system.cpu1.kern.syscall_3 12 10.53% 12.28% # number of syscalls executed -system.cpu1.kern.syscall_4 1 0.88% 13.16% # number of syscalls executed -system.cpu1.kern.syscall_6 13 11.40% 24.56% # number of syscalls executed -system.cpu1.kern.syscall_17 6 5.26% 29.82% # number of syscalls executed -system.cpu1.kern.syscall_19 4 3.51% 33.33% # number of syscalls executed -system.cpu1.kern.syscall_20 2 1.75% 35.09% # number of syscalls executed -system.cpu1.kern.syscall_23 2 1.75% 36.84% # number of syscalls executed -system.cpu1.kern.syscall_24 2 1.75% 38.60% # number of syscalls executed -system.cpu1.kern.syscall_33 4 3.51% 42.11% # number of syscalls executed -system.cpu1.kern.syscall_45 18 15.79% 57.89% # number of syscalls executed -system.cpu1.kern.syscall_47 2 1.75% 59.65% # number of syscalls executed -system.cpu1.kern.syscall_48 3 2.63% 62.28% # number of syscalls executed -system.cpu1.kern.syscall_54 1 0.88% 63.16% # number of syscalls executed -system.cpu1.kern.syscall_59 2 1.75% 64.91% # number of syscalls executed -system.cpu1.kern.syscall_71 26 22.81% 87.72% # number of syscalls executed -system.cpu1.kern.syscall_74 8 7.02% 94.74% # number of syscalls executed -system.cpu1.kern.syscall_90 1 0.88% 95.61% # number of syscalls executed -system.cpu1.kern.syscall_92 2 1.75% 97.37% # number of syscalls executed -system.cpu1.kern.syscall_132 2 1.75% 99.12% # number of syscalls executed -system.cpu1.kern.syscall_144 1 0.88% 100.00% # number of syscalls executed -system.cpu1.not_idle_fraction 0.013720 # Percentage of non-idle cycles -system.cpu1.numCycles 3937427018 # number of cpu cycles simulated -system.cpu1.num_insts 13819748 # Number of instructions executed -system.cpu1.num_refs 4429865 # Number of memory references +system.cpu1.kern.mode_switch_good_idle 0.150950 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks_kernel 18907561000 0.96% 0.96% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 1758275000 0.09% 1.05% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 1946898010000 98.95% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2034 # number of times the context was actually changed +system.cpu1.kern.syscall 104 # number of syscalls executed +system.cpu1.kern.syscall_3 11 10.58% 10.58% # number of syscalls executed +system.cpu1.kern.syscall_6 10 9.62% 20.19% # number of syscalls executed +system.cpu1.kern.syscall_15 1 0.96% 21.15% # number of syscalls executed +system.cpu1.kern.syscall_17 6 5.77% 26.92% # number of syscalls executed +system.cpu1.kern.syscall_23 3 2.88% 29.81% # number of syscalls executed +system.cpu1.kern.syscall_24 3 2.88% 32.69% # number of syscalls executed +system.cpu1.kern.syscall_33 4 3.85% 36.54% # number of syscalls executed +system.cpu1.kern.syscall_45 18 17.31% 53.85% # number of syscalls executed +system.cpu1.kern.syscall_47 3 2.88% 56.73% # number of syscalls executed +system.cpu1.kern.syscall_59 1 0.96% 57.69% # number of syscalls executed +system.cpu1.kern.syscall_71 31 29.81% 87.50% # number of syscalls executed +system.cpu1.kern.syscall_74 10 9.62% 97.12% # number of syscalls executed +system.cpu1.kern.syscall_132 3 2.88% 100.00% # number of syscalls executed +system.cpu1.not_idle_fraction 0.013029 # Percentage of non-idle cycles +system.cpu1.numCycles 3935129140 # number of cpu cycles simulated +system.cpu1.num_insts 13378779 # Number of instructions executed +system.cpu1.num_refs 4274734 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -553,46 +543,46 @@ system.iocache.ReadReq_mshr_miss_latency 10655998 # nu system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_misses 175 # number of ReadReq MSHR misses system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_avg_miss_latency 105505.867491 # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 54505.867491 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 4383979806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_miss_latency 105454.197295 # average WriteReq miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 54454.197295 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 4381832806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 2264827806 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 2262680806 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles_no_mshrs 4141.941655 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles_no_mshrs 4142.720490 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked_no_mshrs 10455 # number of cycles access was blocked +system.iocache.blocked_no_mshrs 10454 # number of cycles access was blocked system.iocache.blocked_no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles_no_mshrs 43304000 # number of cycles access was blocked +system.iocache.blocked_cycles_no_mshrs 43308000 # number of cycles access was blocked system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses 41727 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency 105532.648022 # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 54532.648022 # average overall mshr miss latency +system.iocache.demand_avg_miss_latency 105481.194526 # average overall miss latency +system.iocache.demand_avg_mshr_miss_latency 54481.194526 # average overall mshr miss latency system.iocache.demand_hits 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 4403560804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 4401413804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate 1 # miss rate for demand accesses system.iocache.demand_misses 41727 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 2275483804 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 2273336804 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_misses 41727 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.overall_accesses 41727 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency 105532.648022 # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 54532.648022 # average overall mshr miss latency +system.iocache.overall_avg_miss_latency 105481.194526 # average overall miss latency +system.iocache.overall_avg_mshr_miss_latency 54481.194526 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.iocache.overall_hits 0 # number of overall hits -system.iocache.overall_miss_latency 4403560804 # number of overall miss cycles +system.iocache.overall_miss_latency 4401413804 # number of overall miss cycles system.iocache.overall_miss_rate 1 # miss rate for overall accesses system.iocache.overall_misses 41727 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 2275483804 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 2273336804 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_misses 41727 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -609,83 +599,80 @@ system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 system.iocache.replacements 41695 # number of replacements system.iocache.sampled_refs 41711 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 0.562039 # Cycle average of tags in use +system.iocache.tagsinuse 0.560948 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1762254240000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1761273445000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41520 # number of writebacks -system.l2c.ReadExReq_accesses 298681 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 22003.204087 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 11003.204087 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 6571939000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_accesses 298209 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 22002.897297 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 11002.897297 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 6561462000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 298681 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 3286448000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_misses 298209 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 3281163000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 298681 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 2725193 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 22011.801458 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 11011.571105 # average ReadReq mshr miss latency +system.l2c.ReadExReq_mshr_misses 298209 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2724381 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 22012.979111 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 11012.739257 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits 1631218 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 24080360500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.401430 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 1093975 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 12 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12046383500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.401430 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 1093975 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 780521500 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses 125684 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 20919.070844 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 11005.645110 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 2629192500 # number of UpgradeReq miss cycles +system.l2c.ReadReq_hits 1761295 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 21200392000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.353506 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 963086 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 10606215000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.353506 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 963086 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 779851500 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses 125538 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 20917.475187 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 11004.970607 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 2625938000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 125684 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 1383233500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_misses 125538 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 1381542000 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 125684 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 125538 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1544552000 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses 417692 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.l2c.Writeback_misses 417692 # number of Writeback misses -system.l2c.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses -system.l2c.Writeback_mshr_misses 417692 # number of Writeback MSHR misses +system.l2c.WriteReq_mshr_uncacheable_latency 1544669500 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses 416933 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 416933 # number of Writeback hits system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_refs 1.712431 # Average number of references to valid blocks. +system.l2c.avg_refs 1.775459 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 3023874 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 22009.957592 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 11009.776643 # average overall mshr miss latency -system.l2c.demand_hits 1631218 # number of demand (read+write) hits -system.l2c.demand_miss_latency 30652299500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.460554 # miss rate for demand accesses -system.l2c.demand_misses 1392656 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 12 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 15332831500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.460554 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 1392656 # number of demand (read+write) MSHR misses +system.l2c.demand_accesses 3022590 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 22010.595459 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 11010.412314 # average overall mshr miss latency +system.l2c.demand_hits 1761295 # number of demand (read+write) hits +system.l2c.demand_miss_latency 27761854000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.417289 # miss rate for demand accesses +system.l2c.demand_misses 1261295 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 13887378000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.417289 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 1261295 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 3023874 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 22009.957592 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 11009.776643 # average overall mshr miss latency +system.l2c.overall_accesses 3022590 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 22010.595459 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 11010.412314 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits 1631218 # number of overall hits -system.l2c.overall_miss_latency 30652299500 # number of overall miss cycles -system.l2c.overall_miss_rate 0.460554 # miss rate for overall accesses -system.l2c.overall_misses 1392656 # number of overall misses -system.l2c.overall_mshr_hits 12 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 15332831500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.460554 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 1392656 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 2325073500 # number of overall MSHR uncacheable cycles +system.l2c.overall_hits 1761295 # number of overall hits +system.l2c.overall_miss_latency 27761854000 # number of overall miss cycles +system.l2c.overall_miss_rate 0.417289 # miss rate for overall accesses +system.l2c.overall_misses 1261295 # number of overall misses +system.l2c.overall_mshr_hits 11 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 13887378000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.417289 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 1261295 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 2324521000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -696,13 +683,13 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 947581 # number of replacements -system.l2c.sampled_refs 965893 # Sample count of references to valid blocks. +system.l2c.replacements 1055639 # number of replacements +system.l2c.sampled_refs 1086732 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 16478.368484 # Cycle average of tags in use -system.l2c.total_refs 1654025 # Total number of references to valid blocks. -system.l2c.warmup_cycle 6949110000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 0 # number of writebacks +system.l2c.tagsinuse 31212.139873 # Cycle average of tags in use +system.l2c.total_refs 1929448 # Total number of references to valid blocks. +system.l2c.warmup_cycle 6911380000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 123289 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr index 0cdc8845e..911cefcd6 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr @@ -1,5 +1,6 @@ +warn: kernel located at: /dist/m5/system/binaries/vmlinux Listening for system connection on port 3456 0: system.remote_gdb.listener: listening for remote gdb on port 7000 0: system.remote_gdb.listener: listening for remote gdb on port 7001 warn: Entering event queue @ 0. Starting simulation... -warn: 470073000: Trying to launch CPU number 1! +warn: 469929000: Trying to launch CPU number 1! diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout index 6f89d18ec..91bc31701 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 14 2007 18:18:39 -M5 started Tue Aug 14 18:20:39 2007 -M5 executing on nacho +M5 compiled Feb 13 2008 00:33:19 +M5 started Wed Feb 13 00:40:52 2008 +M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1968713509000 because m5_exit instruction encountered +Exiting @ tick 1967564570000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt index 1b62f3b23..2430e4b42 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt @@ -1,92 +1,92 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1046777 # Simulator instruction rate (inst/s) -host_mem_usage 284980 # Number of bytes of host memory used -host_seconds 57.37 # Real time elapsed on the host -host_tick_rate 33615024315 # Simulator tick rate (ticks/s) +host_inst_rate 696140 # Simulator instruction rate (inst/s) +host_mem_usage 250636 # Number of bytes of host memory used +host_seconds 86.29 # Real time elapsed on the host +host_tick_rate 22338313409 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 60057633 # Number of instructions simulated -sim_seconds 1.928634 # Number of seconds simulated -sim_ticks 1928634086000 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses 200253 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 24764.285714 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 22764.285714 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits 183033 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 426441000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate 0.085991 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 17220 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 392001000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.085991 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 17220 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses 9530639 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 20452.825113 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18452.799311 # average ReadReq mshr miss latency +sim_insts 60068732 # Number of instructions simulated +sim_seconds 1.927543 # Number of seconds simulated +sim_ticks 1927543019000 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses 200271 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency 13100.266914 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11100.266914 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits 183037 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 225770000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate 0.086053 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses 17234 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 191302000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.086053 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_misses 17234 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses 9532729 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 19595.012234 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17594.985853 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits 7805929 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 35275192000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.180965 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1724710 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 31825727500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.180965 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1724710 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_hits 7808009 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 33795909500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.180926 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1724720 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 30346424000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.180926 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1724720 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable_latency 830826000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses 199230 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_avg_miss_latency 25001.705115 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 23001.705115 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_hits 169320 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_latency 747801000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_rate 0.150128 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses 29910 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_mshr_miss_latency 687981000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.150128 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_misses 29910 # number of StoreCondReq MSHR misses -system.cpu.dcache.WriteReq_accesses 6154215 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 25004.189365 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23004.189365 # average WriteReq mshr miss latency +system.cpu.dcache.StoreCondReq_accesses 199250 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_avg_miss_latency 25002.710390 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 23002.710390 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits 169365 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_latency 747206000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_rate 0.149987 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses 29885 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_mshr_miss_latency 687436000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.149987 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_misses 29885 # number of StoreCondReq MSHR misses +system.cpu.dcache.WriteReq_accesses 6155089 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 25003.901042 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23003.901042 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits 5753677 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 10015128000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.065084 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 400538 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 9214052000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.065084 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 400538 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1165152000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_hits 5754555 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 10014912500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.065074 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 400534 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 9213844500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.065074 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 400534 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1165071500 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 6.860327 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 6.861521 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 15684854 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 21310.604692 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 19310.583753 # average overall mshr miss latency -system.cpu.dcache.demand_hits 13559606 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 45290320000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.135497 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2125248 # number of demand (read+write) misses +system.cpu.dcache.demand_accesses 15687818 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 20614.393385 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 18614.371976 # average overall mshr miss latency +system.cpu.dcache.demand_hits 13562564 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 43810822000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.135472 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2125254 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 41039779500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.135497 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2125248 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 39560268500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.135472 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2125254 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 15684854 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 21310.604692 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 19310.583753 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 15687818 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 20614.393385 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 18614.371976 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 13559606 # number of overall hits -system.cpu.dcache.overall_miss_latency 45290320000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.135497 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2125248 # number of overall misses +system.cpu.dcache.overall_hits 13562564 # number of overall hits +system.cpu.dcache.overall_miss_latency 43810822000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.135472 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2125254 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 41039779500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.135497 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2125248 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 1995978000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_miss_latency 39560268500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.135472 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2125254 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 1995897500 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -97,69 +97,69 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 2045756 # number of replacements -system.cpu.dcache.sampled_refs 2046268 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 2045827 # number of replacements +system.cpu.dcache.sampled_refs 2046339 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.986953 # Cycle average of tags in use -system.cpu.dcache.total_refs 14038068 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 511.986919 # Cycle average of tags in use +system.cpu.dcache.total_refs 14040998 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 65018000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 430050 # number of writebacks -system.cpu.dtb.accesses 1020787 # DTB accesses -system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 16064914 # DTB hits -system.cpu.dtb.misses 11471 # DTB misses -system.cpu.dtb.read_accesses 728856 # DTB read accesses +system.cpu.dcache.writebacks 430020 # number of writebacks +system.cpu.dtb.accesses 1021777 # DTB accesses +system.cpu.dtb.acv 373 # DTB access violations +system.cpu.dtb.hits 16067843 # DTB hits +system.cpu.dtb.misses 11527 # DTB misses +system.cpu.dtb.read_accesses 729481 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 9711316 # DTB read hits -system.cpu.dtb.read_misses 10329 # DTB read misses -system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_hits 6353598 # DTB write hits -system.cpu.dtb.write_misses 1142 # DTB write misses -system.cpu.icache.ReadReq_accesses 60069472 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 13194.961147 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11194.230809 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 59140451 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 12258396000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.015466 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 929021 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 10399675500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.015466 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 929021 # number of ReadReq MSHR misses +system.cpu.dtb.read_hits 9713362 # DTB read hits +system.cpu.dtb.read_misses 10376 # DTB read misses +system.cpu.dtb.write_accesses 292296 # DTB write accesses +system.cpu.dtb.write_acv 163 # DTB write access violations +system.cpu.dtb.write_hits 6354481 # DTB write hits +system.cpu.dtb.write_misses 1151 # DTB write misses +system.cpu.icache.ReadReq_accesses 60080633 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 13203.991500 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11203.259450 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 59151734 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 12265174500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.015461 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 928899 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 10406696500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.015461 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 928899 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 63.669861 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 63.690305 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 60069472 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 13194.961147 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11194.230809 # average overall mshr miss latency -system.cpu.icache.demand_hits 59140451 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 12258396000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.015466 # miss rate for demand accesses -system.cpu.icache.demand_misses 929021 # number of demand (read+write) misses +system.cpu.icache.demand_accesses 60080633 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 13203.991500 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11203.259450 # average overall mshr miss latency +system.cpu.icache.demand_hits 59151734 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 12265174500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.015461 # miss rate for demand accesses +system.cpu.icache.demand_misses 928899 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 10399675500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.015466 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 929021 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_latency 10406696500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.015461 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 928899 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 60069472 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 13194.961147 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11194.230809 # average overall mshr miss latency +system.cpu.icache.overall_accesses 60080633 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 13203.991500 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11203.259450 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 59140451 # number of overall hits -system.cpu.icache.overall_miss_latency 12258396000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.015466 # miss rate for overall accesses -system.cpu.icache.overall_misses 929021 # number of overall misses +system.cpu.icache.overall_hits 59151734 # number of overall hits +system.cpu.icache.overall_miss_latency 12265174500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.015461 # miss rate for overall accesses +system.cpu.icache.overall_misses 928899 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 10399675500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.015466 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 929021 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_latency 10406696500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.015461 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 928899 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -171,71 +171,71 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 928350 # number of replacements -system.cpu.icache.sampled_refs 928861 # Sample count of references to valid blocks. +system.cpu.icache.replacements 928229 # number of replacements +system.cpu.icache.sampled_refs 928740 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 507.520799 # Cycle average of tags in use -system.cpu.icache.total_refs 59140451 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 46942784000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tagsinuse 507.528659 # Cycle average of tags in use +system.cpu.icache.total_refs 59151734 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 46711592000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0.930621 # Percentage of idle cycles -system.cpu.itb.accesses 4979706 # ITB accesses +system.cpu.idle_fraction 0.931443 # Percentage of idle cycles +system.cpu.itb.accesses 4984781 # ITB accesses system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 4974700 # ITB hits -system.cpu.itb.misses 5006 # ITB misses -system.cpu.kern.callpal 192925 # number of callpals executed +system.cpu.itb.hits 4979736 # ITB hits +system.cpu.itb.misses 5045 # ITB misses +system.cpu.kern.callpal 192951 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_swpctx 4173 2.16% 2.17% # number of callpals executed -system.cpu.kern.callpal_tbi 54 0.03% 2.19% # number of callpals executed +system.cpu.kern.callpal_swpctx 4179 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal_tbi 55 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal_swpipl 175980 91.22% 93.41% # number of callpals executed -system.cpu.kern.callpal_rdps 6834 3.54% 96.96% # number of callpals executed -system.cpu.kern.callpal_wrkgp 1 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal_swpipl 175991 91.21% 93.41% # number of callpals executed +system.cpu.kern.callpal_rdps 6833 3.54% 96.95% # number of callpals executed +system.cpu.kern.callpal_wrkgp 1 0.00% 96.95% # number of callpals executed system.cpu.kern.callpal_wrusp 7 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal_rdusp 9 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal_whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal_rti 5158 2.67% 99.64% # number of callpals executed -system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed +system.cpu.kern.callpal_whami 2 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal_rti 5165 2.68% 99.64% # number of callpals executed +system.cpu.kern.callpal_callsys 517 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 212019 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6178 # number of quiesce instructions executed -system.cpu.kern.ipl_count 183203 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 74905 40.89% 40.89% # number of times we switched to this ipl -system.cpu.kern.ipl_count_21 131 0.07% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count_22 1933 1.06% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 106234 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 149140 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 73538 49.31% 49.31% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_22 1933 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 73538 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 1928633340000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 1858526897500 96.36% 96.36% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 84112500 0.00% 96.37% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 547765000 0.03% 96.40% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 69474565000 3.60% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used_0 0.981750 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.hwrei 212145 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6176 # number of quiesce instructions executed +system.cpu.kern.ipl_count 183220 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 74917 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.ipl_count_21 132 0.07% 40.96% # number of times we switched to this ipl +system.cpu.kern.ipl_count_22 1932 1.05% 42.02% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 106239 57.98% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 149165 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 73550 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_21 132 0.09% 49.40% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_31 73551 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 1927542285000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 1858193951000 96.40% 96.40% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 83622500 0.00% 96.41% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 547930500 0.03% 96.44% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 68716781000 3.56% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used_0 0.981753 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.692227 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1906 -system.cpu.kern.mode_good_user 1738 +system.cpu.kern.ipl_used_31 0.692316 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1915 +system.cpu.kern.mode_good_user 1747 system.cpu.kern.mode_good_idle 168 -system.cpu.kern.mode_switch_kernel 5905 # number of protection mode switches -system.cpu.kern.mode_switch_user 1738 # number of protection mode switches -system.cpu.kern.mode_switch_idle 2092 # number of protection mode switches -system.cpu.kern.mode_switch_good 1.403083 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.322777 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_kernel 5911 # number of protection mode switches +system.cpu.kern.mode_switch_user 1747 # number of protection mode switches +system.cpu.kern.mode_switch_idle 2099 # number of protection mode switches +system.cpu.kern.mode_switch_good 1.404010 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.323972 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_idle 0.080306 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 44913865000 2.33% 2.33% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 5020516000 0.26% 2.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 1878698957000 97.41% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4174 # number of times the context was actually changed +system.cpu.kern.mode_switch_good_idle 0.080038 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks_kernel 44586957000 2.31% 2.31% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 4962483000 0.26% 2.57% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 1877992843000 97.43% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4180 # number of times the context was actually changed system.cpu.kern.syscall 326 # number of syscalls executed system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed @@ -267,10 +267,10 @@ system.cpu.kern.syscall_98 2 0.61% 97.55% # nu system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed -system.cpu.not_idle_fraction 0.069379 # Percentage of non-idle cycles -system.cpu.numCycles 3857268172 # number of cpu cycles simulated -system.cpu.num_insts 60057633 # Number of instructions executed -system.cpu.num_refs 16313038 # Number of memory references +system.cpu.not_idle_fraction 0.068557 # Percentage of non-idle cycles +system.cpu.numCycles 3855086038 # number of cpu cycles simulated +system.cpu.num_insts 60068732 # Number of instructions executed +system.cpu.num_refs 16316112 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -284,55 +284,55 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iocache.ReadReq_accesses 173 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_avg_miss_latency 111832.358382 # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 60832.358382 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 19346998 # number of ReadReq miss cycles +system.iocache.ReadReq_avg_miss_latency 111884.381503 # average ReadReq miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 60884.381503 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 19355998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.iocache.ReadReq_misses 173 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 10523998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 10532998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_avg_miss_latency 105522.497256 # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 54522.497256 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 4384670806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_miss_latency 105472.006305 # average WriteReq miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 54472.006305 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 4382572806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 2265518806 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 2263420806 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles_no_mshrs 4138.761468 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles_no_mshrs 4141.477870 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked_no_mshrs 10464 # number of cycles access was blocked +system.iocache.blocked_no_mshrs 10461 # number of cycles access was blocked system.iocache.blocked_no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles_no_mshrs 43308000 # number of cycles access was blocked +system.iocache.blocked_cycles_no_mshrs 43324000 # number of cycles access was blocked system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses 41725 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency 105548.659173 # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 54548.659173 # average overall mshr miss latency +system.iocache.demand_avg_miss_latency 105498.593265 # average overall miss latency +system.iocache.demand_avg_mshr_miss_latency 54498.593265 # average overall mshr miss latency system.iocache.demand_hits 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 4404017804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 4401928804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate 1 # miss rate for demand accesses system.iocache.demand_misses 41725 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 2276042804 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 2273953804 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.overall_accesses 41725 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency 105548.659173 # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 54548.659173 # average overall mshr miss latency +system.iocache.overall_avg_miss_latency 105498.593265 # average overall miss latency +system.iocache.overall_avg_mshr_miss_latency 54498.593265 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.iocache.overall_hits 0 # number of overall hits -system.iocache.overall_miss_latency 4404017804 # number of overall miss cycles +system.iocache.overall_miss_latency 4401928804 # number of overall miss cycles system.iocache.overall_miss_rate 1 # miss rate for overall accesses system.iocache.overall_misses 41725 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 2276042804 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 2273953804 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -349,82 +349,79 @@ system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 system.iocache.replacements 41685 # number of replacements system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 1.334892 # Cycle average of tags in use +system.iocache.tagsinuse 1.334772 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1763215764000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1762233995000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses 304339 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 22004.271552 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 11004.271552 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 6696758000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_accesses 304387 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 22004.172320 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 11004.172320 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 6697784000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 304339 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 3349029000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_misses 304387 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 3349527000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 304339 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 2670932 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 22011.408790 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 11011.408790 # average ReadReq mshr miss latency +system.l2c.ReadExReq_mshr_misses 304387 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2670834 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 22012.695417 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 11012.695417 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits 1568887 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 24257563000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.412607 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 1102045 # number of ReadReq misses -system.l2c.ReadReq_mshr_miss_latency 12135068000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.412607 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 1102045 # number of ReadReq MSHR misses +system.l2c.ReadReq_hits 1708085 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 21192700500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.360468 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 962749 # number of ReadReq misses +system.l2c.ReadReq_mshr_miss_latency 10602461500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.360468 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 962749 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_uncacheable_latency 750102000 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses 126109 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 22001.831749 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 11003.401819 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 2774629000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_accesses 126032 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 22001.392503 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 11002.963533 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 2772879500 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 126109 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 1387628000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_misses 126032 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 1386725500 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 126109 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 126032 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1051776000 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses 430050 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.l2c.Writeback_misses 430050 # number of Writeback misses -system.l2c.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses -system.l2c.Writeback_mshr_misses 430050 # number of Writeback MSHR misses +system.l2c.WriteReq_mshr_uncacheable_latency 1051707500 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses 430020 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 430020 # number of Writeback hits system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_refs 1.660494 # Average number of references to valid blocks. +system.l2c.avg_refs 1.742465 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2975271 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 22009.864304 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 11009.864304 # average overall mshr miss latency -system.l2c.demand_hits 1568887 # number of demand (read+write) hits -system.l2c.demand_miss_latency 30954321000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.472691 # miss rate for demand accesses -system.l2c.demand_misses 1406384 # number of demand (read+write) misses +system.l2c.demand_accesses 2975221 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 22010.648028 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 11010.648028 # average overall mshr miss latency +system.l2c.demand_hits 1708085 # number of demand (read+write) hits +system.l2c.demand_miss_latency 27890484500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.425896 # miss rate for demand accesses +system.l2c.demand_misses 1267136 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 15484097000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.472691 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 1406384 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_miss_latency 13951988500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.425896 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 1267136 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 2975271 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 22009.864304 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 11009.864304 # average overall mshr miss latency +system.l2c.overall_accesses 2975221 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 22010.648028 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 11010.648028 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits 1568887 # number of overall hits -system.l2c.overall_miss_latency 30954321000 # number of overall miss cycles -system.l2c.overall_miss_rate 0.472691 # miss rate for overall accesses -system.l2c.overall_misses 1406384 # number of overall misses +system.l2c.overall_hits 1708085 # number of overall hits +system.l2c.overall_miss_latency 27890484500 # number of overall miss cycles +system.l2c.overall_miss_rate 0.425896 # miss rate for overall accesses +system.l2c.overall_misses 1267136 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 15484097000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.472691 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 1406384 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 1801878000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency 13951988500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.425896 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 1267136 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 1801809500 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -435,13 +432,13 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 947158 # number of replacements -system.l2c.sampled_refs 965422 # Sample count of references to valid blocks. +system.l2c.replacements 1050150 # number of replacements +system.l2c.sampled_refs 1081111 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 16013.674144 # Cycle average of tags in use -system.l2c.total_refs 1603077 # Total number of references to valid blocks. -system.l2c.warmup_cycle 4984882000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 0 # number of writebacks +system.l2c.tagsinuse 30789.729249 # Cycle average of tags in use +system.l2c.total_refs 1883798 # Total number of references to valid blocks. +system.l2c.warmup_cycle 4791566000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 118721 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr index 072cb6c8c..7e35fafed 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr @@ -1,3 +1,4 @@ +warn: kernel located at: /dist/m5/system/binaries/vmlinux Listening for system connection on port 3456 0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout index 73f1f9652..192a1f496 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 14 2007 18:18:39 -M5 started Tue Aug 14 18:19:37 2007 -M5 executing on nacho +M5 compiled Feb 13 2008 00:33:19 +M5 started Wed Feb 13 00:39:25 2008 +M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1928634086000 because m5_exit instruction encountered +Exiting @ tick 1927543019000 because m5_exit instruction encountered diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt index 19f13b80b..8a8c21ab1 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt @@ -1,70 +1,70 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 368552 # Number of bytes of host memory used -host_seconds 153.46 # Real time elapsed on the host -host_tick_rate 1061945 # Simulator tick rate (ticks/s) +host_mem_usage 323008 # Number of bytes of host memory used +host_seconds 186.85 # Real time elapsed on the host +host_tick_rate 602387 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_seconds 0.000163 # Number of seconds simulated -sim_ticks 162969030 # Number of ticks simulated -system.cpu0.l1c.ReadReq_accesses 44649 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_avg_miss_latency 23666.382848 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 22664.543419 # average ReadReq mshr miss latency +sim_seconds 0.000113 # Number of seconds simulated +sim_ticks 112555067 # Number of ticks simulated +system.cpu0.l1c.ReadReq_accesses 44584 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_avg_miss_latency 16791.681399 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 15789.838066 # average ReadReq mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_hits 7488 # number of ReadReq hits -system.cpu0.l1c.ReadReq_miss_latency 879466453 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_rate 0.832292 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_misses 37161 # number of ReadReq misses -system.cpu0.l1c.ReadReq_mshr_miss_latency 842237098 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate 0.832292 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_misses 37161 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency 472367401 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_accesses 24088 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_avg_miss_latency 28277.359652 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 27275.445460 # average WriteReq mshr miss latency +system.cpu0.l1c.ReadReq_hits 7569 # number of ReadReq hits +system.cpu0.l1c.ReadReq_miss_latency 621544087 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_rate 0.830231 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_misses 37015 # number of ReadReq misses +system.cpu0.l1c.ReadReq_mshr_miss_latency 584460856 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate 0.830231 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_misses 37015 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency 311047382 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_accesses 24314 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_avg_miss_latency 20326.593908 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 19324.632455 # average WriteReq mshr miss latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_hits 885 # number of WriteReq hits -system.cpu0.l1c.WriteReq_miss_latency 656119576 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_rate 0.963260 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_misses 23203 # number of WriteReq misses -system.cpu0.l1c.WriteReq_mshr_miss_latency 632872161 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_rate 0.963260 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_misses 23203 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency 285830278 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.avg_blocked_cycles_no_mshrs 2295.113017 # average number of cycles each access was blocked +system.cpu0.l1c.WriteReq_hits 940 # number of WriteReq hits +system.cpu0.l1c.WriteReq_miss_latency 475113806 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_rate 0.961339 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_misses 23374 # number of WriteReq misses +system.cpu0.l1c.WriteReq_mshr_miss_latency 451693959 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_rate 0.961339 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_misses 23374 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency 197852033 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.avg_blocked_cycles_no_mshrs 1596.131819 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu0.l1c.avg_refs 0.412189 # Average number of references to valid blocks. -system.cpu0.l1c.blocked_no_mshrs 69538 # number of cycles access was blocked +system.cpu0.l1c.avg_refs 0.411842 # Average number of references to valid blocks. +system.cpu0.l1c.blocked_no_mshrs 69641 # number of cycles access was blocked system.cpu0.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked_cycles_no_mshrs 159597569 # number of cycles access was blocked +system.cpu0.l1c.blocked_cycles_no_mshrs 111156216 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.demand_accesses 68737 # number of demand (read+write) accesses -system.cpu0.l1c.demand_avg_miss_latency 25438.771934 # average overall miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency 24436.903767 # average overall mshr miss latency -system.cpu0.l1c.demand_hits 8373 # number of demand (read+write) hits -system.cpu0.l1c.demand_miss_latency 1535586029 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_rate 0.878188 # miss rate for demand accesses -system.cpu0.l1c.demand_misses 60364 # number of demand (read+write) misses +system.cpu0.l1c.demand_accesses 68898 # number of demand (read+write) accesses +system.cpu0.l1c.demand_avg_miss_latency 18159.894898 # average overall miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency 17158.005845 # average overall mshr miss latency +system.cpu0.l1c.demand_hits 8509 # number of demand (read+write) hits +system.cpu0.l1c.demand_miss_latency 1096657893 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_rate 0.876499 # miss rate for demand accesses +system.cpu0.l1c.demand_misses 60389 # number of demand (read+write) misses system.cpu0.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.l1c.demand_mshr_miss_latency 1475109259 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_rate 0.878188 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_misses 60364 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_miss_latency 1036154815 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_rate 0.876499 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_misses 60389 # number of demand (read+write) MSHR misses system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l1c.overall_accesses 68737 # number of overall (read+write) accesses -system.cpu0.l1c.overall_avg_miss_latency 25438.771934 # average overall miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency 24436.903767 # average overall mshr miss latency +system.cpu0.l1c.overall_accesses 68898 # number of overall (read+write) accesses +system.cpu0.l1c.overall_avg_miss_latency 18159.894898 # average overall miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency 17158.005845 # average overall mshr miss latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.l1c.overall_hits 8373 # number of overall hits -system.cpu0.l1c.overall_miss_latency 1535586029 # number of overall miss cycles -system.cpu0.l1c.overall_miss_rate 0.878188 # miss rate for overall accesses -system.cpu0.l1c.overall_misses 60364 # number of overall misses +system.cpu0.l1c.overall_hits 8509 # number of overall hits +system.cpu0.l1c.overall_miss_latency 1096657893 # number of overall miss cycles +system.cpu0.l1c.overall_miss_rate 0.876499 # miss rate for overall accesses +system.cpu0.l1c.overall_misses 60389 # number of overall misses system.cpu0.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.l1c.overall_mshr_miss_latency 1475109259 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_rate 0.878188 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_misses 60364 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_uncacheable_latency 758197679 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_miss_latency 1036154815 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_rate 0.876499 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_misses 60389 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_uncacheable_latency 508899415 # number of overall MSHR uncacheable cycles system.cpu0.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu0.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -75,75 +75,75 @@ system.cpu0.l1c.prefetcher.num_hwpf_issued 0 # system.cpu0.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu0.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l1c.replacements 27517 # number of replacements -system.cpu0.l1c.sampled_refs 27861 # Sample count of references to valid blocks. +system.cpu0.l1c.replacements 27835 # number of replacements +system.cpu0.l1c.sampled_refs 28188 # Sample count of references to valid blocks. system.cpu0.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.l1c.tagsinuse 345.121888 # Cycle average of tags in use -system.cpu0.l1c.total_refs 11484 # Total number of references to valid blocks. +system.cpu0.l1c.tagsinuse 346.302314 # Cycle average of tags in use +system.cpu0.l1c.total_refs 11609 # Total number of references to valid blocks. system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.writebacks 10876 # number of writebacks +system.cpu0.l1c.writebacks 10966 # number of writebacks system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 99133 # number of read accesses completed -system.cpu0.num_writes 53626 # number of write accesses completed -system.cpu1.l1c.ReadReq_accesses 44934 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_avg_miss_latency 23743.367678 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 22741.526988 # average ReadReq mshr miss latency +system.cpu0.num_reads 98907 # number of read accesses completed +system.cpu0.num_writes 53498 # number of write accesses completed +system.cpu1.l1c.ReadReq_accesses 44625 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_avg_miss_latency 16739.803812 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 15737.959508 # average ReadReq mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_hits 7510 # number of ReadReq hits -system.cpu1.l1c.ReadReq_miss_latency 888571792 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_rate 0.832866 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_misses 37424 # number of ReadReq misses -system.cpu1.l1c.ReadReq_mshr_miss_latency 851078906 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate 0.832866 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_misses 37424 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency 461314055 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_accesses 24224 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_avg_miss_latency 28268.157373 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 27266.371925 # average WriteReq mshr miss latency +system.cpu1.l1c.ReadReq_hits 7482 # number of ReadReq hits +system.cpu1.l1c.ReadReq_miss_latency 621766533 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_rate 0.832336 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_misses 37143 # number of ReadReq misses +system.cpu1.l1c.ReadReq_mshr_miss_latency 584555030 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate 0.832336 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_misses 37143 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency 314667115 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_accesses 24302 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_avg_miss_latency 20215.551692 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 19213.676756 # average WriteReq mshr miss latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_hits 929 # number of WriteReq hits -system.cpu1.l1c.WriteReq_miss_latency 658506726 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_rate 0.961650 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_misses 23295 # number of WriteReq misses -system.cpu1.l1c.WriteReq_mshr_miss_latency 635170134 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_rate 0.961650 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_misses 23295 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency 280215693 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.avg_blocked_cycles_no_mshrs 2295.300422 # average number of cycles each access was blocked +system.cpu1.l1c.WriteReq_hits 1010 # number of WriteReq hits +system.cpu1.l1c.WriteReq_miss_latency 470860630 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_rate 0.958440 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_misses 23292 # number of WriteReq misses +system.cpu1.l1c.WriteReq_mshr_miss_latency 447524959 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_rate 0.958440 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_misses 23292 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency 196094106 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.avg_blocked_cycles_no_mshrs 1590.812213 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu1.l1c.avg_refs 0.407660 # Average number of references to valid blocks. -system.cpu1.l1c.blocked_no_mshrs 69592 # number of cycles access was blocked +system.cpu1.l1c.avg_refs 0.412303 # Average number of references to valid blocks. +system.cpu1.l1c.blocked_no_mshrs 69797 # number of cycles access was blocked system.cpu1.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked_cycles_no_mshrs 159734547 # number of cycles access was blocked +system.cpu1.l1c.blocked_cycles_no_mshrs 111033920 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.demand_accesses 69158 # number of demand (read+write) accesses -system.cpu1.l1c.demand_avg_miss_latency 25479.314844 # average overall miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency 24477.495347 # average overall mshr miss latency -system.cpu1.l1c.demand_hits 8439 # number of demand (read+write) hits -system.cpu1.l1c.demand_miss_latency 1547078518 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_rate 0.877975 # miss rate for demand accesses -system.cpu1.l1c.demand_misses 60719 # number of demand (read+write) misses +system.cpu1.l1c.demand_accesses 68927 # number of demand (read+write) accesses +system.cpu1.l1c.demand_avg_miss_latency 18079.377232 # average overall miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency 17077.521122 # average overall mshr miss latency +system.cpu1.l1c.demand_hits 8492 # number of demand (read+write) hits +system.cpu1.l1c.demand_miss_latency 1092627163 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_rate 0.876797 # miss rate for demand accesses +system.cpu1.l1c.demand_misses 60435 # number of demand (read+write) misses system.cpu1.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.l1c.demand_mshr_miss_latency 1486249040 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_rate 0.877975 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_misses 60719 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_miss_latency 1032079989 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_rate 0.876797 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_misses 60435 # number of demand (read+write) MSHR misses system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l1c.overall_accesses 69158 # number of overall (read+write) accesses -system.cpu1.l1c.overall_avg_miss_latency 25479.314844 # average overall miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency 24477.495347 # average overall mshr miss latency +system.cpu1.l1c.overall_accesses 68927 # number of overall (read+write) accesses +system.cpu1.l1c.overall_avg_miss_latency 18079.377232 # average overall miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency 17077.521122 # average overall mshr miss latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.l1c.overall_hits 8439 # number of overall hits -system.cpu1.l1c.overall_miss_latency 1547078518 # number of overall miss cycles -system.cpu1.l1c.overall_miss_rate 0.877975 # miss rate for overall accesses -system.cpu1.l1c.overall_misses 60719 # number of overall misses +system.cpu1.l1c.overall_hits 8492 # number of overall hits +system.cpu1.l1c.overall_miss_latency 1092627163 # number of overall miss cycles +system.cpu1.l1c.overall_miss_rate 0.876797 # miss rate for overall accesses +system.cpu1.l1c.overall_misses 60435 # number of overall misses system.cpu1.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.l1c.overall_mshr_miss_latency 1486249040 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_rate 0.877975 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_misses 60719 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_uncacheable_latency 741529748 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_miss_latency 1032079989 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_rate 0.876797 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_misses 60435 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_uncacheable_latency 510761221 # number of overall MSHR uncacheable cycles system.cpu1.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu1.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu1.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -154,75 +154,75 @@ system.cpu1.l1c.prefetcher.num_hwpf_issued 0 # system.cpu1.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu1.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l1c.replacements 27839 # number of replacements -system.cpu1.l1c.sampled_refs 28200 # Sample count of references to valid blocks. +system.cpu1.l1c.replacements 27754 # number of replacements +system.cpu1.l1c.sampled_refs 28108 # Sample count of references to valid blocks. system.cpu1.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.l1c.tagsinuse 344.387684 # Cycle average of tags in use -system.cpu1.l1c.total_refs 11496 # Total number of references to valid blocks. +system.cpu1.l1c.tagsinuse 346.756421 # Cycle average of tags in use +system.cpu1.l1c.total_refs 11589 # Total number of references to valid blocks. system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.writebacks 10966 # number of writebacks +system.cpu1.l1c.writebacks 11009 # number of writebacks system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99887 # number of read accesses completed -system.cpu1.num_writes 53581 # number of write accesses completed -system.cpu2.l1c.ReadReq_accesses 44676 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_avg_miss_latency 23702.165485 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 22700.326495 # average ReadReq mshr miss latency +system.cpu1.num_reads 99307 # number of read accesses completed +system.cpu1.num_writes 53968 # number of write accesses completed +system.cpu2.l1c.ReadReq_accesses 44798 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_avg_miss_latency 16757.356387 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 15755.538278 # average ReadReq mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_hits 7579 # number of ReadReq hits -system.cpu2.l1c.ReadReq_miss_latency 879279233 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_rate 0.830356 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_misses 37097 # number of ReadReq misses -system.cpu2.l1c.ReadReq_mshr_miss_latency 842114012 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate 0.830356 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_misses 37097 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency 463945660 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_accesses 24311 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_avg_miss_latency 28427.205208 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 27425.376280 # average WriteReq mshr miss latency +system.cpu2.l1c.ReadReq_hits 7479 # number of ReadReq hits +system.cpu2.l1c.ReadReq_miss_latency 625367783 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_rate 0.833051 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_misses 37319 # number of ReadReq misses +system.cpu2.l1c.ReadReq_mshr_miss_latency 587980933 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate 0.833051 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_misses 37319 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency 312913561 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_accesses 24115 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_avg_miss_latency 20248.523869 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 19246.649160 # average WriteReq mshr miss latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_hits 964 # number of WriteReq hits -system.cpu2.l1c.WriteReq_miss_latency 663689960 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_rate 0.960347 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_misses 23347 # number of WriteReq misses -system.cpu2.l1c.WriteReq_mshr_miss_latency 640300260 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_rate 0.960347 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_misses 23347 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency 293541767 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.avg_blocked_cycles_no_mshrs 2298.353100 # average number of cycles each access was blocked +system.cpu2.l1c.WriteReq_hits 905 # number of WriteReq hits +system.cpu2.l1c.WriteReq_miss_latency 469968239 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_rate 0.962471 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_misses 23210 # number of WriteReq misses +system.cpu2.l1c.WriteReq_mshr_miss_latency 446714727 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_rate 0.962471 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_misses 23210 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency 194813468 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.avg_blocked_cycles_no_mshrs 1594.588395 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu2.l1c.avg_refs 0.415183 # Average number of references to valid blocks. -system.cpu2.l1c.blocked_no_mshrs 69275 # number of cycles access was blocked +system.cpu2.l1c.avg_refs 0.408059 # Average number of references to valid blocks. +system.cpu2.l1c.blocked_no_mshrs 69812 # number of cycles access was blocked system.cpu2.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked_cycles_no_mshrs 159218411 # number of cycles access was blocked +system.cpu2.l1c.blocked_cycles_no_mshrs 111321405 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.demand_accesses 68987 # number of demand (read+write) accesses -system.cpu2.l1c.demand_avg_miss_latency 25527.251555 # average overall miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency 24525.416452 # average overall mshr miss latency -system.cpu2.l1c.demand_hits 8543 # number of demand (read+write) hits -system.cpu2.l1c.demand_miss_latency 1542969193 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_rate 0.876165 # miss rate for demand accesses -system.cpu2.l1c.demand_misses 60444 # number of demand (read+write) misses +system.cpu2.l1c.demand_accesses 68913 # number of demand (read+write) accesses +system.cpu2.l1c.demand_avg_miss_latency 18096.053495 # average overall miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency 17094.213683 # average overall mshr miss latency +system.cpu2.l1c.demand_hits 8384 # number of demand (read+write) hits +system.cpu2.l1c.demand_miss_latency 1095336022 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_rate 0.878339 # miss rate for demand accesses +system.cpu2.l1c.demand_misses 60529 # number of demand (read+write) misses system.cpu2.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.l1c.demand_mshr_miss_latency 1482414272 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_rate 0.876165 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_misses 60444 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_miss_latency 1034695660 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_rate 0.878339 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_misses 60529 # number of demand (read+write) MSHR misses system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.l1c.overall_accesses 68987 # number of overall (read+write) accesses -system.cpu2.l1c.overall_avg_miss_latency 25527.251555 # average overall miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency 24525.416452 # average overall mshr miss latency +system.cpu2.l1c.overall_accesses 68913 # number of overall (read+write) accesses +system.cpu2.l1c.overall_avg_miss_latency 18096.053495 # average overall miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency 17094.213683 # average overall mshr miss latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu2.l1c.overall_hits 8543 # number of overall hits -system.cpu2.l1c.overall_miss_latency 1542969193 # number of overall miss cycles -system.cpu2.l1c.overall_miss_rate 0.876165 # miss rate for overall accesses -system.cpu2.l1c.overall_misses 60444 # number of overall misses +system.cpu2.l1c.overall_hits 8384 # number of overall hits +system.cpu2.l1c.overall_miss_latency 1095336022 # number of overall miss cycles +system.cpu2.l1c.overall_miss_rate 0.878339 # miss rate for overall accesses +system.cpu2.l1c.overall_misses 60529 # number of overall misses system.cpu2.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.l1c.overall_mshr_miss_latency 1482414272 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_rate 0.876165 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_misses 60444 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_uncacheable_latency 757487427 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_miss_latency 1034695660 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_rate 0.878339 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_misses 60529 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_uncacheable_latency 507727029 # number of overall MSHR uncacheable cycles system.cpu2.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu2.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu2.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -233,75 +233,75 @@ system.cpu2.l1c.prefetcher.num_hwpf_issued 0 # system.cpu2.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu2.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu2.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu2.l1c.replacements 27813 # number of replacements -system.cpu2.l1c.sampled_refs 28149 # Sample count of references to valid blocks. +system.cpu2.l1c.replacements 27701 # number of replacements +system.cpu2.l1c.sampled_refs 28067 # Sample count of references to valid blocks. system.cpu2.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.l1c.tagsinuse 346.292399 # Cycle average of tags in use -system.cpu2.l1c.total_refs 11687 # Total number of references to valid blocks. +system.cpu2.l1c.tagsinuse 345.217009 # Cycle average of tags in use +system.cpu2.l1c.total_refs 11453 # Total number of references to valid blocks. system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.writebacks 11045 # number of writebacks +system.cpu2.l1c.writebacks 10945 # number of writebacks system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 99140 # number of read accesses completed -system.cpu2.num_writes 54118 # number of write accesses completed -system.cpu3.l1c.ReadReq_accesses 44967 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_avg_miss_latency 23556.282690 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 22554.335004 # average ReadReq mshr miss latency +system.cpu2.num_reads 99465 # number of read accesses completed +system.cpu2.num_writes 53678 # number of write accesses completed +system.cpu3.l1c.ReadReq_accesses 44738 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_avg_miss_latency 16807.406146 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 15805.508175 # average ReadReq mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_hits 7463 # number of ReadReq hits -system.cpu3.l1c.ReadReq_miss_latency 883454826 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_rate 0.834034 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_misses 37504 # number of ReadReq misses -system.cpu3.l1c.ReadReq_mshr_miss_latency 845877780 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate 0.834034 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_misses 37504 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency 463016288 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_accesses 24252 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_avg_miss_latency 28359.679643 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 27357.936889 # average WriteReq mshr miss latency +system.cpu3.l1c.ReadReq_hits 7611 # number of ReadReq hits +system.cpu3.l1c.ReadReq_miss_latency 624008568 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_rate 0.829876 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_misses 37127 # number of ReadReq misses +system.cpu3.l1c.ReadReq_mshr_miss_latency 586811102 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate 0.829876 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_misses 37127 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency 311781129 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_accesses 24234 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_avg_miss_latency 20220.683790 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 19218.851594 # average WriteReq mshr miss latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_hits 928 # number of WriteReq hits -system.cpu3.l1c.WriteReq_miss_latency 661461168 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_rate 0.961735 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_misses 23324 # number of WriteReq misses -system.cpu3.l1c.WriteReq_mshr_miss_latency 638096520 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_rate 0.961735 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_misses 23324 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency 286853981 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.avg_blocked_cycles_no_mshrs 2284.842199 # average number of cycles each access was blocked +system.cpu3.l1c.WriteReq_hits 933 # number of WriteReq hits +system.cpu3.l1c.WriteReq_miss_latency 471162153 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_rate 0.961500 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_misses 23301 # number of WriteReq misses +system.cpu3.l1c.WriteReq_mshr_miss_latency 447818461 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_rate 0.961500 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_misses 23301 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency 199047765 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.avg_blocked_cycles_no_mshrs 1592.177624 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu3.l1c.avg_refs 0.401096 # Average number of references to valid blocks. -system.cpu3.l1c.blocked_no_mshrs 69803 # number of cycles access was blocked +system.cpu3.l1c.avg_refs 0.416452 # Average number of references to valid blocks. +system.cpu3.l1c.blocked_no_mshrs 69619 # number of cycles access was blocked system.cpu3.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked_cycles_no_mshrs 159488840 # number of cycles access was blocked +system.cpu3.l1c.blocked_cycles_no_mshrs 110845814 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.demand_accesses 69219 # number of demand (read+write) accesses -system.cpu3.l1c.demand_avg_miss_latency 25398.106037 # average overall miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency 24396.236930 # average overall mshr miss latency -system.cpu3.l1c.demand_hits 8391 # number of demand (read+write) hits -system.cpu3.l1c.demand_miss_latency 1544915994 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_rate 0.878776 # miss rate for demand accesses -system.cpu3.l1c.demand_misses 60828 # number of demand (read+write) misses +system.cpu3.l1c.demand_accesses 68972 # number of demand (read+write) accesses +system.cpu3.l1c.demand_avg_miss_latency 18123.563927 # average overall miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency 17121.691319 # average overall mshr miss latency +system.cpu3.l1c.demand_hits 8544 # number of demand (read+write) hits +system.cpu3.l1c.demand_miss_latency 1095170721 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_rate 0.876124 # miss rate for demand accesses +system.cpu3.l1c.demand_misses 60428 # number of demand (read+write) misses system.cpu3.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.l1c.demand_mshr_miss_latency 1483974300 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_rate 0.878776 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_misses 60828 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_miss_latency 1034629563 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_rate 0.876124 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_misses 60428 # number of demand (read+write) MSHR misses system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.l1c.overall_accesses 69219 # number of overall (read+write) accesses -system.cpu3.l1c.overall_avg_miss_latency 25398.106037 # average overall miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency 24396.236930 # average overall mshr miss latency +system.cpu3.l1c.overall_accesses 68972 # number of overall (read+write) accesses +system.cpu3.l1c.overall_avg_miss_latency 18123.563927 # average overall miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency 17121.691319 # average overall mshr miss latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu3.l1c.overall_hits 8391 # number of overall hits -system.cpu3.l1c.overall_miss_latency 1544915994 # number of overall miss cycles -system.cpu3.l1c.overall_miss_rate 0.878776 # miss rate for overall accesses -system.cpu3.l1c.overall_misses 60828 # number of overall misses +system.cpu3.l1c.overall_hits 8544 # number of overall hits +system.cpu3.l1c.overall_miss_latency 1095170721 # number of overall miss cycles +system.cpu3.l1c.overall_miss_rate 0.876124 # miss rate for overall accesses +system.cpu3.l1c.overall_misses 60428 # number of overall misses system.cpu3.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.l1c.overall_mshr_miss_latency 1483974300 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_rate 0.878776 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_misses 60828 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_uncacheable_latency 749870269 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_miss_latency 1034629563 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_rate 0.876124 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_misses 60428 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_uncacheable_latency 510828894 # number of overall MSHR uncacheable cycles system.cpu3.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu3.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu3.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -312,75 +312,75 @@ system.cpu3.l1c.prefetcher.num_hwpf_issued 0 # system.cpu3.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu3.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu3.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu3.l1c.replacements 28133 # number of replacements -system.cpu3.l1c.sampled_refs 28477 # Sample count of references to valid blocks. +system.cpu3.l1c.replacements 27578 # number of replacements +system.cpu3.l1c.sampled_refs 27936 # Sample count of references to valid blocks. system.cpu3.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.l1c.tagsinuse 347.262699 # Cycle average of tags in use -system.cpu3.l1c.total_refs 11422 # Total number of references to valid blocks. +system.cpu3.l1c.tagsinuse 346.223352 # Cycle average of tags in use +system.cpu3.l1c.total_refs 11634 # Total number of references to valid blocks. system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.writebacks 11005 # number of writebacks +system.cpu3.l1c.writebacks 10930 # number of writebacks system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99592 # number of read accesses completed -system.cpu3.num_writes 53713 # number of write accesses completed -system.cpu4.l1c.ReadReq_accesses 44752 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_avg_miss_latency 23804.358655 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 22802.626506 # average ReadReq mshr miss latency +system.cpu3.num_reads 99191 # number of read accesses completed +system.cpu3.num_writes 53892 # number of write accesses completed +system.cpu4.l1c.ReadReq_accesses 44699 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_avg_miss_latency 16730.870402 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 15728.971431 # average ReadReq mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_hits 7485 # number of ReadReq hits -system.cpu4.l1c.ReadReq_miss_latency 887117034 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_rate 0.832745 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_misses 37267 # number of ReadReq misses -system.cpu4.l1c.ReadReq_mshr_miss_latency 849785482 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate 0.832745 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_misses 37267 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency 460944695 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_accesses 24051 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_avg_miss_latency 28478.181673 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 27476.224597 # average WriteReq mshr miss latency +system.cpu4.l1c.ReadReq_hits 7561 # number of ReadReq hits +system.cpu4.l1c.ReadReq_miss_latency 621351065 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_rate 0.830846 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_misses 37138 # number of ReadReq misses +system.cpu4.l1c.ReadReq_mshr_miss_latency 584142541 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate 0.830846 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_misses 37138 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency 311544934 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_accesses 24149 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_avg_miss_latency 20416.974602 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 19415.143220 # average WriteReq mshr miss latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_hits 894 # number of WriteReq hits -system.cpu4.l1c.WriteReq_miss_latency 659469253 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_rate 0.962829 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_misses 23157 # number of WriteReq misses -system.cpu4.l1c.WriteReq_mshr_miss_latency 636266933 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_rate 0.962829 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_misses 23157 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency 290316641 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.avg_blocked_cycles_no_mshrs 2303.542545 # average number of cycles each access was blocked +system.cpu4.l1c.WriteReq_hits 919 # number of WriteReq hits +system.cpu4.l1c.WriteReq_miss_latency 474286320 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_rate 0.961945 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_misses 23230 # number of WriteReq misses +system.cpu4.l1c.WriteReq_mshr_miss_latency 451013777 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_rate 0.961945 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_misses 23230 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency 197320845 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.avg_blocked_cycles_no_mshrs 1595.899195 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu4.l1c.avg_refs 0.410509 # Average number of references to valid blocks. -system.cpu4.l1c.blocked_no_mshrs 69338 # number of cycles access was blocked +system.cpu4.l1c.avg_refs 0.415693 # Average number of references to valid blocks. +system.cpu4.l1c.blocked_no_mshrs 69580 # number of cycles access was blocked system.cpu4.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked_cycles_no_mshrs 159723033 # number of cycles access was blocked +system.cpu4.l1c.blocked_cycles_no_mshrs 111042666 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.demand_accesses 68803 # number of demand (read+write) accesses -system.cpu4.l1c.demand_avg_miss_latency 25595.562806 # average overall miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency 24593.744456 # average overall mshr miss latency -system.cpu4.l1c.demand_hits 8379 # number of demand (read+write) hits -system.cpu4.l1c.demand_miss_latency 1546586287 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_rate 0.878218 # miss rate for demand accesses -system.cpu4.l1c.demand_misses 60424 # number of demand (read+write) misses +system.cpu4.l1c.demand_accesses 68848 # number of demand (read+write) accesses +system.cpu4.l1c.demand_avg_miss_latency 18149.307332 # average overall miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency 17147.434369 # average overall mshr miss latency +system.cpu4.l1c.demand_hits 8480 # number of demand (read+write) hits +system.cpu4.l1c.demand_miss_latency 1095637385 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_rate 0.876830 # miss rate for demand accesses +system.cpu4.l1c.demand_misses 60368 # number of demand (read+write) misses system.cpu4.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu4.l1c.demand_mshr_miss_latency 1486052415 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_rate 0.878218 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_misses 60424 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_miss_latency 1035156318 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_rate 0.876830 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_misses 60368 # number of demand (read+write) MSHR misses system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.l1c.overall_accesses 68803 # number of overall (read+write) accesses -system.cpu4.l1c.overall_avg_miss_latency 25595.562806 # average overall miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency 24593.744456 # average overall mshr miss latency +system.cpu4.l1c.overall_accesses 68848 # number of overall (read+write) accesses +system.cpu4.l1c.overall_avg_miss_latency 18149.307332 # average overall miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency 17147.434369 # average overall mshr miss latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu4.l1c.overall_hits 8379 # number of overall hits -system.cpu4.l1c.overall_miss_latency 1546586287 # number of overall miss cycles -system.cpu4.l1c.overall_miss_rate 0.878218 # miss rate for overall accesses -system.cpu4.l1c.overall_misses 60424 # number of overall misses +system.cpu4.l1c.overall_hits 8480 # number of overall hits +system.cpu4.l1c.overall_miss_latency 1095637385 # number of overall miss cycles +system.cpu4.l1c.overall_miss_rate 0.876830 # miss rate for overall accesses +system.cpu4.l1c.overall_misses 60368 # number of overall misses system.cpu4.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu4.l1c.overall_mshr_miss_latency 1486052415 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_rate 0.878218 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_misses 60424 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_uncacheable_latency 751261336 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_miss_latency 1035156318 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_rate 0.876830 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_misses 60368 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_uncacheable_latency 508865779 # number of overall MSHR uncacheable cycles system.cpu4.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu4.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu4.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -391,75 +391,75 @@ system.cpu4.l1c.prefetcher.num_hwpf_issued 0 # system.cpu4.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu4.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu4.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu4.l1c.replacements 27694 # number of replacements -system.cpu4.l1c.sampled_refs 28053 # Sample count of references to valid blocks. +system.cpu4.l1c.replacements 27387 # number of replacements +system.cpu4.l1c.sampled_refs 27744 # Sample count of references to valid blocks. system.cpu4.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu4.l1c.tagsinuse 346.576888 # Cycle average of tags in use -system.cpu4.l1c.total_refs 11516 # Total number of references to valid blocks. +system.cpu4.l1c.tagsinuse 342.465450 # Cycle average of tags in use +system.cpu4.l1c.total_refs 11533 # Total number of references to valid blocks. system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.writebacks 10817 # number of writebacks +system.cpu4.l1c.writebacks 10754 # number of writebacks system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 98799 # number of read accesses completed -system.cpu4.num_writes 53431 # number of write accesses completed -system.cpu5.l1c.ReadReq_accesses 44885 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_avg_miss_latency 23518.665421 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 22516.852786 # average ReadReq mshr miss latency +system.cpu4.num_reads 98875 # number of read accesses completed +system.cpu4.num_writes 53476 # number of write accesses completed +system.cpu5.l1c.ReadReq_accesses 45145 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_avg_miss_latency 16695.250027 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 15693.270526 # average ReadReq mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_hits 7701 # number of ReadReq hits -system.cpu5.l1c.ReadReq_miss_latency 874518055 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_rate 0.828428 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_misses 37184 # number of ReadReq misses -system.cpu5.l1c.ReadReq_mshr_miss_latency 837266654 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate 0.828428 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_misses 37184 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency 472519207 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_accesses 24343 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_avg_miss_latency 28185.897903 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 27184.111666 # average WriteReq mshr miss latency +system.cpu5.l1c.ReadReq_hits 7729 # number of ReadReq hits +system.cpu5.l1c.ReadReq_miss_latency 624669475 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_rate 0.828796 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_misses 37416 # number of ReadReq misses +system.cpu5.l1c.ReadReq_mshr_miss_latency 587179410 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate 0.828796 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_misses 37416 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency 307088107 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_accesses 24354 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_avg_miss_latency 20311.644445 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 19309.896163 # average WriteReq mshr miss latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_hits 934 # number of WriteReq hits -system.cpu5.l1c.WriteReq_miss_latency 659803684 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_rate 0.961632 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_misses 23409 # number of WriteReq misses -system.cpu5.l1c.WriteReq_mshr_miss_latency 636352870 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_rate 0.961632 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_misses 23409 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency 285116672 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.avg_blocked_cycles_no_mshrs 2289.516557 # average number of cycles each access was blocked +system.cpu5.l1c.WriteReq_hits 923 # number of WriteReq hits +system.cpu5.l1c.WriteReq_miss_latency 475922141 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_rate 0.962101 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_misses 23431 # number of WriteReq misses +system.cpu5.l1c.WriteReq_mshr_miss_latency 452450177 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_rate 0.962101 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_misses 23431 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency 201036456 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.avg_blocked_cycles_no_mshrs 1589.108090 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu5.l1c.avg_refs 0.417638 # Average number of references to valid blocks. -system.cpu5.l1c.blocked_no_mshrs 69638 # number of cycles access was blocked +system.cpu5.l1c.avg_refs 0.411131 # Average number of references to valid blocks. +system.cpu5.l1c.blocked_no_mshrs 69923 # number of cycles access was blocked system.cpu5.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked_cycles_no_mshrs 159437354 # number of cycles access was blocked +system.cpu5.l1c.blocked_cycles_no_mshrs 111115205 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.demand_accesses 69228 # number of demand (read+write) accesses -system.cpu5.l1c.demand_avg_miss_latency 25321.765534 # average overall miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency 24319.963098 # average overall mshr miss latency -system.cpu5.l1c.demand_hits 8635 # number of demand (read+write) hits -system.cpu5.l1c.demand_miss_latency 1534321739 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_rate 0.875267 # miss rate for demand accesses -system.cpu5.l1c.demand_misses 60593 # number of demand (read+write) misses +system.cpu5.l1c.demand_accesses 69499 # number of demand (read+write) accesses +system.cpu5.l1c.demand_avg_miss_latency 18087.853403 # average overall miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency 17085.962940 # average overall mshr miss latency +system.cpu5.l1c.demand_hits 8652 # number of demand (read+write) hits +system.cpu5.l1c.demand_miss_latency 1100591616 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_rate 0.875509 # miss rate for demand accesses +system.cpu5.l1c.demand_misses 60847 # number of demand (read+write) misses system.cpu5.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu5.l1c.demand_mshr_miss_latency 1473619524 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_rate 0.875267 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_misses 60593 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_miss_latency 1039629587 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_rate 0.875509 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_misses 60847 # number of demand (read+write) MSHR misses system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.l1c.overall_accesses 69228 # number of overall (read+write) accesses -system.cpu5.l1c.overall_avg_miss_latency 25321.765534 # average overall miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency 24319.963098 # average overall mshr miss latency +system.cpu5.l1c.overall_accesses 69499 # number of overall (read+write) accesses +system.cpu5.l1c.overall_avg_miss_latency 18087.853403 # average overall miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency 17085.962940 # average overall mshr miss latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu5.l1c.overall_hits 8635 # number of overall hits -system.cpu5.l1c.overall_miss_latency 1534321739 # number of overall miss cycles -system.cpu5.l1c.overall_miss_rate 0.875267 # miss rate for overall accesses -system.cpu5.l1c.overall_misses 60593 # number of overall misses +system.cpu5.l1c.overall_hits 8652 # number of overall hits +system.cpu5.l1c.overall_miss_latency 1100591616 # number of overall miss cycles +system.cpu5.l1c.overall_miss_rate 0.875509 # miss rate for overall accesses +system.cpu5.l1c.overall_misses 60847 # number of overall misses system.cpu5.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu5.l1c.overall_mshr_miss_latency 1473619524 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_rate 0.875267 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_misses 60593 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_uncacheable_latency 757635879 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_miss_latency 1039629587 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_rate 0.875509 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_misses 60847 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_uncacheable_latency 508124563 # number of overall MSHR uncacheable cycles system.cpu5.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu5.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu5.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -470,75 +470,75 @@ system.cpu5.l1c.prefetcher.num_hwpf_issued 0 # system.cpu5.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu5.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu5.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu5.l1c.replacements 27880 # number of replacements -system.cpu5.l1c.sampled_refs 28223 # Sample count of references to valid blocks. +system.cpu5.l1c.replacements 28136 # number of replacements +system.cpu5.l1c.sampled_refs 28497 # Sample count of references to valid blocks. system.cpu5.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu5.l1c.tagsinuse 348.223192 # Cycle average of tags in use -system.cpu5.l1c.total_refs 11787 # Total number of references to valid blocks. +system.cpu5.l1c.tagsinuse 345.800641 # Cycle average of tags in use +system.cpu5.l1c.total_refs 11716 # Total number of references to valid blocks. system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.writebacks 11039 # number of writebacks +system.cpu5.l1c.writebacks 11040 # number of writebacks system.cpu5.num_copies 0 # number of copy accesses completed system.cpu5.num_reads 100000 # number of read accesses completed -system.cpu5.num_writes 53951 # number of write accesses completed -system.cpu6.l1c.ReadReq_accesses 44452 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_avg_miss_latency 23599.078540 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 22597.239994 # average ReadReq mshr miss latency +system.cpu5.num_writes 53687 # number of write accesses completed +system.cpu6.l1c.ReadReq_accesses 45027 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_avg_miss_latency 16617.118087 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 15615.219316 # average ReadReq mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_hits 7401 # number of ReadReq hits -system.cpu6.l1c.ReadReq_miss_latency 874369459 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_rate 0.833506 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_misses 37051 # number of ReadReq misses -system.cpu6.l1c.ReadReq_mshr_miss_latency 837250339 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate 0.833506 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_misses 37051 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency 468398074 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_accesses 24180 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_avg_miss_latency 28689.725113 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 27687.897435 # average WriteReq mshr miss latency +system.cpu6.l1c.ReadReq_hits 7597 # number of ReadReq hits +system.cpu6.l1c.ReadReq_miss_latency 621978730 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_rate 0.831279 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_misses 37430 # number of ReadReq misses +system.cpu6.l1c.ReadReq_mshr_miss_latency 584477659 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate 0.831279 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_misses 37430 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency 320096620 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_accesses 23941 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_avg_miss_latency 20221.380036 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 19219.637304 # average WriteReq mshr miss latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_hits 985 # number of WriteReq hits -system.cpu6.l1c.WriteReq_miss_latency 665458174 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_rate 0.959264 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_misses 23195 # number of WriteReq misses -system.cpu6.l1c.WriteReq_mshr_miss_latency 642220781 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_rate 0.959264 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_misses 23195 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency 283288804 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.avg_blocked_cycles_no_mshrs 2306.135407 # average number of cycles each access was blocked +system.cpu6.l1c.WriteReq_hits 930 # number of WriteReq hits +system.cpu6.l1c.WriteReq_miss_latency 465314176 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_rate 0.961155 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_misses 23011 # number of WriteReq misses +system.cpu6.l1c.WriteReq_mshr_miss_latency 442263074 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_rate 0.961155 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_misses 23011 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency 197754604 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.avg_blocked_cycles_no_mshrs 1586.699742 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu6.l1c.avg_refs 0.410866 # Average number of references to valid blocks. -system.cpu6.l1c.blocked_no_mshrs 69302 # number of cycles access was blocked +system.cpu6.l1c.avg_refs 0.414524 # Average number of references to valid blocks. +system.cpu6.l1c.blocked_no_mshrs 70023 # number of cycles access was blocked system.cpu6.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked_cycles_no_mshrs 159819796 # number of cycles access was blocked +system.cpu6.l1c.blocked_cycles_no_mshrs 111105476 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.demand_accesses 68632 # number of demand (read+write) accesses -system.cpu6.l1c.demand_avg_miss_latency 25559.001975 # average overall miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency 24557.167613 # average overall mshr miss latency -system.cpu6.l1c.demand_hits 8386 # number of demand (read+write) hits -system.cpu6.l1c.demand_miss_latency 1539827633 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_rate 0.877812 # miss rate for demand accesses -system.cpu6.l1c.demand_misses 60246 # number of demand (read+write) misses +system.cpu6.l1c.demand_accesses 68968 # number of demand (read+write) accesses +system.cpu6.l1c.demand_avg_miss_latency 17989.326881 # average overall miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency 16987.487517 # average overall mshr miss latency +system.cpu6.l1c.demand_hits 8527 # number of demand (read+write) hits +system.cpu6.l1c.demand_miss_latency 1087292906 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_rate 0.876363 # miss rate for demand accesses +system.cpu6.l1c.demand_misses 60441 # number of demand (read+write) misses system.cpu6.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu6.l1c.demand_mshr_miss_latency 1479471120 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_rate 0.877812 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_misses 60246 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_miss_latency 1026740733 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_rate 0.876363 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_misses 60441 # number of demand (read+write) MSHR misses system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.l1c.overall_accesses 68632 # number of overall (read+write) accesses -system.cpu6.l1c.overall_avg_miss_latency 25559.001975 # average overall miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency 24557.167613 # average overall mshr miss latency +system.cpu6.l1c.overall_accesses 68968 # number of overall (read+write) accesses +system.cpu6.l1c.overall_avg_miss_latency 17989.326881 # average overall miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency 16987.487517 # average overall mshr miss latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu6.l1c.overall_hits 8386 # number of overall hits -system.cpu6.l1c.overall_miss_latency 1539827633 # number of overall miss cycles -system.cpu6.l1c.overall_miss_rate 0.877812 # miss rate for overall accesses -system.cpu6.l1c.overall_misses 60246 # number of overall misses +system.cpu6.l1c.overall_hits 8527 # number of overall hits +system.cpu6.l1c.overall_miss_latency 1087292906 # number of overall miss cycles +system.cpu6.l1c.overall_miss_rate 0.876363 # miss rate for overall accesses +system.cpu6.l1c.overall_misses 60441 # number of overall misses system.cpu6.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu6.l1c.overall_mshr_miss_latency 1479471120 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_rate 0.877812 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_misses 60246 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_uncacheable_latency 751686878 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_miss_latency 1026740733 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_rate 0.876363 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_misses 60441 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_uncacheable_latency 517851224 # number of overall MSHR uncacheable cycles system.cpu6.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu6.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu6.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -549,75 +549,75 @@ system.cpu6.l1c.prefetcher.num_hwpf_issued 0 # system.cpu6.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu6.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu6.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu6.l1c.replacements 27468 # number of replacements -system.cpu6.l1c.sampled_refs 27829 # Sample count of references to valid blocks. +system.cpu6.l1c.replacements 27646 # number of replacements +system.cpu6.l1c.sampled_refs 27996 # Sample count of references to valid blocks. system.cpu6.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu6.l1c.tagsinuse 345.245640 # Cycle average of tags in use -system.cpu6.l1c.total_refs 11434 # Total number of references to valid blocks. +system.cpu6.l1c.tagsinuse 344.481018 # Cycle average of tags in use +system.cpu6.l1c.total_refs 11605 # Total number of references to valid blocks. system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.writebacks 10779 # number of writebacks +system.cpu6.l1c.writebacks 10854 # number of writebacks system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 98631 # number of read accesses completed -system.cpu6.num_writes 53473 # number of write accesses completed -system.cpu7.l1c.ReadReq_accesses 45026 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_avg_miss_latency 23566.694007 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 22564.854082 # average ReadReq mshr miss latency +system.cpu6.num_reads 99885 # number of read accesses completed +system.cpu6.num_writes 53649 # number of write accesses completed +system.cpu7.l1c.ReadReq_accesses 44691 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_avg_miss_latency 16751.059693 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 15749.134660 # average ReadReq mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_hits 7731 # number of ReadReq hits -system.cpu7.l1c.ReadReq_miss_latency 878919853 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_rate 0.828299 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_misses 37295 # number of ReadReq misses -system.cpu7.l1c.ReadReq_mshr_miss_latency 841556233 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate 0.828299 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_misses 37295 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency 464511482 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_accesses 24312 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_avg_miss_latency 28334.071468 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 27332.156470 # average WriteReq mshr miss latency +system.cpu7.l1c.ReadReq_hits 7568 # number of ReadReq hits +system.cpu7.l1c.ReadReq_miss_latency 621849589 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_rate 0.830659 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_misses 37123 # number of ReadReq misses +system.cpu7.l1c.ReadReq_mshr_miss_latency 584655126 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate 0.830659 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_misses 37123 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency 309541021 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_accesses 24304 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_avg_miss_latency 20320.041471 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 19318.250661 # average WriteReq mshr miss latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_hits 889 # number of WriteReq hits -system.cpu7.l1c.WriteReq_miss_latency 663668956 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_rate 0.963434 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_misses 23423 # number of WriteReq misses -system.cpu7.l1c.WriteReq_mshr_miss_latency 640201101 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_rate 0.963434 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_misses 23423 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency 287294687 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.avg_blocked_cycles_no_mshrs 2290.551288 # average number of cycles each access was blocked +system.cpu7.l1c.WriteReq_hits 866 # number of WriteReq hits +system.cpu7.l1c.WriteReq_miss_latency 476261132 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_rate 0.964368 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_misses 23438 # number of WriteReq misses +system.cpu7.l1c.WriteReq_mshr_miss_latency 452781159 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_rate 0.964368 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_misses 23438 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency 195853343 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.avg_blocked_cycles_no_mshrs 1592.201934 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu7.l1c.avg_refs 0.413973 # Average number of references to valid blocks. -system.cpu7.l1c.blocked_no_mshrs 69548 # number of cycles access was blocked +system.cpu7.l1c.avg_refs 0.409635 # Average number of references to valid blocks. +system.cpu7.l1c.blocked_no_mshrs 69815 # number of cycles access was blocked system.cpu7.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked_cycles_no_mshrs 159303261 # number of cycles access was blocked +system.cpu7.l1c.blocked_cycles_no_mshrs 111159578 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.demand_accesses 69338 # number of demand (read+write) accesses -system.cpu7.l1c.demand_avg_miss_latency 25405.790853 # average overall miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency 24403.921967 # average overall mshr miss latency -system.cpu7.l1c.demand_hits 8620 # number of demand (read+write) hits -system.cpu7.l1c.demand_miss_latency 1542588809 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_rate 0.875681 # miss rate for demand accesses -system.cpu7.l1c.demand_misses 60718 # number of demand (read+write) misses +system.cpu7.l1c.demand_accesses 68995 # number of demand (read+write) accesses +system.cpu7.l1c.demand_avg_miss_latency 18132.308268 # average overall miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency 17130.435181 # average overall mshr miss latency +system.cpu7.l1c.demand_hits 8434 # number of demand (read+write) hits +system.cpu7.l1c.demand_miss_latency 1098110721 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_rate 0.877759 # miss rate for demand accesses +system.cpu7.l1c.demand_misses 60561 # number of demand (read+write) misses system.cpu7.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu7.l1c.demand_mshr_miss_latency 1481757334 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_rate 0.875681 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_misses 60718 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_miss_latency 1037436285 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_rate 0.877759 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_misses 60561 # number of demand (read+write) MSHR misses system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.l1c.overall_accesses 69338 # number of overall (read+write) accesses -system.cpu7.l1c.overall_avg_miss_latency 25405.790853 # average overall miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency 24403.921967 # average overall mshr miss latency +system.cpu7.l1c.overall_accesses 68995 # number of overall (read+write) accesses +system.cpu7.l1c.overall_avg_miss_latency 18132.308268 # average overall miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency 17130.435181 # average overall mshr miss latency system.cpu7.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu7.l1c.overall_hits 8620 # number of overall hits -system.cpu7.l1c.overall_miss_latency 1542588809 # number of overall miss cycles -system.cpu7.l1c.overall_miss_rate 0.875681 # miss rate for overall accesses -system.cpu7.l1c.overall_misses 60718 # number of overall misses +system.cpu7.l1c.overall_hits 8434 # number of overall hits +system.cpu7.l1c.overall_miss_latency 1098110721 # number of overall miss cycles +system.cpu7.l1c.overall_miss_rate 0.877759 # miss rate for overall accesses +system.cpu7.l1c.overall_misses 60561 # number of overall misses system.cpu7.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu7.l1c.overall_mshr_miss_latency 1481757334 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_rate 0.875681 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_misses 60718 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_uncacheable_latency 751806169 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_miss_latency 1037436285 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_rate 0.877759 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_misses 60561 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_uncacheable_latency 505394364 # number of overall MSHR uncacheable cycles system.cpu7.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu7.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu7.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -628,91 +628,88 @@ system.cpu7.l1c.prefetcher.num_hwpf_issued 0 # system.cpu7.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu7.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu7.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu7.l1c.replacements 27895 # number of replacements -system.cpu7.l1c.sampled_refs 28241 # Sample count of references to valid blocks. +system.cpu7.l1c.replacements 27888 # number of replacements +system.cpu7.l1c.sampled_refs 28230 # Sample count of references to valid blocks. system.cpu7.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu7.l1c.tagsinuse 346.417041 # Cycle average of tags in use -system.cpu7.l1c.total_refs 11691 # Total number of references to valid blocks. +system.cpu7.l1c.tagsinuse 344.969892 # Cycle average of tags in use +system.cpu7.l1c.total_refs 11564 # Total number of references to valid blocks. system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.writebacks 10935 # number of writebacks +system.cpu7.l1c.writebacks 10925 # number of writebacks system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 99923 # number of read accesses completed -system.cpu7.num_writes 53956 # number of write accesses completed -system.l2c.ReadExReq_accesses 74537 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 20115.263386 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 10011.845848 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 1499331387 # number of ReadExReq miss cycles +system.cpu7.num_reads 99393 # number of read accesses completed +system.cpu7.num_writes 53943 # number of write accesses completed +system.l2c.ReadExReq_accesses 74841 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 20077.258829 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 10005.440708 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 1502602128 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 74537 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_hits 461 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_miss_latency 746252954 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_misses 74841 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_hits 333 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_miss_latency 748817188 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 74537 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 137370 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 20204.368124 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 10010.792670 # average ReadReq mshr miss latency +system.l2c.ReadExReq_mshr_misses 74841 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 137840 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 20218.016376 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 10005.490618 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits 62417 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 1514378004 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.545629 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 74953 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 884 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 750338943 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.545629 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 74953 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 791888060 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses 18325 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 10129.887094 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 10011.324093 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 185630181 # number of UpgradeReq miss cycles +system.l2c.ReadReq_hits 90514 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 956837843 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.343340 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 47326 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 619 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 473519849 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.343340 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 47326 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 791100325 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses 18299 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 11082.248210 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 10005.327832 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 202794060 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 18325 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_hits 24 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_miss_latency 183457514 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_misses 18299 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_hits 30 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_miss_latency 183087494 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 18325 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 18299 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 429360910 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses 86629 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.l2c.Writeback_misses 86629 # number of Writeback misses -system.l2c.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses -system.l2c.Writeback_mshr_misses 86629 # number of Writeback MSHR misses +system.l2c.WriteReq_mshr_uncacheable_latency 429380546 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses 86810 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 86810 # number of Writeback hits system.l2c.avg_blocked_cycles_no_mshrs 2919.500000 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_refs 3.325063 # Average number of references to valid blocks. +system.l2c.avg_refs 2.008302 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 6 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 17517 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 211907 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 20159.939735 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 10011.317794 # average overall mshr miss latency -system.l2c.demand_hits 62417 # number of demand (read+write) hits -system.l2c.demand_miss_latency 3013709391 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.705451 # miss rate for demand accesses -system.l2c.demand_misses 149490 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 1345 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 1496591897 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.705451 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 149490 # number of demand (read+write) MSHR misses +system.l2c.demand_accesses 212681 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 20131.786579 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 10005.460042 # average overall mshr miss latency +system.l2c.demand_hits 90514 # number of demand (read+write) hits +system.l2c.demand_miss_latency 2459439971 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.574414 # miss rate for demand accesses +system.l2c.demand_misses 122167 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 952 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 1222337037 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.574414 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 122167 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 211907 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 20159.939735 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 10011.317794 # average overall mshr miss latency +system.l2c.overall_accesses 212681 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 20131.786579 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 10005.460042 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits 62417 # number of overall hits -system.l2c.overall_miss_latency 3013709391 # number of overall miss cycles -system.l2c.overall_miss_rate 0.705451 # miss rate for overall accesses -system.l2c.overall_misses 149490 # number of overall misses -system.l2c.overall_mshr_hits 1345 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 1496591897 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.705451 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 149490 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 1221248970 # number of overall MSHR uncacheable cycles +system.l2c.overall_hits 90514 # number of overall hits +system.l2c.overall_miss_latency 2459439971 # number of overall miss cycles +system.l2c.overall_miss_rate 0.574414 # miss rate for overall accesses +system.l2c.overall_misses 122167 # number of overall misses +system.l2c.overall_mshr_hits 952 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 1222337037 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.574414 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 122167 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 1220480871 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -723,12 +720,12 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 30719 # number of replacements -system.l2c.sampled_refs 31154 # Sample count of references to valid blocks. +system.l2c.replacements 73609 # number of replacements +system.l2c.sampled_refs 74198 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 460.327226 # Cycle average of tags in use -system.l2c.total_refs 103589 # Total number of references to valid blocks. +system.l2c.tagsinuse 631.450089 # Cycle average of tags in use +system.l2c.total_refs 149012 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 0 # number of writebacks +system.l2c.writebacks 47009 # number of writebacks ---------- End Simulation Statistics ---------- diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr b/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr index 6aaad2045..6e067280a 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr @@ -1,74 +1,74 @@ warn: Entering event queue @ 0. Starting simulation... -system.cpu7: completed 10000 read accesses @15573567 -system.cpu3: completed 10000 read accesses @15845087 -system.cpu6: completed 10000 read accesses @15845510 -system.cpu2: completed 10000 read accesses @15899346 -system.cpu0: completed 10000 read accesses @15988699 -system.cpu5: completed 10000 read accesses @15997024 -system.cpu1: completed 10000 read accesses @16210356 -system.cpu4: completed 10000 read accesses @16435221 -system.cpu7: completed 20000 read accesses @31796453 -system.cpu2: completed 20000 read accesses @32128661 -system.cpu5: completed 20000 read accesses @32234396 -system.cpu6: completed 20000 read accesses @32294014 -system.cpu0: completed 20000 read accesses @32471317 -system.cpu3: completed 20000 read accesses @32570615 -system.cpu1: completed 20000 read accesses @32640091 -system.cpu4: completed 20000 read accesses @32877562 -system.cpu5: completed 30000 read accesses @48207622 -system.cpu2: completed 30000 read accesses @48440845 -system.cpu7: completed 30000 read accesses @48459290 -system.cpu3: completed 30000 read accesses @48710826 -system.cpu0: completed 30000 read accesses @48923796 -system.cpu1: completed 30000 read accesses @48961602 -system.cpu6: completed 30000 read accesses @49000253 -system.cpu4: completed 30000 read accesses @49456834 -system.cpu5: completed 40000 read accesses @64830509 -system.cpu7: completed 40000 read accesses @64831406 -system.cpu2: completed 40000 read accesses @64990686 -system.cpu0: completed 40000 read accesses @65126336 -system.cpu3: completed 40000 read accesses @65216672 -system.cpu1: completed 40000 read accesses @65233718 -system.cpu6: completed 40000 read accesses @65544034 -system.cpu4: completed 40000 read accesses @65878034 -system.cpu5: completed 50000 read accesses @81060957 -system.cpu7: completed 50000 read accesses @81212197 -system.cpu2: completed 50000 read accesses @81437704 -system.cpu3: completed 50000 read accesses @81544353 -system.cpu0: completed 50000 read accesses @81653617 -system.cpu4: completed 50000 read accesses @81787398 -system.cpu1: completed 50000 read accesses @81868780 -system.cpu6: completed 50000 read accesses @82227342 -system.cpu7: completed 60000 read accesses @97291732 -system.cpu5: completed 60000 read accesses @97361345 -system.cpu2: completed 60000 read accesses @97621191 -system.cpu3: completed 60000 read accesses @97673986 -system.cpu1: completed 60000 read accesses @97950396 -system.cpu0: completed 60000 read accesses @98086520 -system.cpu4: completed 60000 read accesses @98139060 -system.cpu6: completed 60000 read accesses @98866267 -system.cpu7: completed 70000 read accesses @113775234 -system.cpu5: completed 70000 read accesses @114027734 -system.cpu3: completed 70000 read accesses @114107654 -system.cpu2: completed 70000 read accesses @114287447 -system.cpu1: completed 70000 read accesses @114429712 -system.cpu0: completed 70000 read accesses @114626666 -system.cpu4: completed 70000 read accesses @115046863 -system.cpu6: completed 70000 read accesses @115625699 -system.cpu7: completed 80000 read accesses @130114471 -system.cpu5: completed 80000 read accesses @130239115 -system.cpu3: completed 80000 read accesses @130679996 -system.cpu1: completed 80000 read accesses @130860729 -system.cpu0: completed 80000 read accesses @131170286 -system.cpu2: completed 80000 read accesses @131219347 -system.cpu4: completed 80000 read accesses @131694972 -system.cpu6: completed 80000 read accesses @132127278 -system.cpu7: completed 90000 read accesses @146355152 -system.cpu5: completed 90000 read accesses @146631518 -system.cpu3: completed 90000 read accesses @146856424 -system.cpu1: completed 90000 read accesses @147217275 -system.cpu0: completed 90000 read accesses @147658368 -system.cpu2: completed 90000 read accesses @147775118 -system.cpu4: completed 90000 read accesses @148157312 -system.cpu6: completed 90000 read accesses @148500053 -system.cpu5: completed 100000 read accesses @162969030 +system.cpu2: completed 10000 read accesses @10737200 +system.cpu5: completed 10000 read accesses @10933125 +system.cpu6: completed 10000 read accesses @10968295 +system.cpu4: completed 10000 read accesses @11004110 +system.cpu0: completed 10000 read accesses @11034624 +system.cpu1: completed 10000 read accesses @11079796 +system.cpu7: completed 10000 read accesses @11098893 +system.cpu3: completed 10000 read accesses @11305149 +system.cpu5: completed 20000 read accesses @22247478 +system.cpu0: completed 20000 read accesses @22286441 +system.cpu2: completed 20000 read accesses @22412370 +system.cpu6: completed 20000 read accesses @22412546 +system.cpu7: completed 20000 read accesses @22443360 +system.cpu4: completed 20000 read accesses @22571774 +system.cpu3: completed 20000 read accesses @22684521 +system.cpu1: completed 20000 read accesses @22854803 +system.cpu6: completed 30000 read accesses @33383823 +system.cpu5: completed 30000 read accesses @33433409 +system.cpu2: completed 30000 read accesses @33567039 +system.cpu0: completed 30000 read accesses @33772397 +system.cpu7: completed 30000 read accesses @33863963 +system.cpu4: completed 30000 read accesses @34085859 +system.cpu1: completed 30000 read accesses @34145159 +system.cpu3: completed 30000 read accesses @34287598 +system.cpu5: completed 40000 read accesses @44537930 +system.cpu6: completed 40000 read accesses @44682656 +system.cpu2: completed 40000 read accesses @45063291 +system.cpu7: completed 40000 read accesses @45207960 +system.cpu4: completed 40000 read accesses @45307242 +system.cpu0: completed 40000 read accesses @45322044 +system.cpu1: completed 40000 read accesses @45703462 +system.cpu3: completed 40000 read accesses @45764765 +system.cpu5: completed 50000 read accesses @55736175 +system.cpu6: completed 50000 read accesses @55796558 +system.cpu2: completed 50000 read accesses @56140676 +system.cpu7: completed 50000 read accesses @56614131 +system.cpu1: completed 50000 read accesses @56649016 +system.cpu0: completed 50000 read accesses @56658259 +system.cpu4: completed 50000 read accesses @56697374 +system.cpu3: completed 50000 read accesses @56853901 +system.cpu5: completed 60000 read accesses @66922971 +system.cpu6: completed 60000 read accesses @67166318 +system.cpu2: completed 60000 read accesses @67391190 +system.cpu4: completed 60000 read accesses @67879872 +system.cpu1: completed 60000 read accesses @67932570 +system.cpu7: completed 60000 read accesses @68061664 +system.cpu0: completed 60000 read accesses @68084935 +system.cpu3: completed 60000 read accesses @68091555 +system.cpu6: completed 70000 read accesses @78400269 +system.cpu5: completed 70000 read accesses @78438516 +system.cpu2: completed 70000 read accesses @78758205 +system.cpu3: completed 70000 read accesses @79263647 +system.cpu4: completed 70000 read accesses @79315746 +system.cpu7: completed 70000 read accesses @79346909 +system.cpu0: completed 70000 read accesses @79354333 +system.cpu1: completed 70000 read accesses @79387143 +system.cpu5: completed 80000 read accesses @89714934 +system.cpu6: completed 80000 read accesses @89763887 +system.cpu2: completed 80000 read accesses @90325410 +system.cpu7: completed 80000 read accesses @90552338 +system.cpu4: completed 80000 read accesses @90699585 +system.cpu1: completed 80000 read accesses @90703570 +system.cpu3: completed 80000 read accesses @90734586 +system.cpu0: completed 80000 read accesses @90833170 +system.cpu5: completed 90000 read accesses @100989582 +system.cpu6: completed 90000 read accesses @101209540 +system.cpu7: completed 90000 read accesses @101654330 +system.cpu2: completed 90000 read accesses @101680284 +system.cpu1: completed 90000 read accesses @101964609 +system.cpu3: completed 90000 read accesses @101974763 +system.cpu0: completed 90000 read accesses @102286151 +system.cpu4: completed 90000 read accesses @102328481 +system.cpu5: completed 100000 read accesses @112555067 diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout index a0a2b76f8..9edc3918b 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 2 2008 15:26:07 -M5 started Wed Jan 2 15:26:09 2008 -M5 executing on vm1 +M5 compiled Feb 13 2008 00:33:15 +M5 started Wed Feb 13 00:34:33 2008 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest Global frequency set at 1000000000000 ticks per second -Exiting @ tick 162969030 because maximum number of loads reached +Exiting @ tick 112555067 because maximum number of loads reached |