diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2011-04-12 16:09:20 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2011-04-12 16:09:20 -0400 |
| commit | d50d0152d0ea40e93c73dec1ffb6f37e79609fdd (patch) | |
| tree | c3e2400206e83dd3ca5f36a53ba5e88d31f26ac4 /tests/quick | |
| parent | 4b61abe8da876ed3e56a1851384ec11ede65bd89 (diff) | |
| download | gem5-d50d0152d0ea40e93c73dec1ffb6f37e79609fdd.tar.xz | |
ARM: Fix stats for ARM_SE checkpoint restore fix.
Register reads/writes done in startup() count against the stats while they
don't count if done in initState().
Diffstat (limited to 'tests/quick')
| -rw-r--r-- | tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini | 2 | ||||
| -rw-r--r-- | tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt | 14 |
2 files changed, 8 insertions, 8 deletions
diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini index 69223be2f..c995df06b 100644 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini @@ -498,7 +498,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/test-progs/hello/bin/arm/linux/hello +executable=/arm/scratch/alisai01/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt index f9b43ff41..bb000db1d 100644 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 40713 # Simulator instruction rate (inst/s) -host_mem_usage 251964 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host -host_tick_rate 76493621 # Simulator tick rate (ticks/s) +host_inst_rate 51112 # Simulator instruction rate (inst/s) +host_mem_usage 254432 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host +host_tick_rate 95982480 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5739 # Number of instructions simulated sim_seconds 0.000011 # Number of seconds simulated @@ -287,7 +287,7 @@ system.cpu.iew.memOrderViolationEvents 12 # Nu system.cpu.iew.predictedNotTakenIncorrect 246 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 119 # Number of branches that were predicted taken incorrectly system.cpu.int_regfile_reads 18334 # number of integer regfile reads -system.cpu.int_regfile_writes 5507 # number of integer regfile writes +system.cpu.int_regfile_writes 5503 # number of integer regfile writes system.cpu.ipc 0.265596 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.265596 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -484,8 +484,8 @@ system.cpu.memDep0.conflictingLoads 10 # Nu system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 2372 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1498 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 13984 # number of misc regfile reads -system.cpu.misc_regfile_writes 26 # number of misc regfile writes +system.cpu.misc_regfile_reads 13982 # number of misc regfile reads +system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.numCycles 21608 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started |