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| author | Tuan Ta <qtt2@cornell.edu> | 2018-05-22 00:24:24 -0400 |
|---|---|---|
| committer | Tuan Ta <qtt2@cornell.edu> | 2018-06-15 00:25:50 +0000 |
| commit | e502572ce4c30a74ea1847e123c886f984dee311 (patch) | |
| tree | f153cbf2076a9c2336da3d2215a89d50ccd672f6 /tests/test-progs/asmtest/src/riscv/isa/rv64uc/Makefrag | |
| parent | 3bb22b7fc3e642533f8bb170e8de1de5e62d976c (diff) | |
| download | gem5-e502572ce4c30a74ea1847e123c886f984dee311.tar.xz | |
tests,style: add RISC-V assembly tests
This patch adds a subset (rv64*) of RISC-V assembly tests. The original
riscv-test project can be found here:
https://github.com/riscv/riscv-tests. The riscv-test project is under the
BSD license (https://github.com/riscv/riscv-tests/blob/master/LICENSE)
and is maintained separately from gem5 project.
The tests have been slightly modified to work in gem5 SE mode:
(1) Removed a trap handler used in riscv-tests for bare-metal systems
(2) Instead of throwing an exception, the tests call the exit syscall
with
the exit code of
- '0' if SUCCESS
- Failed test case's number (non-zero) if FAILURE
The exit code can be captured after a simuation completes.
In addition to original RISC-V assembly tests, this patch adds several
assembly tests specifically for AMO, LR, SC and system calls. Those
tests target a multi-core system.
(1) rv64uamt: multi-threaded tests for A-extension instructions
(2) rv64samt: multi-threaded tests for clone and futex system calls
This patch also makes the style checker ignore RISC-V assembly test
directory. The assembly tests are maintained in an external project
that does not follow the gem5 coding conventions.
Please find more details in the README file included in this patch.
Change-Id: Id1015d9a2c6c7d0341fa8b81483289e5f0bfcec0
Reviewed-on: https://gem5-review.googlesource.com/6703
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'tests/test-progs/asmtest/src/riscv/isa/rv64uc/Makefrag')
| -rw-r--r-- | tests/test-progs/asmtest/src/riscv/isa/rv64uc/Makefrag | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64uc/Makefrag b/tests/test-progs/asmtest/src/riscv/isa/rv64uc/Makefrag new file mode 100644 index 000000000..90aeb6311 --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64uc/Makefrag @@ -0,0 +1,12 @@ +#======================================================================= +# Makefrag for rv64uc tests +#----------------------------------------------------------------------- + +rv64uc_sc_tests = \ + rvc \ + +rv64ua_p_tests = $(addprefix rv64ua-p-, $(rv64ua_sc_tests)) +rv64uc_v_tests = $(addprefix rv64uc-v-, $(rv64uc_sc_tests)) +rv64ua_ps_tests = $(addprefix rv64ua-ps-, $(rv64ua_sc_tests)) + +spike_tests += $(rv64uc_p_tests) $(rv64uc_v_tests) |