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authorTuan Ta <qtt2@cornell.edu>2018-05-22 00:24:24 -0400
committerTuan Ta <qtt2@cornell.edu>2018-06-15 00:25:50 +0000
commite502572ce4c30a74ea1847e123c886f984dee311 (patch)
treef153cbf2076a9c2336da3d2215a89d50ccd672f6 /tests/test-progs/asmtest/src/riscv/isa/rv64uf/fclass.S
parent3bb22b7fc3e642533f8bb170e8de1de5e62d976c (diff)
downloadgem5-e502572ce4c30a74ea1847e123c886f984dee311.tar.xz
tests,style: add RISC-V assembly tests
This patch adds a subset (rv64*) of RISC-V assembly tests. The original riscv-test project can be found here: https://github.com/riscv/riscv-tests. The riscv-test project is under the BSD license (https://github.com/riscv/riscv-tests/blob/master/LICENSE) and is maintained separately from gem5 project. The tests have been slightly modified to work in gem5 SE mode: (1) Removed a trap handler used in riscv-tests for bare-metal systems (2) Instead of throwing an exception, the tests call the exit syscall with the exit code of - '0' if SUCCESS - Failed test case's number (non-zero) if FAILURE The exit code can be captured after a simuation completes. In addition to original RISC-V assembly tests, this patch adds several assembly tests specifically for AMO, LR, SC and system calls. Those tests target a multi-core system. (1) rv64uamt: multi-threaded tests for A-extension instructions (2) rv64samt: multi-threaded tests for clone and futex system calls This patch also makes the style checker ignore RISC-V assembly test directory. The assembly tests are maintained in an external project that does not follow the gem5 coding conventions. Please find more details in the README file included in this patch. Change-Id: Id1015d9a2c6c7d0341fa8b81483289e5f0bfcec0 Reviewed-on: https://gem5-review.googlesource.com/6703 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'tests/test-progs/asmtest/src/riscv/isa/rv64uf/fclass.S')
-rw-r--r--tests/test-progs/asmtest/src/riscv/isa/rv64uf/fclass.S40
1 files changed, 40 insertions, 0 deletions
diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64uf/fclass.S b/tests/test-progs/asmtest/src/riscv/isa/rv64uf/fclass.S
new file mode 100644
index 000000000..9bb86b17b
--- /dev/null
+++ b/tests/test-progs/asmtest/src/riscv/isa/rv64uf/fclass.S
@@ -0,0 +1,40 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fclass.S
+#-----------------------------------------------------------------------------
+#
+# Test fclass.s instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_FCLASS_S( 2, 1 << 0, 0xff800000 )
+ TEST_FCLASS_S( 3, 1 << 1, 0xbf800000 )
+ TEST_FCLASS_S( 4, 1 << 2, 0x807fffff )
+ TEST_FCLASS_S( 5, 1 << 3, 0x80000000 )
+ TEST_FCLASS_S( 6, 1 << 4, 0x00000000 )
+ TEST_FCLASS_S( 7, 1 << 5, 0x007fffff )
+ TEST_FCLASS_S( 8, 1 << 6, 0x3f800000 )
+ TEST_FCLASS_S( 9, 1 << 7, 0x7f800000 )
+ TEST_FCLASS_S(10, 1 << 8, 0x7f800001 )
+ TEST_FCLASS_S(11, 1 << 9, 0x7fc00000 )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END