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| author | Kevin Lim <ktlim@umich.edu> | 2006-07-22 15:50:39 -0400 |
|---|---|---|
| committer | Kevin Lim <ktlim@umich.edu> | 2006-07-22 15:50:39 -0400 |
| commit | 7ccdb7accc073d282e9df804da400394a795b2ae (patch) | |
| tree | d935413c25fa0e0684bcfdc8dcda4052a10a853d /tests/test1/ref/alpha/timing/m5stats.txt | |
| parent | db5f710a7b9fbaf6cc63861d9cd7dc3f4a3fdea1 (diff) | |
| download | gem5-7ccdb7accc073d282e9df804da400394a795b2ae.tar.xz | |
Last minute check in. Very few functional changes other than some minor config updates. Also include some recently generated stats.
SConstruct:
Make test CPUs option non-sticky.
configs/common/FSConfig.py:
Be sure to set the memory mode.
configs/test/fs.py:
Wrong string.
tests/SConscript:
Only test valid CPUs that have been compiled in.
tests/test1/ref/alpha/atomic/config.ini:
tests/test1/ref/alpha/atomic/config.out:
tests/test1/ref/alpha/atomic/m5stats.txt:
tests/test1/ref/alpha/atomic/stdout:
tests/test1/ref/alpha/detailed/config.ini:
tests/test1/ref/alpha/detailed/config.out:
tests/test1/ref/alpha/detailed/m5stats.txt:
tests/test1/ref/alpha/detailed/stdout:
tests/test1/ref/alpha/timing/config.ini:
tests/test1/ref/alpha/timing/config.out:
tests/test1/ref/alpha/timing/m5stats.txt:
tests/test1/ref/alpha/timing/stdout:
Update output.
--HG--
extra : convert_revision : 6eee2a5eae0291b5121b41bcd7021179cdd520a3
Diffstat (limited to 'tests/test1/ref/alpha/timing/m5stats.txt')
| -rw-r--r-- | tests/test1/ref/alpha/timing/m5stats.txt | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/tests/test1/ref/alpha/timing/m5stats.txt b/tests/test1/ref/alpha/timing/m5stats.txt index 64d05099f..5f7766bac 100644 --- a/tests/test1/ref/alpha/timing/m5stats.txt +++ b/tests/test1/ref/alpha/timing/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 739858 # Simulator instruction rate (inst/s) -host_mem_usage 147760 # Number of bytes of host memory used -host_seconds 0.68 # Real time elapsed on the host -host_tick_rate 1006609 # Simulator tick rate (ticks/s) +host_inst_rate 781730 # Simulator instruction rate (inst/s) +host_mem_usage 147616 # Number of bytes of host memory used +host_seconds 0.64 # Real time elapsed on the host +host_tick_rate 1063244 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500000 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated sim_ticks 680774 # Number of ticks simulated -system.cpu0.idle_fraction 0 # Percentage of idle cycles -system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu0.numCycles 0 # number of cpu cycles simulated -system.cpu0.num_insts 500000 # Number of instructions executed -system.cpu0.num_refs 182203 # Number of memory references +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 0 # number of cpu cycles simulated +system.cpu.num_insts 500000 # Number of instructions executed +system.cpu.num_refs 182203 # Number of memory references system.workload.PROG:num_syscalls 18 # Number of system calls ---------- End Simulation Statistics ---------- |