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author | Arthur Perais <arthur.perais@inria.fr> | 2016-12-21 15:04:06 -0600 |
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committer | Arthur Perais <arthur.perais@inria.fr> | 2016-12-21 15:04:06 -0600 |
commit | e5fb6752d613a6f85e2f93b4c01836ac59a8c90c (patch) | |
tree | 7bec60d7645ed4a1d7e20dc8071c0dafd288b786 /tests/testing | |
parent | 3a656da1a64f08d5e4c755e94cefda5a4e985a50 (diff) | |
download | gem5-e5fb6752d613a6f85e2f93b4c01836ac59a8c90c.tar.xz |
cpu: Clarify meaning of cachePorts variable in lsq_unit.hh of O3
cachePorts currently constrains the number of store packets written to the
D-Cache each cycle), but loads currently affect this variable. This leads
to unexpected congestion (e.g., setting cachePorts to a realistic 1 will
in fact allow a store to WB only if no loads have accessed the D-Cache
this cycle). In the absence of arbitration, this patch decouples how many
loads can be done per cycle from how many stores can be done per cycle.
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'tests/testing')
0 files changed, 0 insertions, 0 deletions