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authorGabe Black <gabeblack@google.com>2019-11-05 16:21:20 -0800
committerGabe Black <gabeblack@google.com>2019-12-27 20:52:13 +0000
commit2093d84a774fdbd744a5a560df3c6f620b266cd1 (patch)
tree7bee938788d10ee14426ee616f37f75e7d5f22f0 /tests/tests.py
parent09b658f69969ef998b5994156f92f7b645aaf619 (diff)
downloadgem5-2093d84a774fdbd744a5a560df3c6f620b266cd1.tar.xz
fastmodel: Mostly collapse ARM base classes for the CortexA76 CPU.
Fast models are in practice only ARM, so it's not that helpful to have the ARM-ness factored out. It is, however, helpful to have aspects which control how gem5 concepts like registers are mapped to fast model concepts like resources, especially since these mappings may vary from fast model to fast model. For instance, it looks like the CortexA76 does not have predicate vector registers. Rather than make all fast models support or not support those registers, that can be done on a model by model basis. Change-Id: I195da4a2f4d2f8593032d0d63e9fd3d20a240d01 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23786 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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