diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2012-04-24 00:48:57 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2012-04-24 00:48:57 -0700 |
| commit | 312b6fe43b3be7bd1618bb6ffd7810787eea75a0 (patch) | |
| tree | ce44a51fd121c42d4bc5fe9309cdf06c18b166f2 /tests | |
| parent | 64bf90dca3b050591386cfc09121a54733f57706 (diff) | |
| download | gem5-312b6fe43b3be7bd1618bb6ffd7810787eea75a0.tar.xz | |
X86: Update stats for the slightly changed TLB behavior.
Diffstat (limited to 'tests')
4 files changed, 814 insertions, 808 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index a45397a7d..f04a1d212 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -20,7 +20,6 @@ load_addr_mask=18446744073709551615 mem_mode=timing memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile=tests/halt.sh smbios_table=system.smbios_table symbolfile= @@ -31,7 +30,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[3] +system_port=system.membus.slave[1] [system.acpi_description_table_pointer] type=X86ACPIRSDP @@ -58,8 +57,8 @@ ranges=11529215046068469760:11529215046068473855 req_size=16 resp_size=16 write_ack=false -master=system.membus.port[2] -slave=system.iobus.port[1] +master=system.membus.slave[0] +slave=system.iobus.master[0] [system.bridge] type=Bridge @@ -69,8 +68,8 @@ ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 1383505805 req_size=16 resp_size=16 write_ack=false -master=system.iobus.port[0] -slave=system.membus.port[1] +master=system.iobus.slave[0] +slave=system.membus.master[1] [system.cpu] type=DerivO3CPU @@ -171,7 +170,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=4 block_size=64 forward_snoops=true @@ -192,7 +191,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.toL2Bus.port[2] +mem_side=system.toL2Bus.slave[1] [system.cpu.dtb] type=X86TLB @@ -207,7 +206,7 @@ port=system.cpu.dtb_walker_cache.cpu_side [system.cpu.dtb_walker_cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -228,7 +227,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dtb.walker.port -mem_side=system.toL2Bus.port[4] +mem_side=system.toL2Bus.slave[3] [system.cpu.fuPool] type=FUPool @@ -495,7 +494,7 @@ opLat=3 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=1 block_size=64 forward_snoops=true @@ -516,7 +515,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.toL2Bus.port[1] +mem_side=system.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic @@ -524,8 +523,9 @@ int_latency=1000 pio_addr=2305843009213693952 pio_latency=1000 system=system -int_port=system.membus.port[7] -pio=system.membus.port[6] +int_master=system.membus.slave[4] +int_slave=system.membus.master[3] +pio=system.membus.master[2] [system.cpu.itb] type=X86TLB @@ -540,7 +540,7 @@ port=system.cpu.itb_walker_cache.cpu_side [system.cpu.itb_walker_cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -561,7 +561,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.itb.walker.port -mem_side=system.toL2Bus.port[3] +mem_side=system.toL2Bus.slave[2] [system.cpu.tracer] type=ExeTracer @@ -938,11 +938,12 @@ header_cycles=1 use_default_range=true width=64 default=system.pc.pciconfig.pio -port=system.bridge.master system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side +master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side +slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master [system.iocache] type=BaseCache -addr_range=0:134217727 +addr_ranges=0:134217727 assoc=8 block_size=64 forward_snoops=false @@ -962,12 +963,12 @@ tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.iobus.port[21] -mem_side=system.membus.port[4] +cpu_side=system.iobus.master[18] +mem_side=system.membus.slave[2] [system.l2c] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=8 block_size=64 forward_snoops=true @@ -987,8 +988,8 @@ tgts_per_mshr=16 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.toL2Bus.port[0] -mem_side=system.membus.port[5] +cpu_side=system.toL2Bus.master[0] +mem_side=system.membus.slave[3] [system.membus] type=Bus @@ -1000,7 +1001,8 @@ header_cycles=1 use_default_range=false width=64 default=system.membus.badaddr_responder.pio -port=system.physmem.port[0] system.bridge.slave system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port +master=system.physmem.port[0] system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave +slave=system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.int_master [system.membus.badaddr_responder] type=IsaFake @@ -1038,7 +1040,7 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.port[15] +pio=system.iobus.master[12] [system.pc.com_1] type=Uart8250 @@ -1048,7 +1050,7 @@ pio_latency=1000 platform=system.pc system=system terminal=system.pc.com_1.terminal -pio=system.iobus.port[16] +pio=system.iobus.master[13] [system.pc.com_1.terminal] type=Terminal @@ -1078,7 +1080,7 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.port[17] +pio=system.iobus.master[14] [system.pc.fake_com_3] type=IsaFake @@ -1094,7 +1096,7 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.port[18] +pio=system.iobus.master[15] [system.pc.fake_com_4] type=IsaFake @@ -1110,7 +1112,7 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.port[19] +pio=system.iobus.master[16] [system.pc.fake_floppy] type=IsaFake @@ -1126,7 +1128,7 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.port[20] +pio=system.iobus.master[17] [system.pc.i_dont_exist] type=IsaFake @@ -1142,7 +1144,7 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.port[14] +pio=system.iobus.master[11] [system.pc.pciconfig] type=PciConfigAll @@ -1175,7 +1177,7 @@ pio_addr=9223372036854775920 pio_latency=1000 system=system time=Sun Jan 1 00:00:00 2012 -pio=system.iobus.port[2] +pio=system.iobus.master[1] [system.pc.south_bridge.cmos.int_pin] type=X86IntSourcePin @@ -1185,7 +1187,7 @@ type=I8237 pio_addr=9223372036854775808 pio_latency=1000 system=system -pio=system.iobus.port[3] +pio=system.iobus.master[2] [system.pc.south_bridge.ide] type=IdeController @@ -1240,9 +1242,9 @@ pci_func=0 pio_latency=1000 platform=system.pc system=system -config=system.iobus.port[5] -dma=system.iobus.port[6] -pio=system.iobus.port[4] +config=system.iobus.master[4] +dma=system.iobus.slave[1] +pio=system.iobus.master[3] [system.pc.south_bridge.ide.disks0] type=IdeDisk @@ -1369,8 +1371,8 @@ int_latency=1000 pio_addr=4273995776 pio_latency=1000 system=system -int_port=system.iobus.port[13] -pio=system.iobus.port[12] +int_master=system.iobus.slave[2] +pio=system.iobus.master[10] [system.pc.south_bridge.keyboard] type=I8042 @@ -1382,7 +1384,7 @@ mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin pio_addr=0 pio_latency=1000 system=system -pio=system.iobus.port[7] +pio=system.iobus.master[5] [system.pc.south_bridge.keyboard.keyboard_int_pin] type=X86IntSourcePin @@ -1399,7 +1401,7 @@ pio_addr=9223372036854775840 pio_latency=1000 slave=system.pc.south_bridge.pic2 system=system -pio=system.iobus.port[8] +pio=system.iobus.master[6] [system.pc.south_bridge.pic1.output] type=X86IntSourcePin @@ -1413,7 +1415,7 @@ pio_addr=9223372036854775968 pio_latency=1000 slave=Null system=system -pio=system.iobus.port[9] +pio=system.iobus.master[7] [system.pc.south_bridge.pic2.output] type=X86IntSourcePin @@ -1425,7 +1427,7 @@ int_pin=system.pc.south_bridge.pit.int_pin pio_addr=9223372036854775872 pio_latency=1000 system=system -pio=system.iobus.port[10] +pio=system.iobus.master[8] [system.pc.south_bridge.pit.int_pin] type=X86IntSourcePin @@ -1436,17 +1438,19 @@ i8254=system.pc.south_bridge.pit pio_addr=9223372036854775905 pio_latency=1000 system=system -pio=system.iobus.port[11] +pio=system.iobus.master[9] [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[0] +port=system.membus.master[0] [system.smbios_table] type=X86SMBiosSMBiosTable @@ -1477,5 +1481,6 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side +master=system.l2c.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index e4f17be50..379525fde 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,12 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 12 2012 17:18:12 -gem5 started Feb 12 2012 19:53:18 -gem5 executing on zizzer -command line: build/X86/gem5.fast -d build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-o3-timing +gem5 compiled Apr 22 2012 22:41:43 +gem5 started Apr 22 2012 23:27:12 +gem5 executing on burrito +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 + 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5155288336500 because m5_exit instruction encountered +Exiting @ tick 5169499540500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 1c3be5421..0afcdd36b 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,151 +1,151 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.155288 # Number of seconds simulated -sim_ticks 5155288336500 # Number of ticks simulated -final_tick 5155288336500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.169500 # Number of seconds simulated +sim_ticks 5169499540500 # Number of ticks simulated +final_tick 5169499540500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 187724 # Simulator instruction rate (inst/s) -host_op_rate 369929 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2268413480 # Simulator tick rate (ticks/s) -host_mem_usage 362380 # Number of bytes of host memory used -host_seconds 2272.64 # Real time elapsed on the host -sim_insts 426629675 # Number of instructions simulated -sim_ops 840716593 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 15943680 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1259264 # Number of instructions bytes read from this memory -system.physmem.bytes_written 12043648 # Number of bytes written to this memory -system.physmem.num_reads 249120 # Number of read requests responded to by this memory -system.physmem.num_writes 188182 # Number of write requests responded to by this memory +host_inst_rate 164266 # Simulator instruction rate (inst/s) +host_op_rate 323704 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1990886287 # Simulator tick rate (ticks/s) +host_mem_usage 388036 # Number of bytes of host memory used +host_seconds 2596.58 # Real time elapsed on the host +sim_insts 426530860 # Number of instructions simulated +sim_ops 840523890 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 15909184 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1237824 # Number of instructions bytes read from this memory +system.physmem.bytes_written 12067392 # Number of bytes written to this memory +system.physmem.num_reads 248581 # Number of read requests responded to by this memory +system.physmem.num_writes 188553 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 3092684 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 244266 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 2336174 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 5428858 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 167456 # number of replacements -system.l2c.tagsinuse 37822.927931 # Cycle average of tags in use -system.l2c.total_refs 3846980 # Total number of references to valid blocks. -system.l2c.sampled_refs 202165 # Sample count of references to valid blocks. -system.l2c.avg_refs 19.028912 # Average number of references to valid blocks. +system.physmem.bw_read 3077510 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 239448 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 2334344 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 5411854 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 167476 # number of replacements +system.l2c.tagsinuse 37831.311454 # Cycle average of tags in use +system.l2c.total_refs 3834095 # Total number of references to valid blocks. +system.l2c.sampled_refs 201653 # Sample count of references to valid blocks. +system.l2c.avg_refs 19.013330 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 26706.608582 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 11.179185 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.034739 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 2430.963092 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 8674.142332 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.407511 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000171 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 26693.996125 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 11.281842 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.035682 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 2446.646461 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 8679.351345 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.407318 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000172 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.037094 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.132357 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.577132 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 117941 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 9215 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 1064505 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 1335031 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2526692 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1602581 # number of Writeback hits -system.l2c.Writeback_hits::total 1602581 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 322 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 322 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 151453 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 151453 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 117941 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 9215 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 1064505 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1486484 # number of demand (read+write) hits -system.l2c.demand_hits::total 2678145 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 117941 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 9215 # number of overall hits -system.l2c.overall_hits::cpu.inst 1064505 # number of overall hits -system.l2c.overall_hits::cpu.data 1486484 # number of overall hits -system.l2c.overall_hits::total 2678145 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 98 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 19677 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 45243 # number of ReadReq misses -system.l2c.ReadReq_misses::total 65025 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 2687 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2687 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 141494 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 141494 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 98 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 19677 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 186737 # number of demand (read+write) misses -system.l2c.demand_misses::total 206519 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 98 # number of overall misses -system.l2c.overall_misses::cpu.itb.walker 7 # number of overall misses -system.l2c.overall_misses::cpu.inst 19677 # number of overall misses -system.l2c.overall_misses::cpu.data 186737 # number of overall misses -system.l2c.overall_misses::total 206519 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.dtb.walker 5116000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.itb.walker 364000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 1028234500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 2378237500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 3411952000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 39192000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 39192000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 7368603000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7368603000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.dtb.walker 5116000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.itb.walker 364000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 1028234500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 9746840500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 10780555000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.dtb.walker 5116000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.itb.walker 364000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.inst 1028234500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 9746840500 # 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number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1230144500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 61206131500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 61206131500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000830 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000759 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.018148 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.032778 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.892988 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.483002 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000830 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000759 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.018148 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.111603 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000830 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000759 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.018148 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.111603 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40076.530612 # average ReadReq mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 104 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.itb.walker 11 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.inst 19341 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 45290 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 64746 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 2653 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2653 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 141019 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 141019 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.dtb.walker 104 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.itb.walker 11 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 19341 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 186309 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 205765 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.dtb.walker 104 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.itb.walker 11 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 19341 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 186309 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 205765 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 4167500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 440000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 774472500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 1827120500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 2606200500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 106465000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 106465000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5642238000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5642238000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 4167500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.itb.walker 440000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 774472500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 7469358500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 8248438500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 4167500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.itb.walker 440000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 774472500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 7469358500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 8248438500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 59975752000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 59975752000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1229777500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1229777500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 61205529500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 61205529500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000945 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001186 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017836 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.032808 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.891166 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.482200 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000945 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001186 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.017836 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.111370 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000945 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001186 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.017836 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.111370 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40072.115385 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40042.640781 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40341.894700 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40135.839226 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40010.385599 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40076.530612 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40043.043276 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40342.691543 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40130.041462 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40010.480857 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40072.115385 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40042.640781 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40090.702917 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40076.530612 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40043.043276 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40091.238212 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40072.115385 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40042.640781 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40090.702917 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40043.043276 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40091.238212 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47576 # number of replacements -system.iocache.tagsinuse 0.159321 # Cycle average of tags in use +system.iocache.replacements 47577 # number of replacements +system.iocache.tagsinuse 0.202876 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47592 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47593 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 4996368196000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.159321 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.009958 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.009958 # Average percentage of cache occupancy +system.iocache.occ_blocks::pc.south_bridge.ide 0.202876 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.012680 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.012680 # Average percentage of cache occupancy system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses system.iocache.ReadReq_misses::total 911 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses @@ -258,14 +258,14 @@ system.iocache.demand_misses::pc.south_bridge.ide 47631 system.iocache.demand_misses::total 47631 # number of demand (read+write) misses system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses system.iocache.overall_misses::total 47631 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 114195932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 114195932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6370894160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 6370894160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 6485090092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 6485090092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 6485090092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 6485090092 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 114136932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 114136932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6374051160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 6374051160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 6488188092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 6488188092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 6488188092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 6488188092 # number of overall miss cycles system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) @@ -278,20 +278,20 @@ system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 125352.285401 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136363.316781 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136152.717600 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136152.717600 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 68835510 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 125287.521405 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136430.889555 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136217.759274 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136217.759274 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 68852524 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11261 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11251 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6112.735103 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6119.680384 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 46667 # number of writebacks -system.iocache.writebacks::total 46667 # number of writebacks +system.iocache.writebacks::writebacks 46668 # number of writebacks +system.iocache.writebacks::total 46668 # number of writebacks system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses @@ -300,22 +300,22 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 66802976 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 66802976 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3941136864 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3941136864 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4007939840 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4007939840 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4007939840 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4007939840 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 66741982 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 66741982 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3944293874 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3944293874 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4011035856 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4011035856 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4011035856 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4011035856 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 73329.282108 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84356.525342 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84145.616090 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84145.616090 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 73262.329308 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84424.098330 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84210.616111 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84210.616111 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -329,395 +329,395 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 461736319 # number of cpu cycles simulated +system.cpu.numCycles 461361546 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 90084371 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 90084371 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1179546 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 84316538 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 81732802 # Number of BTB hits +system.cpu.BPredUnit.lookups 90046229 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 90046229 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1176099 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 84310101 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 81718791 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 29640549 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 447158079 # Number of instructions fetch has processed -system.cpu.fetch.Branches 90084371 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 81732802 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 169862026 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5320379 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 145881 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 102119338 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 37850 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 39504 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 372 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9392758 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 524186 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5360 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 305948772 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.876024 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.383488 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29608637 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 447015807 # Number of instructions fetch has processed +system.cpu.fetch.Branches 90046229 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 81718791 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 169801708 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5302195 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 145260 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 101860609 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 38090 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 39269 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 431 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9372396 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 523997 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5250 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 305583315 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.878441 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.383859 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 136524607 44.62% 44.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1781462 0.58% 45.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72780882 23.79% 68.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 993009 0.32% 69.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1639605 0.54% 69.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3682017 1.20% 71.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1148071 0.38% 71.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1456036 0.48% 71.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 85943083 28.09% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 136218016 44.58% 44.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1767126 0.58% 45.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72778652 23.82% 68.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 988391 0.32% 69.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1638096 0.54% 69.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3679779 1.20% 71.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1146175 0.38% 71.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1451143 0.47% 71.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 85915937 28.12% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 305948772 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.195099 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.968427 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 34742596 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 98230101 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 164036692 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4836131 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4103252 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 876669813 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 827 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4103252 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 39030266 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 68185463 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10584671 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 164072016 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 19973104 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 872862955 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 10194 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 12946310 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3889382 # Number of times rename has blocked due to LSQ full +system.cpu.fetch.rateDist::total 305583315 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.195175 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.968906 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 34706026 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 97971351 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 163987110 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4829517 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4089311 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 876370840 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 830 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4089311 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 38986696 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 68087703 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10443345 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 164022583 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 19953677 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 872580437 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 9956 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 12941208 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3881940 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 874188806 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1710305089 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1710304369 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 720 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 843320455 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 30868344 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 477917 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 485258 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 46626951 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 18944692 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10483519 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1301190 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1038101 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 865973387 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1727922 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 864611178 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 114248 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26054957 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 37073399 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 207270 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 305948772 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.826000 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.403043 # Number of insts issued each cycle +system.cpu.rename.RenamedOperands 873928862 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1709683510 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1709682778 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 732 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 843141263 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 30787592 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 471317 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 478659 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 46567853 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 18906689 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10452552 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1298619 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1044286 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 865700998 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1721462 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 864366018 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 113102 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 25970693 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 36970619 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 205740 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 305583315 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.828577 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.402836 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 99370843 32.48% 32.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 25451279 8.32% 40.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 14262788 4.66% 45.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 9410835 3.08% 48.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 79123808 25.86% 74.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4863158 1.59% 75.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72802263 23.80% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 533166 0.17% 99.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 130632 0.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 99104201 32.43% 32.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 25415077 8.32% 40.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 14237257 4.66% 45.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 9395044 3.07% 48.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 79117426 25.89% 74.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4854972 1.59% 75.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72798510 23.82% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 530953 0.17% 99.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 129875 0.04% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 305948772 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 305583315 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 169581 8.02% 8.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1777046 84.08% 92.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 166802 7.89% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 169376 8.03% 8.03% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.03% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1775092 84.15% 92.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 164908 7.82% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 304260 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 829639344 95.96% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25194661 2.91% 98.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9472913 1.10% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 297276 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 829460280 95.96% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25161401 2.91% 98.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9447061 1.09% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 864611178 # Type of FU issued -system.cpu.iq.rate 1.872521 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2113429 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.002444 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2037542293 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 893767044 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 854207329 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 316 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 340 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 80 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 866420202 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 145 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1589122 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 864366018 # Type of FU issued +system.cpu.iq.rate 1.873511 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2109376 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.002440 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2036675779 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 893403890 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 853968919 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 282 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 338 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 72 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 866177988 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 130 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1585170 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3614563 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 21772 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12029 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2051269 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3604924 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 21755 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11989 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2042240 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7821662 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2623 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7821681 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2629 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4103252 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 45514835 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6136303 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 867701309 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 314417 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 18944692 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10483519 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 889203 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 5413874 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12817 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12029 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 702671 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 628126 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1330797 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 862708188 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24767979 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1902989 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4089311 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 45428780 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6134519 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 867422460 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 315149 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 18906689 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10452552 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 882877 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 5413459 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12395 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11989 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 702330 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 623988 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1326318 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 862468357 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24736140 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1897660 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 33996128 # number of memory reference insts executed -system.cpu.iew.exec_branches 86527576 # Number of branches executed -system.cpu.iew.exec_stores 9228149 # Number of stores executed -system.cpu.iew.exec_rate 1.868400 # Inst execution rate -system.cpu.iew.wb_sent 862244747 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 854207409 # cumulative count of insts written-back -system.cpu.iew.wb_producers 668533054 # num instructions producing a value -system.cpu.iew.wb_consumers 1167360089 # num instructions consuming a value +system.cpu.iew.exec_refs 33938822 # number of memory reference insts executed +system.cpu.iew.exec_branches 86500210 # Number of branches executed +system.cpu.iew.exec_stores 9202682 # Number of stores executed +system.cpu.iew.exec_rate 1.869398 # Inst execution rate +system.cpu.iew.wb_sent 862004512 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 853968991 # cumulative count of insts written-back +system.cpu.iew.wb_producers 668394030 # num instructions producing a value +system.cpu.iew.wb_consumers 1167144528 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.849990 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.572688 # average fanout of values written-back +system.cpu.iew.wb_rate 1.850976 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.572675 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 426629675 # The number of committed instructions -system.cpu.commit.commitCommittedOps 840716593 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 26871696 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1520650 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1183899 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 301861557 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.785107 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.863294 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 426530860 # The number of committed instructions +system.cpu.commit.commitCommittedOps 840523890 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 26793490 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1515720 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1180385 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 301509545 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.787719 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.863521 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 121093745 40.12% 40.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14426665 4.78% 44.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4304237 1.43% 46.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 76676312 25.40% 71.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3920373 1.30% 73.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1782325 0.59% 73.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1109784 0.37% 73.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71984231 23.85% 97.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6563885 2.17% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 120813310 40.07% 40.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14395799 4.77% 44.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4294572 1.42% 46.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 76662723 25.43% 71.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3914441 1.30% 72.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1779119 0.59% 73.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1107804 0.37% 73.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71983621 23.87% 97.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6558156 2.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 301861557 # Number of insts commited each cycle -system.cpu.commit.committedInsts 426629675 # Number of instructions committed -system.cpu.commit.committedOps 840716593 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 301509545 # Number of insts commited each cycle +system.cpu.commit.committedInsts 426530860 # Number of instructions committed +system.cpu.commit.committedOps 840523890 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 23762376 # Number of memory references committed -system.cpu.commit.loads 15330126 # Number of loads committed -system.cpu.commit.membars 781563 # Number of memory barriers committed -system.cpu.commit.branches 85529575 # Number of branches committed +system.cpu.commit.refs 23712074 # Number of memory references committed +system.cpu.commit.loads 15301762 # Number of loads committed +system.cpu.commit.membars 781561 # Number of memory barriers committed +system.cpu.commit.branches 85507623 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 768542107 # Number of committed integer instructions. +system.cpu.commit.int_insts 768350160 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6563885 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6558156 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1162802870 # The number of ROB reads -system.cpu.rob.rob_writes 1739294618 # The number of ROB writes -system.cpu.timesIdled 2882631 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 155787547 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9848837790 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 426629675 # Number of Instructions Simulated -system.cpu.committedOps 840716593 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 426629675 # Number of Instructions Simulated -system.cpu.cpi 1.082288 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.082288 # CPI: Total CPI of All Threads -system.cpu.ipc 0.923968 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.923968 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1404705112 # number of integer regfile reads -system.cpu.int_regfile_writes 855482985 # number of integer regfile writes -system.cpu.fp_regfile_reads 80 # number of floating regfile reads -system.cpu.misc_regfile_reads 281196998 # number of misc regfile reads -system.cpu.misc_regfile_writes 410876 # number of misc regfile writes -system.cpu.icache.replacements 1083725 # number of replacements -system.cpu.icache.tagsinuse 510.022776 # Cycle average of tags in use -system.cpu.icache.total_refs 8238065 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1084236 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.598037 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 1162189391 # The number of ROB reads +system.cpu.rob.rob_writes 1738738969 # The number of ROB writes +system.cpu.timesIdled 2883863 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 155778231 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9877634963 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 426530860 # Number of Instructions Simulated +system.cpu.committedOps 840523890 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 426530860 # Number of Instructions Simulated +system.cpu.cpi 1.081660 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.081660 # CPI: Total CPI of All Threads +system.cpu.ipc 0.924505 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.924505 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1404302602 # number of integer regfile reads +system.cpu.int_regfile_writes 855269990 # number of integer regfile writes +system.cpu.fp_regfile_reads 72 # number of floating regfile reads +system.cpu.misc_regfile_reads 281075555 # number of misc regfile reads +system.cpu.misc_regfile_writes 403685 # number of misc regfile writes +system.cpu.icache.replacements 1083950 # number of replacements +system.cpu.icache.tagsinuse 510.027693 # Cycle average of tags in use +system.cpu.icache.total_refs 8217570 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1084462 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.577555 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 56617488000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.022776 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996138 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996138 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 8238065 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8238065 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8238065 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8238065 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8238065 # number of overall hits -system.cpu.icache.overall_hits::total 8238065 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1154689 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1154689 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1154689 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1154689 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1154689 # number of overall misses -system.cpu.icache.overall_misses::total 1154689 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17243109487 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17243109487 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17243109487 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17243109487 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17243109487 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17243109487 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9392754 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9392754 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9392754 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9392754 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9392754 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9392754 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122934 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.122934 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.122934 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14933.120076 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14933.120076 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14933.120076 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2884989 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 510.027693 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996148 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996148 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 8217570 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8217570 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8217570 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8217570 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8217570 # number of overall hits +system.cpu.icache.overall_hits::total 8217570 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1154822 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1154822 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1154822 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1154822 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1154822 # number of overall misses +system.cpu.icache.overall_misses::total 1154822 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17227563988 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17227563988 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17227563988 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17227563988 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17227563988 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17227563988 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9372392 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9372392 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9372392 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9372392 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9372392 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9372392 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123215 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.123215 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.123215 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14917.938858 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14917.938858 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14917.938858 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2880990 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 300 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 292 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 9616.630000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 9866.404110 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 1570 # number of writebacks system.cpu.icache.writebacks::total 1570 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69164 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 69164 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 69164 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 69164 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 69164 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 69164 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1085525 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1085525 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1085525 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1085525 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1085525 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1085525 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13103385489 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13103385489 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13103385489 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13103385489 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13103385489 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13103385489 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115570 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115570 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115570 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12071.012173 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12071.012173 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12071.012173 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69061 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 69061 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 69061 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 69061 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 69061 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 69061 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1085761 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1085761 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1085761 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1085761 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1085761 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1085761 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13090786490 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13090786490 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13090786490 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13090786490 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13090786490 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13090786490 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115847 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115847 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115847 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12056.784587 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12056.784587 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12056.784587 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 11375 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.006905 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 28918 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 11386 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.539786 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5142961834000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.006905 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375432 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.375432 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 28987 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 28987 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 11295 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.030801 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 28582 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 11307 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.527815 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5144328078000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.030801 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376925 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.376925 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 28593 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 28593 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 28990 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 28990 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 28990 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 28990 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 12232 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 12232 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 12232 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 12232 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 12232 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 12232 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 154656000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 154656000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 154656000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 154656000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 154656000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 154656000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41219 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 41219 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 28596 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 28596 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 28596 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 28596 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 12165 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 12165 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 12165 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 12165 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 12165 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 12165 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 154895000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 154895000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 154895000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 154895000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 154895000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 154895000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 40758 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 40758 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41222 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 41222 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41222 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 41222 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.296756 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.296735 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.296735 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12643.557881 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12643.557881 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12643.557881 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 40761 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 40761 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 40761 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 40761 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.298469 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.298447 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.298447 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12732.840115 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12732.840115 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12732.840115 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -726,66 +726,66 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1402 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1402 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 12232 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 12232 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 12232 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 12232 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 12232 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 12232 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 117502000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 117502000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 117502000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 117502000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 117502000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 117502000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.296756 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.296735 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.296735 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9606.115108 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9606.115108 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9606.115108 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1487 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1487 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 12165 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 12165 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 12165 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 12165 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 12165 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 12165 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 117952000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 117952000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 117952000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 117952000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 117952000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 117952000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.298469 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.298447 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.298447 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9696.013152 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9696.013152 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9696.013152 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 125889 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 12.942075 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 147310 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 125903 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.170028 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.replacements 117758 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 12.948183 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 134592 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 117774 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.142799 # Average number of references to valid blocks. system.cpu.dtb_walker_cache.warmup_cycle 5108639465000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.942075 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.808880 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.808880 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 147324 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 147324 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 147324 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 147324 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 147324 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 147324 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 126858 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 126858 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 126858 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 126858 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 126858 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 126858 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1765137000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1765137000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1765137000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 1765137000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1765137000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 1765137000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 274182 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 274182 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 274182 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 274182 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 274182 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 274182 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.462678 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.462678 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.462678 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13914.274228 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13914.274228 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13914.274228 # average overall miss latency +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.948183 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.809261 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.809261 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 134592 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 134592 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 134592 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 134592 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 134592 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 134592 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 118727 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 118727 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 118727 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 118727 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 118727 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 118727 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1650934500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1650934500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1650934500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 1650934500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1650934500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 1650934500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 253319 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 253319 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 253319 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 253319 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 253319 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 253319 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.468686 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.468686 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.468686 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13905.299553 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13905.299553 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13905.299553 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -794,124 +794,124 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 38155 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 38155 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 126858 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 126858 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 126858 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 126858 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 126858 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 126858 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1381422000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1381422000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1381422000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1381422000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1381422000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1381422000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.462678 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.462678 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.462678 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10889.514260 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10889.514260 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10889.514260 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 34129 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 34129 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 118727 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 118727 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 118727 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 118727 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 118727 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 118727 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1291951000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1291951000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1291951000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1291951000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1291951000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1291951000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.468686 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.468686 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.468686 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10881.694981 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10881.694981 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10881.694981 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1673228 # number of replacements -system.cpu.dcache.tagsinuse 511.997037 # Cycle average of tags in use -system.cpu.dcache.total_refs 19088314 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1673740 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.404587 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1672937 # number of replacements +system.cpu.dcache.tagsinuse 511.997030 # Cycle average of tags in use +system.cpu.dcache.total_refs 19038676 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1673449 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.376908 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 34328000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997037 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.997030 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 10979879 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10979879 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8104687 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8104687 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19084566 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19084566 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19084566 # number of overall hits -system.cpu.dcache.overall_hits::total 19084566 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2411794 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2411794 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 318210 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 318210 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2730004 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2730004 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2730004 # number of overall misses -system.cpu.dcache.overall_misses::total 2730004 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 36160191000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36160191000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10588613980 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10588613980 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 46748804980 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 46748804980 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 46748804980 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 46748804980 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13391673 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13391673 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8422897 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8422897 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21814570 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21814570 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21814570 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21814570 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180097 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037779 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.125146 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.125146 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14993.067816 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33275.553817 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17124.079298 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17124.079298 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 23292480 # number of cycles access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 10951636 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10951636 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8083299 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8083299 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19034935 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19034935 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19034935 # number of overall hits +system.cpu.dcache.overall_hits::total 19034935 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2412266 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2412266 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 317673 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 317673 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2729939 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2729939 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2729939 # number of overall misses +system.cpu.dcache.overall_misses::total 2729939 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 36171443000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36171443000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10559722481 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10559722481 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 46731165481 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 46731165481 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 46731165481 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 46731165481 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13363902 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13363902 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8400972 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8400972 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21764874 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21764874 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21764874 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21764874 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180506 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037814 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.125429 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.125429 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14994.798666 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33240.856104 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17118.025524 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17118.025524 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 23782481 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3427 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3499 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6796.755179 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6796.936553 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1561454 # number of writebacks -system.cpu.dcache.writebacks::total 1561454 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1030426 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1030426 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22364 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 22364 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1052790 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1052790 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1052790 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1052790 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1381368 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1381368 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 295846 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 295846 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1677214 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1677214 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1677214 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1677214 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18158276000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 18158276000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9372225480 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9372225480 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27530501480 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27530501480 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27530501480 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27530501480 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 85208380500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 85208380500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1393791500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1393791500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86602172000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 86602172000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103151 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035124 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076885 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076885 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13145.140180 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31679.405772 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16414.423848 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16414.423848 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1561356 # number of writebacks +system.cpu.dcache.writebacks::total 1561356 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1030690 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1030690 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22348 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 22348 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1053038 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1053038 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1053038 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1053038 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1381576 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1381576 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 295325 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 295325 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1676901 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1676901 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1676901 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1676901 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18163645000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 18163645000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9344995981 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9344995981 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27508640981 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27508640981 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27508640981 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27508640981 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 85208124500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 85208124500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1393505500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1393505500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86601630000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 86601630000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103381 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035154 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077046 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077046 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13147.047285 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31643.091445 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16404.451414 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16404.451414 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal index 6cae7ef0f..f0dc7f01e 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal @@ -39,7 +39,7 @@ ACPI: Core revision 20070126 ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
ACPI: Unable to load the System Description Tables
Using local APIC timer interrupts.
-result 7812498
+result 7812499
Detected 7.812 MHz APIC timer.
NET: Registered protocol family 16
PCI: Using configuration type 1
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