inorder: Fix up some reference stats.

6 files changed, 112 insertions, 112 deletions

diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
index 83e53a5c0..ca54a43c1 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
@@ -190,7 +190,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/n/poolfs/z/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
index 284845884..b0f68db24 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled May 12 2009 12:20:30
-M5 revision 2eebd457f8fc 6197 default qtip tip inorder-vortex-regress
-M5 started May 12 2009 12:20:31
-M5 executing on zooks
+M5 compiled Jul  4 2009 20:43:52
+M5 revision 20167772fb15 6281 default tip
+M5 started Jul  4 2009 20:43:52
+M5 executing on tater
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
index c3b1c377a..2791e3ab6 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  51305                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 216648                       # Number of bytes of host memory used
-host_seconds                                  1721.87                       # Real time elapsed on the host
-host_tick_rate                               63437429                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  66323                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 296324                       # Number of bytes of host memory used
+host_seconds                                  1331.98                       # Real time elapsed on the host
+host_tick_rate                               81990812                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    88340673                       # Number of instructions simulated
-sim_seconds                                  0.109231                       # Number of seconds simulated
-sim_ticks                                109230836500                       # Number of ticks simulated
+sim_seconds                                  0.109210                       # Number of seconds simulated
+sim_ticks                                109210014500                       # Number of ticks simulated
 system.cpu.AGEN-Unit.instReqsProcessed       35224018                       # Number of Instructions Requests that completed in this resource.
 system.cpu.Branch-Predictor.instReqsProcessed     88340674                       # Number of Instructions Requests that completed in this resource.
 system.cpu.Branch-Predictor.predictedNotTaken     10443271                       # Number of Branches Predicted As Not Taken (False).
@@ -28,27 +28,27 @@ system.cpu.Mult-Div-Unit.multInstReqsProcessed        41101
 system.cpu.RegFile-Manager.instReqsProcessed    158796488                       # Number of Instructions Requests that completed in this resource.
 system.cpu.committedInsts                    88340673                       # Number of Instructions Simulated (Per-Thread)
 system.cpu.committedInsts_total              88340673                       # Number of Instructions Simulated (Total)
-system.cpu.cpi                               2.472946                       # CPI: Cycles Per Instruction (Per-Thread)
-system.cpu.cpi_total                         2.472946                       # CPI: Total CPI of All Threads
+system.cpu.cpi                               2.472474                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi_total                         2.472474                       # CPI: Total CPI of All Threads
 system.cpu.dcache.ReadReq_accesses           20276638                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 38182.186102                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35069.874601                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 38181.240129                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35069.166968                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits               20215854                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency     2320866000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency     2320808500                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.002998                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses                60784                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_mshr_hits                18                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency   2131056000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency   2131013000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.002997                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses           60766                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses          14613377                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56050.509703                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53050.509703                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 56049.825426                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53049.825426                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_hits              14463584                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency    8395974000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency    8395871500                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_rate         0.010250                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_misses              149793                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency   7946595000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   7946492500                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.010250                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_misses         149793                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
@@ -60,29 +60,29 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses            34890015                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 50892.737573                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 47861.411766                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 50891.977756                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 47860.720748                       # average overall mshr miss latency
 system.cpu.dcache.demand_hits                34679438                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     10716840000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency     10716680000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.006035                       # miss rate for demand accesses
 system.cpu.dcache.demand_misses                210577                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                 18                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  10077651000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency  10077505500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.006035                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_misses           210559                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.overall_accesses           34890015                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 50892.737573                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 47861.411766                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 50891.977756                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 47860.720748                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits               34679438                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    10716840000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency    10716680000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.006035                       # miss rate for overall accesses
 system.cpu.dcache.overall_misses               210577                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                18                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  10077651000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency  10077505500                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.006035                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_misses          210559                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -90,7 +90,7 @@ system.cpu.dcache.overall_mshr_uncacheable_misses            0
 system.cpu.dcache.replacements                 200248                       # number of replacements
 system.cpu.dcache.sampled_refs                 204344                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4077.186045                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4077.182458                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                 34685659                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              848449000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                   147714                       # number of writebacks
@@ -112,14 +112,14 @@ system.cpu.dtb.write_acv                            0                       # DT
 system.cpu.dtb.write_hits                    14613377                       # DTB write hits
 system.cpu.dtb.write_misses                      7252                       # DTB write misses
 system.cpu.icache.ReadReq_accesses           96166938                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 19084.255120                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 15849.213376                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 19084.949617                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 15849.033723                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits               96087744                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency     1511358500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency     1511413500                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000824                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                79194                       # number of ReadReq misses
 system.cpu.icache.ReadReq_mshr_hits              1266                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency   1235097500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency   1235083500                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000810                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses           77928                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
@@ -131,29 +131,29 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses            96166938                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 19084.255120                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 15849.213376                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 19084.949617                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 15849.033723                       # average overall mshr miss latency
 system.cpu.icache.demand_hits                96087744                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency      1511358500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency      1511413500                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000824                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                 79194                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits               1266                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency   1235097500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency   1235083500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000810                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses            77928                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.overall_accesses           96166938                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 19084.255120                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 15849.213376                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 19084.949617                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 15849.033723                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits               96087744                       # number of overall hits
-system.cpu.icache.overall_miss_latency     1511358500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency     1511413500                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000824                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                79194                       # number of overall misses
 system.cpu.icache.overall_mshr_hits              1266                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency   1235097500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency   1235083500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000810                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses           77928                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -161,13 +161,13 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                  75882                       # number of replacements
 system.cpu.icache.sampled_refs                  77928                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1874.324882                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               1874.320715                       # Cycle average of tags in use
 system.cpu.icache.total_refs                 96087744                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.icache_port.instReqsProcessed     96166940                       # Number of Instructions Requests that completed in this resource.
-system.cpu.ipc                               0.404376                       # IPC: Instructions Per Cycle (Per-Thread)
-system.cpu.ipc_total                         0.404376                       # IPC: Total IPC of All Threads
+system.cpu.ipc                               0.404453                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.ipc_total                         0.404453                       # IPC: Total IPC of All Threads
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_hits                            0                       # DTB hits
@@ -185,28 +185,28 @@ system.cpu.itb.write_acv                            0                       # DT
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.l2cache.ReadExReq_accesses          143578                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52039.532519                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52038.849963                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000.083578                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency   7471732000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   7471634000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_misses            143578                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_mshr_miss_latency   5743132000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_misses       143578                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadReq_accesses            138694                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52317.460317                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 52316.057051                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40003.485162                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_hits                 95224                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency    2274240000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency    2274179000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_rate         0.313424                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_misses               43470                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_mshr_miss_latency   1738951500                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate     0.313424                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses          43470                       # number of ReadReq MSHR misses
 system.cpu.l2cache.UpgradeReq_accesses           6215                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51994.529364                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 51993.805310                       # average UpgradeReq miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000.884956                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency    323146000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency    323141500                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_misses             6215                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency    248605500                       # number of UpgradeReq MSHR miss cycles
@@ -223,10 +223,10 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.demand_accesses             282272                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52104.123006                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52103.272957                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency 40000.874107                       # average overall mshr miss latency
 system.cpu.l2cache.demand_hits                  95224                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency     9745972000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency     9745813000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_rate          0.662652                       # miss rate for demand accesses
 system.cpu.l2cache.demand_misses               187048                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
@@ -237,11 +237,11 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.l2cache.overall_accesses            282272                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52104.123006                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52103.272957                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 40000.874107                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_hits                 95224                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency    9745972000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency    9745813000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_rate         0.662652                       # miss rate for overall accesses
 system.cpu.l2cache.overall_misses              187048                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
@@ -253,16 +253,16 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses            0
 system.cpu.l2cache.replacements                147733                       # number of replacements
 system.cpu.l2cache.sampled_refs                172939                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             18262.964194                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             18262.944082                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                  110306                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                  120636                       # number of writebacks
-system.cpu.numCycles                        218461674                       # number of cpu cycles simulated
+system.cpu.numCycles                        218420030                       # number of cpu cycles simulated
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was simultaneous multithreading.(SMT)
 system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
 system.cpu.smt_ipc                           no_value                       # IPC: Total SMT-IPC
-system.cpu.threadCycles                     218461674                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles                     218420030                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.workload.PROG:num_syscalls            4583                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
index e86e90189..f04bd741b 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
@@ -190,7 +190,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/n/poolfs/z/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout
index 783130f31..4a762fa1c 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled May 12 2009 10:42:48
-M5 revision 40b296e9f790 6196 default qtip tip inorder-twolf-regress
-M5 started May 12 2009 10:42:49
-M5 executing on zooks
+M5 compiled Jul  4 2009 20:43:52
+M5 revision 20167772fb15 6281 default tip
+M5 started Jul  4 2009 20:43:52
+M5 executing on tater
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing
 Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sav
 Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
index cf845abd9..c58b2a060 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  52331                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 157196                       # Number of bytes of host memory used
-host_seconds                                  1756.17                       # Real time elapsed on the host
-host_tick_rate                               57825432                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  69440                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 210892                       # Number of bytes of host memory used
+host_seconds                                  1323.48                       # Real time elapsed on the host
+host_tick_rate                               76516395                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    91903056                       # Number of instructions simulated
-sim_seconds                                  0.101552                       # Number of seconds simulated
-sim_ticks                                101551554000                       # Number of ticks simulated
+sim_seconds                                  0.101268                       # Number of seconds simulated
+sim_ticks                                101268061000                       # Number of ticks simulated
 system.cpu.AGEN-Unit.instReqsProcessed       26537108                       # Number of Instructions Requests that completed in this resource.
 system.cpu.Branch-Predictor.instReqsProcessed     91903057                       # Number of Instructions Requests that completed in this resource.
 system.cpu.Branch-Predictor.predictedNotTaken      8198984                       # Number of Branches Predicted As Not Taken (False).
@@ -28,17 +28,17 @@ system.cpu.Mult-Div-Unit.multInstReqsProcessed       458252
 system.cpu.RegFile-Manager.instReqsProcessed    188816950                       # Number of Instructions Requests that completed in this resource.
 system.cpu.committedInsts                    91903056                       # Number of Instructions Simulated (Per-Thread)
 system.cpu.committedInsts_total              91903056                       # Number of Instructions Simulated (Total)
-system.cpu.cpi                               2.209971                       # CPI: Cycles Per Instruction (Per-Thread)
-system.cpu.cpi_total                         2.209971                       # CPI: Total CPI of All Threads
+system.cpu.cpi                               2.203802                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi_total                         2.203802                       # CPI: Total CPI of All Threads
 system.cpu.dcache.ReadReq_accesses           19996198                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 51625.779626                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48552.631579                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 51623.700624                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48550.526316                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits               19995717                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency       24832000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency       24831000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.000024                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses                  481                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_mshr_hits                 6                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency     23062500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency     23061500                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses             475                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses           6501103                       # number of WriteReq accesses(hits+misses)
@@ -60,29 +60,29 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses            26497301                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 55430.769231                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 52425.664096                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 55430.341880                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 52425.235647                       # average overall mshr miss latency
 system.cpu.dcache.demand_hits                26494961                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency       129708000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency       129707000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.000088                       # miss rate for demand accesses
 system.cpu.dcache.demand_misses                  2340                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  6                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency    122361500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency    122360500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.000088                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_misses             2334                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.overall_accesses           26497301                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 55430.769231                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 52425.664096                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 55430.341880                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 52425.235647                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits               26494961                       # number of overall hits
-system.cpu.dcache.overall_miss_latency      129708000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency      129707000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.000088                       # miss rate for overall accesses
 system.cpu.dcache.overall_misses                 2340                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 6                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency    122361500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency    122360500                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.000088                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_misses            2334                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -90,7 +90,7 @@ system.cpu.dcache.overall_mshr_uncacheable_misses            0
 system.cpu.dcache.replacements                    157                       # number of replacements
 system.cpu.dcache.sampled_refs                   2223                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               1441.841728                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               1441.819572                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                 26495076                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                      104                       # number of writebacks
@@ -112,14 +112,14 @@ system.cpu.dtb.write_acv                            0                       # DT
 system.cpu.dtb.write_hits                     6501103                       # DTB write hits
 system.cpu.dtb.write_misses                        23                       # DTB write misses
 system.cpu.icache.ReadReq_accesses           97683877                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 27281.166802                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 24026.033154                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 27282.787360                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 24026.266636                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits               97675238                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency      235682000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency      235696000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000088                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                 8639                       # number of ReadReq misses
 system.cpu.icache.ReadReq_mshr_hits                73                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency    205807000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency    205809000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000088                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses            8566                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
@@ -131,29 +131,29 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses            97683877                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 27281.166802                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 24026.033154                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 27282.787360                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 24026.266636                       # average overall mshr miss latency
 system.cpu.icache.demand_hits                97675238                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency       235682000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency       235696000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000088                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                  8639                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                 73                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency    205807000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    205809000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000088                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses             8566                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.overall_accesses           97683877                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 27281.166802                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 24026.033154                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 27282.787360                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 24026.266636                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits               97675238                       # number of overall hits
-system.cpu.icache.overall_miss_latency      235682000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency      235696000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000088                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                 8639                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                73                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency    205807000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    205809000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000088                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses            8566                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -161,13 +161,13 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                   6732                       # number of replacements
 system.cpu.icache.sampled_refs                   8566                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1428.662553                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               1428.614683                       # Cycle average of tags in use
 system.cpu.icache.total_refs                 97675238                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.icache_port.instReqsProcessed     97683876                       # Number of Instructions Requests that completed in this resource.
-system.cpu.ipc                               0.452495                       # IPC: Instructions Per Cycle (Per-Thread)
-system.cpu.ipc_total                         0.452495                       # IPC: Total IPC of All Threads
+system.cpu.ipc                               0.453761                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.ipc_total                         0.453761                       # IPC: Total IPC of All Threads
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_hits                            0                       # DTB hits
@@ -185,28 +185,28 @@ system.cpu.itb.write_acv                            0                       # DT
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.l2cache.ReadExReq_accesses            1748                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52413.329519                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52413.043478                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40003.432494                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency     91618500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency     91618000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_misses              1748                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_mshr_miss_latency     69926000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_misses         1748                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadReq_accesses              9041                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52240.287300                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 52240.613777                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40013.548808                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_hits                  5978                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency     160012000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency     160013000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_rate         0.338790                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_misses                3063                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_mshr_miss_latency    122561500                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate     0.338790                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses           3063                       # number of ReadReq MSHR misses
 system.cpu.l2cache.UpgradeReq_accesses            111                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 52409.909910                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 52414.414414                       # average UpgradeReq miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency      5817500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency      5818000                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_misses              111                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency      4440000                       # number of UpgradeReq MSHR miss cycles
@@ -223,10 +223,10 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.demand_accesses              10789                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52303.159426                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52303.263355                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency 40009.873207                       # average overall mshr miss latency
 system.cpu.l2cache.demand_hits                   5978                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency      251630500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency      251631000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_rate          0.445917                       # miss rate for demand accesses
 system.cpu.l2cache.demand_misses                 4811                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
@@ -237,11 +237,11 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.l2cache.overall_accesses             10789                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52303.159426                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52303.263355                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 40009.873207                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_hits                  5978                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency     251630500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency     251631000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_rate         0.445917                       # miss rate for overall accesses
 system.cpu.l2cache.overall_misses                4811                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
@@ -253,16 +253,16 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses            0
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.sampled_refs                  3030                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              2039.443667                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse              2039.371088                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                    5964                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.numCycles                        203103109                       # number of cpu cycles simulated
+system.cpu.numCycles                        202536123                       # number of cpu cycles simulated
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was simultaneous multithreading.(SMT)
 system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
 system.cpu.smt_ipc                           no_value                       # IPC: Total SMT-IPC
-system.cpu.threadCycles                     203103109                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles                     202536123                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.workload.PROG:num_syscalls             389                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------