diff options
| author | Gabe Black <gabeblack@google.com> | 2014-11-17 00:16:36 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2014-11-17 00:16:36 -0800 |
| commit | 994c44035d796791f80e108db821760a1e0c4e83 (patch) | |
| tree | a818f8e437bfc3e5e4abf8e903eac48d9f466cd4 /tests | |
| parent | d228db1143f3302af27cae477473a6489b19c565 (diff) | |
| download | gem5-994c44035d796791f80e108db821760a1e0c4e83.tar.xz | |
x86: Update the stats for the x86 FS o3 boot test.
Diffstat (limited to 'tests')
17 files changed, 1762 insertions, 1761 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index fe256a291..e3424a85b 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -20,7 +20,7 @@ eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/usr/local/google/home/gabeblack/gem5/x86_system_files/binaries/x86_64-vmlinux-2.6.22.9 kernel_addr_check=true load_addr_mask=18446744073709551615 load_offset=0 @@ -28,7 +28,7 @@ mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/usr/local/google/home/gabeblack/gem5/hg/gem5/tests/halt.sh smbios_table=system.smbios_table symbolfile= work_begin_ckpt_count=0 @@ -1560,7 +1560,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-x86.img +image_file=/usr/local/google/home/gabeblack/gem5/x86_system_files/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1583,7 +1583,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-bigswap2.img +image_file=/usr/local/google/home/gabeblack/gem5/x86_system_files/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr index 0a8bc6fbe..0aaa4f921 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr @@ -1,7 +1,7 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting terminal connections -warn: Reading current count from inactive timer. warn: Sockets disabled, not accepting gdb connections +warn: Reading current count from inactive timer. warn: Don't know what interrupt to clear for console. warn: x86 cpuid: unknown family 0x8086 warn: x86 cpuid: unknown family 0x8086 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index 3b996a550..91003600d 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 29 2014 09:18:07 -gem5 started Oct 29 2014 09:27:02 -gem5 executing on u200540-lin -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re /work/gem5.latest/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing +gem5 compiled Nov 16 2014 23:19:52 +gem5 started Nov 16 2014 23:20:03 +gem5 executing on gabeblackz620.mtv.corp.google.com +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re /usr/local/google/home/gabeblack/gem5/hg/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /usr/local/google/home/gabeblack/gem5/x86_system_files/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 5125902116500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 560862ac3..a6e63eaeb 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.125902 # Nu sim_ticks 5125902116500 # Number of ticks simulated final_tick 5125902116500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 182847 # Simulator instruction rate (inst/s) -host_op_rate 361437 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2297162464 # Simulator tick rate (ticks/s) -host_mem_usage 805240 # Number of bytes of host memory used -host_seconds 2231.41 # Real time elapsed on the host +host_inst_rate 225212 # Simulator instruction rate (inst/s) +host_op_rate 445179 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2829401321 # Simulator tick rate (ticks/s) +host_mem_usage 748772 # Number of bytes of host memory used +host_seconds 1811.66 # Real time elapsed on the host sim_insts 408006726 # Number of instructions simulated sim_ops 806511598 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini index 5c0ccd72f..d43104caf 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini @@ -20,7 +20,7 @@ eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/usr/local/google/home/gabeblack/gem5/x86_system_files/binaries/x86_64-vmlinux-2.6.22.9 kernel_addr_check=true load_addr_mask=18446744073709551615 load_offset=0 @@ -28,7 +28,7 @@ mem_mode=atomic mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/usr/local/google/home/gabeblack/gem5/hg/gem5/tests/halt.sh smbios_table=system.smbios_table symbolfile= work_begin_ckpt_count=0 @@ -1616,7 +1616,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-x86.img +image_file=/usr/local/google/home/gabeblack/gem5/x86_system_files/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1639,7 +1639,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-bigswap2.img +image_file=/usr/local/google/home/gabeblack/gem5/x86_system_files/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json index 3c9f7ff5e..3be878044 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json @@ -2,7 +2,7 @@ "name": null, "sim_quantum": 0, "system": { - "kernel": "/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9", + "kernel": "/usr/local/google/home/gabeblack/gem5/x86_system_files/binaries/x86_64-vmlinux-2.6.22.9", "l2c": { "is_top_level": false, "prefetcher": null, @@ -145,7 +145,7 @@ "type": "Bridge" }, "symbolfile": "", - "readfile": "/scratch/nilay/GEM5/gem5/tests/halt.sh", + "readfile": "/usr/local/google/home/gabeblack/gem5/hg/gem5/tests/halt.sh", "intel_mp_table": { "oem_table_addr": 0, "name": "intel_mp_table", @@ -1176,7 +1176,7 @@ "eventq_index": 0, "cxx_class": "RawDiskImage", "path": "system.pc.south_bridge.ide.disks0.image.child", - "image_file": "/scratch/nilay/GEM5/system/disks/linux-x86.img", + "image_file": "/usr/local/google/home/gabeblack/gem5/x86_system_files/disks/linux-x86.img", "type": "RawDiskImage" }, "path": "system.pc.south_bridge.ide.disks0.image", @@ -1204,7 +1204,7 @@ "eventq_index": 0, "cxx_class": "RawDiskImage", "path": "system.pc.south_bridge.ide.disks1.image.child", - "image_file": "/scratch/nilay/GEM5/system/disks/linux-bigswap2.img", + "image_file": "/usr/local/google/home/gabeblack/gem5/x86_system_files/disks/linux-bigswap2.img", "type": "RawDiskImage" }, "path": "system.pc.south_bridge.ide.disks1.image", @@ -1629,8 +1629,9 @@ "IDD3N": "0.057", "name": "physmem", "tXSDLL": 0, - "tXAW": 30000, + "device_size": 536870912, "dll": true, + "tXAW": 30000, "write_low_thresh_perc": 50, "range": "0:134217727", "VDD2": "0.0", diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr index b4d02041b..2cf33b630 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr @@ -1,7 +1,7 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting terminal connections -warn: Reading current count from inactive timer. warn: Sockets disabled, not accepting gdb connections +warn: Reading current count from inactive timer. warn: Don't know what interrupt to clear for console. warn: x86 cpuid: unknown family 0x8086 warn: x86 cpuid: unknown family 0x8086 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout index ca2891ded..498a02071 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 29 2014 09:18:07 -gem5 started Oct 29 2014 09:28:19 -gem5 executing on u200540-lin -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /work/gem5.latest/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full +gem5 compiled Nov 16 2014 23:19:52 +gem5 started Nov 16 2014 23:20:03 +gem5 executing on gabeblackz620.mtv.corp.google.com +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /usr/local/google/home/gabeblack/gem5/hg/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full Global frequency set at 1000000000000 ticks per second 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index 847df0bf1..4de64b96e 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -4,16 +4,15 @@ sim_seconds 5.137752 # Nu sim_ticks 5137751757500 # Number of ticks simulated final_tick 5137751757500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 311526 # Simulator instruction rate (inst/s) -host_op_rate 619354 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6572918502 # Simulator tick rate (ticks/s) -host_mem_usage 927072 # Number of bytes of host memory used -host_seconds 781.65 # Real time elapsed on the host +host_inst_rate 342085 # Simulator instruction rate (inst/s) +host_op_rate 680107 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7217672543 # Simulator tick rate (ticks/s) +host_mem_usage 932836 # Number of bytes of host memory used +host_seconds 711.83 # Real time elapsed on the host sim_insts 243506025 # Number of instructions simulated sim_ops 484120527 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 475328 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 5564736 # Number of bytes read from this memory @@ -23,6 +22,7 @@ system.physmem.bytes_read::cpu1.data 2113344 # Nu system.physmem.bytes_read::cpu2.dtb.walker 2688 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.inst 362880 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 2752000 # Number of bytes read from this memory +system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory system.physmem.bytes_read::total 11429696 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 475328 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 130048 # Number of instructions bytes read from this memory @@ -31,7 +31,6 @@ system.physmem.bytes_inst_read::total 968256 # Nu system.physmem.bytes_written::writebacks 6180416 # Number of bytes written to this memory system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory system.physmem.bytes_written::total 9170496 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.inst 7427 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 86949 # Number of read requests responded to by this memory @@ -41,11 +40,11 @@ system.physmem.num_reads::cpu1.data 33021 # Nu system.physmem.num_reads::cpu2.dtb.walker 42 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.inst 5670 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 43000 # Number of read requests responded to by this memory +system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory system.physmem.num_reads::total 178589 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 96569 # Number of write requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory system.physmem.num_writes::total 143289 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 5518 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.inst 92517 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.data 1083107 # Total read bandwidth from this memory (bytes/s) @@ -55,6 +54,7 @@ system.physmem.bw_read::cpu1.data 411336 # To system.physmem.bw_read::cpu2.dtb.walker 523 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.inst 70630 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.data 535643 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5518 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 2224649 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 92517 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 25312 # Instruction read bandwidth from this memory (bytes/s) @@ -64,7 +64,6 @@ system.physmem.bw_write::writebacks 1202942 # Wr system.physmem.bw_write::pc.south_bridge.ide 581982 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 1784924 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 1202942 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 587501 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 92517 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.data 1083107 # Total bandwidth to/from this memory (bytes/s) @@ -74,6 +73,7 @@ system.physmem.bw_total::cpu1.data 411336 # To system.physmem.bw_total::cpu2.dtb.walker 523 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.inst 70630 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.data 535643 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 587501 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 4009573 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 84209 # Number of read requests accepted system.physmem.writeReqs 74716 # Number of write requests accepted @@ -329,712 +329,7 @@ system.physmem.totalEnergy::0 3434046565050 # T system.physmem.totalEnergy::1 3434197896405 # Total energy per rank (pJ) system.physmem.averagePower::0 668.395092 # Core power per rank (mW) system.physmem.averagePower::1 668.424547 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 5119571 # Transaction distribution -system.membus.trans_dist::ReadResp 5119569 # Transaction distribution -system.membus.trans_dist::WriteReq 13900 # Transaction distribution -system.membus.trans_dist::WriteResp 13900 # Transaction distribution -system.membus.trans_dist::Writeback 96569 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1658 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1658 # Transaction distribution -system.membus.trans_dist::ReadExReq 130179 # Transaction distribution -system.membus.trans_dist::ReadExResp 130179 # Transaction distribution -system.membus.trans_dist::MessageReq 1687 # Transaction distribution -system.membus.trans_dist::MessageResp 1687 # Transaction distribution -system.membus.trans_dist::BadAddressError 2 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3374 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3374 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7129206 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3039990 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 456177 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 10625377 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94957 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 94957 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10723708 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6748 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6748 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3570760 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6079977 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17581760 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 27232497 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3029312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 3029312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 30268557 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 291 # Total snoops (count) -system.membus.snoop_fanout::samples 323999 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 323999 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 323999 # Request fanout histogram -system.membus.reqLayer0.occupancy 162958500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 314938500 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 2254000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 804193000 # Layer occupancy (ticks) -system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 2000 # Layer occupancy (ticks) -system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1127000 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1664243698 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 28678745 # Layer occupancy (ticks) -system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 104648 # number of replacements -system.l2c.tags.tagsinuse 64825.327064 # Cycle average of tags in use -system.l2c.tags.total_refs 3691316 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 168821 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.865266 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 51329.060133 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.131449 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1735.761730 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4946.132925 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.003182 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 379.214744 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1982.386911 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 11.162749 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 878.696468 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 3562.776774 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.783219 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.026486 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.075472 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.005786 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.030249 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000170 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.013408 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.054364 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.989156 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64173 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3770 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7642 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52446 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.979202 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 33857298 # Number of tag accesses -system.l2c.tags.data_accesses 33857298 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 21885 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 11413 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 321088 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 497388 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 12632 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6595 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 160077 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 224317 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 53710 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 12539 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 370609 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 592462 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2284715 # number of ReadReq hits -system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits -system.l2c.WriteReq_hits::total 2 # number of WriteReq hits -system.l2c.Writeback_hits::writebacks 1547592 # number of Writeback hits -system.l2c.Writeback_hits::total 1547592 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 126 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 49 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 89 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 264 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 63533 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 34910 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 62567 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 161010 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 21885 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 11415 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 321088 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 560921 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 12632 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6595 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 160077 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 259227 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 53710 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 12539 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 370609 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 655029 # number of demand (read+write) hits -system.l2c.demand_hits::total 2445727 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 21885 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 11415 # number of overall hits -system.l2c.overall_hits::cpu0.inst 321088 # number of overall hits -system.l2c.overall_hits::cpu0.data 560921 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 12632 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6595 # number of overall hits -system.l2c.overall_hits::cpu1.inst 160077 # number of overall hits -system.l2c.overall_hits::cpu1.data 259227 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 53710 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 12539 # number of overall hits -system.l2c.overall_hits::cpu2.inst 370609 # number of overall hits -system.l2c.overall_hits::cpu2.data 655029 # number of overall hits -system.l2c.overall_hits::total 2445727 # number of overall hits -system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7427 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 17501 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2032 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4808 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 42 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 5670 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 10484 # number of ReadReq misses -system.l2c.ReadReq_misses::total 47969 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 766 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 250 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 384 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1400 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 69535 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 28299 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 32603 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 130437 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7427 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 87036 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2032 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 33107 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 42 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 5670 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 43087 # number of demand (read+write) misses -system.l2c.demand_misses::total 178406 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7427 # number of overall misses -system.l2c.overall_misses::cpu0.data 87036 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2032 # number of overall misses -system.l2c.overall_misses::cpu1.data 33107 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 42 # number of overall misses -system.l2c.overall_misses::cpu2.inst 5670 # number of overall misses -system.l2c.overall_misses::cpu2.data 43087 # number of overall misses -system.l2c.overall_misses::total 178406 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 74500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 150329750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 367685500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 3647250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 442043250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 814497000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1778277250 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 2652136 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 4441809 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 7093945 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1942003664 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 2343046915 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 4285050579 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 74500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 150329750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 2309689164 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.dtb.walker 3647250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 442043250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 3157543915 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 6063327829 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 74500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 150329750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 2309689164 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 3647250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 442043250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 3157543915 # number of overall miss cycles -system.l2c.overall_miss_latency::total 6063327829 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 21885 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 11417 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 328515 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 514889 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 12632 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 6596 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 162109 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 229125 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 53752 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 12539 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 376279 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 602946 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2332684 # number of ReadReq accesses(hits+misses) -system.l2c.WriteReq_accesses::cpu0.itb.walker 2 # number of WriteReq accesses(hits+misses) -system.l2c.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1547592 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1547592 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 892 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 299 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 473 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1664 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 133068 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 63209 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 95170 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 291447 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 21885 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 11419 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 328515 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 647957 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 12632 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 6596 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 162109 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 292334 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.dtb.walker 53752 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.itb.walker 12539 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 376279 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 698116 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2624133 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 21885 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 11419 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 328515 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 647957 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 12632 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6596 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 162109 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 292334 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 53752 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 12539 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 376279 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 698116 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2624133 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000350 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.022608 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.033990 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000152 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.012535 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.020984 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000781 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.015069 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.017388 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.020564 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.858744 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.836120 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.811839 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.841346 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.522552 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.447705 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.342576 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.447550 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000350 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.022608 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.134324 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.000152 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.012535 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.113251 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000781 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.015069 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.061719 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.067987 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000350 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.022608 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.134324 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.000152 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.012535 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.113251 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000781 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.015069 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.061719 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.067987 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 74500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73981.176181 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 76473.689684 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 86839.285714 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 77961.772487 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 77689.526898 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 37071.384644 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 10608.544000 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 11567.210938 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 5067.103571 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68624.462490 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 71865.991320 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 32851.495964 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 73981.176181 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 69764.375026 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 86839.285714 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 77961.772487 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 73282.983615 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 33986.120585 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 73981.176181 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 69764.375026 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 86839.285714 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 77961.772487 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 73282.983615 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 33986.120585 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 96569 # number of writebacks -system.l2c.writebacks::total 96569 # number of writebacks -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 2032 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4808 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 42 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 5670 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 10484 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 23037 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 250 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 384 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 634 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 28299 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 32603 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 60902 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2032 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 33107 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.dtb.walker 42 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 5670 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 43087 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 83939 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2032 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 33107 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.dtb.walker 42 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 5670 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 43087 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 83939 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 124575250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 307568500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 3127250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 371081250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 683718500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1490133250 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 2500500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 3860881 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 6361381 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1578314336 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1925294585 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 3503608921 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 124575250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1885882836 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 3127250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 371081250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 2609013085 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 4993742171 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 62500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 124575250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1885882836 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 3127250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 371081250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 2609013085 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 4993742171 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 27997217000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30232738500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 58229955500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 537806500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 646167500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1183974000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28535023500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 30878906000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 59413929500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000152 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.012535 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.020984 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000781 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.015069 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.017388 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.009876 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.836120 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.811839 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.381010 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.447705 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.342576 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.208964 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000152 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.012535 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.113251 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000781 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.015069 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.061719 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.031987 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000152 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.012535 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.113251 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000781 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.015069 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.061719 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.031987 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61306.717520 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63970.153910 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 74458.333333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 65446.428571 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 65215.423502 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 64684.344750 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10054.377604 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10033.723975 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55772.795364 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 59052.681808 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 57528.634872 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61306.717520 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56963.265654 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 74458.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65446.428571 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 60552.210295 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 59492.514457 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61306.717520 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56963.265654 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 74458.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65446.428571 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 60552.210295 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 59492.514457 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 47569 # number of replacements -system.iocache.tags.tagsinuse 0.092434 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5000571333009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.092434 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005777 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.005777 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428616 # Number of tag accesses -system.iocache.tags.data_accesses 428616 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits -system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses -system.iocache.ReadReq_misses::total 904 # number of ReadReq misses -system.iocache.demand_misses::pc.south_bridge.ide 904 # number of demand (read+write) misses -system.iocache.demand_misses::total 904 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 904 # number of overall misses -system.iocache.overall_misses::total 904 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 131931527 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 131931527 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 131931527 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 131931527 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 131931527 # number of overall miss cycles -system.iocache.overall_miss_latency::total 131931527 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 904 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 904 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 904 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 904 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145941.954646 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 145941.954646 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 145941.954646 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 145941.954646 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 145941.954646 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 145941.954646 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 471 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.076923 # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 46720 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 734 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 734 # number of ReadReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 734 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 734 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 734 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 734 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 93740027 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 93740027 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 1329860248 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1329860248 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 93740027 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 93740027 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 93740027 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 93740027 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.811947 # mshr miss rate for ReadReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.811947 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.811947 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 127711.208447 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 127711.208447 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 127711.208447 # average overall mshr miss latency -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). -system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. -system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. -system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. -system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. -system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. -system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 7431790 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 7431262 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13902 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13902 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1547592 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 22056 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1664 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1664 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 291447 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 291447 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1733856 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 14997138 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 72735 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 201275 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17005004 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55482624 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213567857 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 271280 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 749120 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 270070881 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 66934 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4248687 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.011209 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.105278 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 4201063 98.88% 98.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 47624 1.12% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4248687 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 5247340592 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 936000 # Layer occupancy (ticks) -system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2425844552 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4872344858 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 24091410 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 80681637 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 3554542 # Transaction distribution -system.iobus.trans_dist::ReadResp 3554542 # Transaction distribution -system.iobus.trans_dist::WriteReq 57685 # Transaction distribution -system.iobus.trans_dist::WriteResp 33021 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 24664 # Transaction distribution -system.iobus.trans_dist::MessageReq 1687 # Transaction distribution -system.iobus.trans_dist::MessageResp 1687 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7085054 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1126 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27782 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 7129206 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95248 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95248 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3374 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3374 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 7227828 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3542527 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2252 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13891 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 3570760 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027776 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027776 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6748 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6748 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 6605284 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2693792 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 27000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 4846000 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 4000 # Layer occupancy (ticks) -system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks) -system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 25000 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) -system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 142528000 # Layer occupancy (ticks) -system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 333000 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 134000 # Layer occupancy (ticks) -system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 10264000 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 199614020 # Layer occupancy (ticks) -system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 1032000 # Layer occupancy (ticks) -system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 303080000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 27344255 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1127000 # Layer occupancy (ticks) -system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu0.numCycles 818767223 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started @@ -1098,143 +393,6 @@ system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Cl system.cpu0.op_class::total 146799291 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 866413 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.840210 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 130156159 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 866925 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 150.135432 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 149014386250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 138.994027 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 266.522548 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 105.323634 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.271473 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.520552 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.205710 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997735 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 295 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 131912504 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 131912504 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 87639896 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 39531787 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2984476 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 130156159 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 87639896 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 39531787 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2984476 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 130156159 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 87639896 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 39531787 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2984476 # number of overall hits -system.cpu0.icache.overall_hits::total 130156159 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 328528 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 162109 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 398768 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 889405 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 328528 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 162109 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 398768 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 889405 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 328528 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 162109 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 398768 # number of overall misses -system.cpu0.icache.overall_misses::total 889405 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2245844750 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5606326194 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 7852170944 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 2245844750 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 5606326194 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 7852170944 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 2245844750 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 5606326194 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 7852170944 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 87968424 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 39693896 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 3383244 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 131045564 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 87968424 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 39693896 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 3383244 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 131045564 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 87968424 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 39693896 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 3383244 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 131045564 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003735 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004084 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.117866 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.006787 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003735 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004084 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.117866 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.006787 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003735 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004084 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.117866 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.006787 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13853.917734 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14059.117567 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8828.566226 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13853.917734 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14059.117567 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8828.566226 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13853.917734 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14059.117567 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8828.566226 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4938 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 262 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.847328 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 22465 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 22465 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 22465 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 22465 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 22465 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 22465 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 162109 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 376303 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 538412 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 162109 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 376303 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 538412 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 162109 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 376303 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 538412 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1920905250 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4627637688 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 6548542938 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1920905250 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4627637688 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6548542938 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1920905250 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4627637688 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6548542938 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004084 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.111225 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004109 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004084 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.111225 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.004109 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004084 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.111225 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.004109 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11849.467025 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12297.636979 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12162.698710 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11849.467025 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12297.636979 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12162.698710 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11849.467025 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12297.636979 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12162.698710 # average overall mshr miss latency -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.tags.replacements 1637866 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.999423 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 19673585 # Total number of references to valid blocks. @@ -1460,6 +618,143 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.tags.replacements 866413 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.840210 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 130156159 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 866925 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 150.135432 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 149014386250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 138.994027 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 266.522548 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 105.323634 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.271473 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.520552 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.205710 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997735 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 295 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 131912504 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 131912504 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 87639896 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 39531787 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2984476 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 130156159 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 87639896 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 39531787 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2984476 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 130156159 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 87639896 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 39531787 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 2984476 # number of overall hits +system.cpu0.icache.overall_hits::total 130156159 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 328528 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 162109 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 398768 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 889405 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 328528 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 162109 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 398768 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 889405 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 328528 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 162109 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 398768 # number of overall misses +system.cpu0.icache.overall_misses::total 889405 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2245844750 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5606326194 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 7852170944 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 2245844750 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 5606326194 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 7852170944 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 2245844750 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 5606326194 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 7852170944 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 87968424 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 39693896 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 3383244 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 131045564 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 87968424 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 39693896 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 3383244 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 131045564 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 87968424 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 39693896 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 3383244 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 131045564 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003735 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004084 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.117866 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.006787 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003735 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004084 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.117866 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.006787 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003735 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004084 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.117866 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.006787 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13853.917734 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14059.117567 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8828.566226 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13853.917734 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14059.117567 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8828.566226 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13853.917734 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14059.117567 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8828.566226 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4938 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 262 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.847328 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 22465 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 22465 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 22465 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 22465 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 22465 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 22465 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 162109 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 376303 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 538412 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 162109 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 376303 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 538412 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 162109 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 376303 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 538412 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1920905250 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4627637688 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6548542938 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1920905250 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4627637688 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6548542938 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1920905250 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4627637688 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6548542938 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004084 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.111225 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004109 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004084 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.111225 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.004109 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004084 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.111225 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.004109 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11849.467025 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12297.636979 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12162.698710 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11849.467025 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12297.636979 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12162.698710 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11849.467025 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12297.636979 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12162.698710 # average overall mshr miss latency +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.numCycles 2606022983 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -1830,6 +1125,711 @@ system.cpu2.cc_regfile_reads 138904210 # nu system.cpu2.cc_regfile_writes 106846664 # number of cc regfile writes system.cpu2.misc_regfile_reads 88678814 # number of misc regfile reads system.cpu2.misc_regfile_writes 129757 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 3554542 # Transaction distribution +system.iobus.trans_dist::ReadResp 3554542 # Transaction distribution +system.iobus.trans_dist::WriteReq 57685 # Transaction distribution +system.iobus.trans_dist::WriteResp 33021 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 24664 # Transaction distribution +system.iobus.trans_dist::MessageReq 1687 # Transaction distribution +system.iobus.trans_dist::MessageResp 1687 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7085054 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1126 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27782 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 7129206 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95248 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95248 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3374 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3374 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 7227828 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3542527 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2252 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13891 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 3570760 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027776 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027776 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6748 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6748 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 6605284 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2693792 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 27000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 4846000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 4000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 25000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) +system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer9.occupancy 142528000 # Layer occupancy (ticks) +system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 333000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer11.occupancy 134000 # Layer occupancy (ticks) +system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 10264000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 199614020 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 1032000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 303080000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer1.occupancy 27344255 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer2.occupancy 1127000 # Layer occupancy (ticks) +system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) +system.iocache.tags.replacements 47569 # number of replacements +system.iocache.tags.tagsinuse 0.092434 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 5000571333009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.092434 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005777 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005777 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 428616 # Number of tag accesses +system.iocache.tags.data_accesses 428616 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits +system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses +system.iocache.ReadReq_misses::total 904 # number of ReadReq misses +system.iocache.demand_misses::pc.south_bridge.ide 904 # number of demand (read+write) misses +system.iocache.demand_misses::total 904 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 904 # number of overall misses +system.iocache.overall_misses::total 904 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 131931527 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 131931527 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 131931527 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 131931527 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 131931527 # number of overall miss cycles +system.iocache.overall_miss_latency::total 131931527 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::pc.south_bridge.ide 904 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 904 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 904 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 904 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145941.954646 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 145941.954646 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 145941.954646 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 145941.954646 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 145941.954646 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 145941.954646 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 471 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.076923 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 46720 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 734 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 734 # number of ReadReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 734 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 734 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 734 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 734 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 93740027 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 93740027 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 1329860248 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1329860248 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 93740027 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 93740027 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 93740027 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 93740027 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.811947 # mshr miss rate for ReadReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.811947 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.811947 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 127711.208447 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 127711.208447 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 127711.208447 # average overall mshr miss latency +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.tags.replacements 104648 # number of replacements +system.l2c.tags.tagsinuse 64825.327064 # Cycle average of tags in use +system.l2c.tags.total_refs 3691316 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168821 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.865266 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 51329.060133 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.131449 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1735.761730 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4946.132925 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.003182 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 379.214744 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1982.386911 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 11.162749 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 878.696468 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 3562.776774 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.783219 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.026486 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.075472 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.005786 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.030249 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000170 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.013408 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.054364 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.989156 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 64173 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3770 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7642 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52446 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.979202 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 33857298 # Number of tag accesses +system.l2c.tags.data_accesses 33857298 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 21885 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 11413 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 321088 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 497388 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 12632 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6595 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 160077 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 224317 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 53710 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 12539 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 370609 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 592462 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2284715 # number of ReadReq hits +system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits +system.l2c.WriteReq_hits::total 2 # number of WriteReq hits +system.l2c.Writeback_hits::writebacks 1547592 # number of Writeback hits +system.l2c.Writeback_hits::total 1547592 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 126 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 49 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 89 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 264 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 63533 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 34910 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 62567 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 161010 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 21885 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 11415 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 321088 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 560921 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 12632 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 6595 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 160077 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 259227 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 53710 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 12539 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 370609 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 655029 # number of demand (read+write) hits +system.l2c.demand_hits::total 2445727 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 21885 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 11415 # number of overall hits +system.l2c.overall_hits::cpu0.inst 321088 # number of overall hits +system.l2c.overall_hits::cpu0.data 560921 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 12632 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 6595 # number of overall hits +system.l2c.overall_hits::cpu1.inst 160077 # number of overall hits +system.l2c.overall_hits::cpu1.data 259227 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 53710 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 12539 # number of overall hits +system.l2c.overall_hits::cpu2.inst 370609 # number of overall hits +system.l2c.overall_hits::cpu2.data 655029 # number of overall hits +system.l2c.overall_hits::total 2445727 # number of overall hits +system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 7427 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 17501 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 2032 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4808 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 42 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 5670 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 10484 # number of ReadReq misses +system.l2c.ReadReq_misses::total 47969 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 766 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 250 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 384 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1400 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 69535 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 28299 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 32603 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 130437 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 7427 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 87036 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2032 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 33107 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.dtb.walker 42 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 5670 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 43087 # number of demand (read+write) misses +system.l2c.demand_misses::total 178406 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses +system.l2c.overall_misses::cpu0.inst 7427 # number of overall misses +system.l2c.overall_misses::cpu0.data 87036 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2032 # number of overall misses +system.l2c.overall_misses::cpu1.data 33107 # number of overall misses +system.l2c.overall_misses::cpu2.dtb.walker 42 # number of overall misses +system.l2c.overall_misses::cpu2.inst 5670 # number of overall misses +system.l2c.overall_misses::cpu2.data 43087 # number of overall misses +system.l2c.overall_misses::total 178406 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 74500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 150329750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 367685500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 3647250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 442043250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 814497000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1778277250 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 2652136 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 4441809 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 7093945 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1942003664 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 2343046915 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 4285050579 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 74500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 150329750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 2309689164 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.dtb.walker 3647250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 442043250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 3157543915 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 6063327829 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 74500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 150329750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 2309689164 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.dtb.walker 3647250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 442043250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 3157543915 # number of overall miss cycles +system.l2c.overall_miss_latency::total 6063327829 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 21885 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 11417 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 328515 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 514889 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 12632 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 6596 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 162109 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 229125 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 53752 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 12539 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 376279 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 602946 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2332684 # number of ReadReq accesses(hits+misses) +system.l2c.WriteReq_accesses::cpu0.itb.walker 2 # number of WriteReq accesses(hits+misses) +system.l2c.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 1547592 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1547592 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 892 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 299 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 473 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1664 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 133068 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 63209 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 95170 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 291447 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 21885 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 11419 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 328515 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 647957 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 12632 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 6596 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 162109 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 292334 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 53752 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 12539 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 376279 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 698116 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2624133 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 21885 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 11419 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 328515 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 647957 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 12632 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 6596 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 162109 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 292334 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 53752 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 12539 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 376279 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 698116 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2624133 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000350 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.022608 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.033990 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000152 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.012535 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.020984 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000781 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.015069 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.017388 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.020564 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.858744 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.836120 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.811839 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.841346 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.522552 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.447705 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.342576 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.447550 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000350 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.022608 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.134324 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.000152 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.012535 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.113251 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000781 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.015069 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.061719 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.067987 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000350 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.022608 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.134324 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.000152 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.012535 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.113251 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000781 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.015069 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.061719 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.067987 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 74500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73981.176181 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 76473.689684 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 86839.285714 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 77961.772487 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 77689.526898 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 37071.384644 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 10608.544000 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 11567.210938 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 5067.103571 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68624.462490 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 71865.991320 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 32851.495964 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 73981.176181 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 69764.375026 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 86839.285714 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 77961.772487 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 73282.983615 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 33986.120585 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 73981.176181 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 69764.375026 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 86839.285714 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 77961.772487 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 73282.983615 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 33986.120585 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.writebacks::writebacks 96569 # number of writebacks +system.l2c.writebacks::total 96569 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 2032 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 4808 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 42 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 5670 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 10484 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 23037 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 250 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 384 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 634 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 28299 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 32603 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 60902 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2032 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 33107 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 42 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 5670 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 43087 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 83939 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2032 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 33107 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 42 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 5670 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 43087 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 83939 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 62500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 124575250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 307568500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 3127250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 371081250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 683718500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1490133250 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 2500500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 3860881 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 6361381 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1578314336 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1925294585 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 3503608921 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 62500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 124575250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1885882836 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 3127250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 371081250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 2609013085 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 4993742171 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 62500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 124575250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1885882836 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 3127250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 371081250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 2609013085 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 4993742171 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 27997217000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30232738500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 58229955500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 537806500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 646167500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1183974000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28535023500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 30878906000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 59413929500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000152 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.012535 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.020984 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000781 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.015069 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.017388 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.009876 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.836120 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.811839 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.381010 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.447705 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.342576 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.208964 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000152 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.012535 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.113251 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000781 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.015069 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.061719 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.031987 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000152 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.012535 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.113251 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000781 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.015069 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.061719 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.031987 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61306.717520 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63970.153910 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 74458.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 65446.428571 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 65215.423502 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 64684.344750 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10054.377604 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10033.723975 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55772.795364 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 59052.681808 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 57528.634872 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61306.717520 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56963.265654 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 74458.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65446.428571 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 60552.210295 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59492.514457 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61306.717520 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56963.265654 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 74458.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65446.428571 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 60552.210295 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59492.514457 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 5119571 # Transaction distribution +system.membus.trans_dist::ReadResp 5119569 # Transaction distribution +system.membus.trans_dist::WriteReq 13900 # Transaction distribution +system.membus.trans_dist::WriteResp 13900 # Transaction distribution +system.membus.trans_dist::Writeback 96569 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1658 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1658 # Transaction distribution +system.membus.trans_dist::ReadExReq 130179 # Transaction distribution +system.membus.trans_dist::ReadExResp 130179 # Transaction distribution +system.membus.trans_dist::MessageReq 1687 # Transaction distribution +system.membus.trans_dist::MessageResp 1687 # Transaction distribution +system.membus.trans_dist::BadAddressError 2 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3374 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3374 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7129206 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3039990 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 456177 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 10625377 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94957 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 94957 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10723708 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6748 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6748 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3570760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6079977 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17581760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 27232497 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3029312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 3029312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 30268557 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 291 # Total snoops (count) +system.membus.snoop_fanout::samples 323999 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 323999 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 323999 # Request fanout histogram +system.membus.reqLayer0.occupancy 162958500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 314938500 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 2254000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer3.occupancy 804193000 # Layer occupancy (ticks) +system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer4.occupancy 2000 # Layer occupancy (ticks) +system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.membus.respLayer0.occupancy 1127000 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 1664243698 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer4.occupancy 28678745 # Layer occupancy (ticks) +system.membus.respLayer4.utilization 0.0 # Layer utilization (%) +system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. +system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. +system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. +system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. +system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. +system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. +system.toL2Bus.trans_dist::ReadReq 7431790 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 7431262 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13902 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13902 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 1547592 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 22056 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1664 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1664 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 291447 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 291447 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1733856 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 14997138 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 72735 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 201275 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17005004 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55482624 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213567857 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 271280 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 749120 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 270070881 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 66934 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4248687 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.011209 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.105278 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 4201063 98.88% 98.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 47624 1.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 4248687 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 5247340592 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 936000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 2425844552 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 4872344858 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 24091410 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 80681637 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini index 9627624a2..e4451124c 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini @@ -20,7 +20,7 @@ eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/usr/local/google/home/gabeblack/gem5/x86_system_files/binaries/x86_64-vmlinux-2.6.22.9 kernel_addr_check=true load_addr_mask=18446744073709551615 load_offset=0 @@ -28,7 +28,7 @@ mem_mode=atomic mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +readfile=/usr/local/google/home/gabeblack/gem5/hg/gem5/tests/halt.sh smbios_table=system.smbios_table symbolfile= work_begin_ckpt_count=0 @@ -1184,7 +1184,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img +image_file=/usr/local/google/home/gabeblack/gem5/x86_system_files/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1207,7 +1207,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/usr/local/google/home/gabeblack/gem5/x86_system_files/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr index bb1874a4f..49ecbe6ac 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr @@ -1,6 +1,6 @@ warn: Sockets disabled, not accepting terminal connections -warn: Reading current count from inactive timer. warn: Sockets disabled, not accepting gdb connections +warn: Reading current count from inactive timer. warn: Don't know what interrupt to clear for console. warn: x86 cpuid: unknown family 0x8086 warn: Tried to clear PCI interrupt 14 diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout index 04f5d2889..b2d8b456f 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:10:34 -gem5 started Jan 22 2014 17:30:13 -gem5 executing on u200540-lin -command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic +gem5 compiled Nov 16 2014 23:19:52 +gem5 started Nov 16 2014 23:20:03 +gem5 executing on gabeblackz620.mtv.corp.google.com +command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re /usr/local/google/home/gabeblack/gem5/hg/gem5/tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /usr/local/google/home/gabeblack/gem5/x86_system_files/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5112126264500 because m5_exit instruction encountered +Exiting @ tick 5112155173500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 52d540f15..1c8458cfb 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,40 +4,40 @@ sim_seconds 5.112155 # Nu sim_ticks 5112155173500 # Number of ticks simulated final_tick 5112155173500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1096092 # Simulator instruction rate (inst/s) -host_op_rate 2244090 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28012193632 # Simulator tick rate (ticks/s) -host_mem_usage 637772 # Number of bytes of host memory used -host_seconds 182.50 # Real time elapsed on the host +host_inst_rate 1971048 # Simulator instruction rate (inst/s) +host_op_rate 4035436 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50372945560 # Simulator tick rate (ticks/s) +host_mem_usage 594916 # Number of bytes of host memory used +host_seconds 101.49 # Real time elapsed on the host sim_insts 200033988 # Number of instructions simulated sim_ops 409540726 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 852288 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10678208 # Number of bytes read from this memory +system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory system.physmem.bytes_read::total 11559232 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 852288 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 852288 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 6294336 # Number of bytes written to this memory system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory system.physmem.bytes_written::total 9284416 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 13317 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 166847 # Number of read requests responded to by this memory +system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory system.physmem.num_reads::total 180613 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 98349 # Number of write requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory system.physmem.num_writes::total 145069 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 5546 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 166718 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 2088788 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5546 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 2261127 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 166718 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 166718 # Instruction read bandwidth from this memory (bytes/s) @@ -45,167 +45,12 @@ system.physmem.bw_write::writebacks 1231249 # Wr system.physmem.bw_write::pc.south_bridge.ide 584896 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 1816145 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 1231249 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 590442 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 166718 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2088788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 590442 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 4077272 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 13903768 # Transaction distribution -system.membus.trans_dist::ReadResp 13903768 # Transaction distribution -system.membus.trans_dist::WriteReq 13911 # Transaction distribution -system.membus.trans_dist::WriteResp 13911 # Transaction distribution -system.membus.trans_dist::Writeback 98349 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2525 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2096 # Transaction distribution -system.membus.trans_dist::ReadExReq 134620 # Transaction distribution -system.membus.trans_dist::ReadExResp 134615 # Transaction distribution -system.membus.trans_dist::MessageReq 1696 # Transaction distribution -system.membus.trans_dist::MessageResp 1696 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3392 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044188 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 463315 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28205747 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95256 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 95256 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28304395 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028212 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 15396485 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17825216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43249913 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3048192 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 3048192 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 46304889 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 328677 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 328677 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 328677 # Request fanout histogram -system.iocache.tags.replacements 47573 # number of replacements -system.iocache.tags.tagsinuse 0.042448 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47589 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4994875221009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042448 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428652 # Number of tag accesses -system.iocache.tags.data_accesses 428652 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits -system.iocache.ReadReq_misses::pc.south_bridge.ide 908 # number of ReadReq misses -system.iocache.ReadReq_misses::total 908 # number of ReadReq misses -system.iocache.demand_misses::pc.south_bridge.ide 908 # number of demand (read+write) misses -system.iocache.demand_misses::total 908 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 908 # number of overall misses -system.iocache.overall_misses::total 908 # number of overall misses -system.iocache.ReadReq_accesses::pc.south_bridge.ide 908 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 908 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 908 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 908 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 908 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 46720 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). -system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. -system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. -system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. -system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. -system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. -system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 10012030 # Transaction distribution -system.iobus.trans_dist::ReadResp 10012030 # Transaction distribution -system.iobus.trans_dist::WriteReq 57692 # Transaction distribution -system.iobus.trans_dist::WriteResp 10972 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.iobus.trans_dist::MessageReq 1696 # Transaction distribution -system.iobus.trans_dist::MessageResp 1696 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 19999988 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1098 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27812 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 20044188 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95256 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95256 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3392 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3392 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 20142836 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 9999994 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2196 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13906 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 10028212 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027808 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027808 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6784 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6784 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 13062804 # Cumulative packet size per connected master and slave (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.numCycles 10224314318 # number of cpu cycles simulated @@ -270,6 +115,124 @@ system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class::total 409541761 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu.dcache.tags.replacements 1623441 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.999462 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20193263 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1623953 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.434635 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.999462 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 233 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 88892882 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88892882 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 12028464 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12028464 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8103633 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8103633 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 58902 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 58902 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 20132097 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20132097 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20190999 # number of overall hits +system.cpu.dcache.overall_hits::total 20190999 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 905998 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 905998 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 317173 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 317173 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 403059 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 403059 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1223171 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1223171 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1626230 # number of overall misses +system.cpu.dcache.overall_misses::total 1626230 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 12934462 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12934462 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8420806 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8420806 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 461961 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 461961 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21355268 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21355268 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21817229 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21817229 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070045 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.070045 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037665 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037665 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872496 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.872496 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.057277 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.057277 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074539 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074539 # miss rate for overall accesses +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 1536849 # number of writebacks +system.cpu.dcache.writebacks::total 1536849 # number of writebacks +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dtb_walker_cache.tags.replacements 8174 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.013947 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 12516 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 8188 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.528578 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5101311942500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.013947 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313372 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313372 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 53153 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 53153 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12517 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 12517 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12517 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 12517 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12517 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 12517 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9373 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 9373 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9373 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 9373 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9373 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 9373 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21890 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 21890 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21890 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21890 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21890 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21890 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.428186 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.428186 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.428186 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.428186 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.428186 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.428186 # miss rate for overall accesses +system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed +system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed +system.cpu.dtb_walker_cache.writebacks::writebacks 2794 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2794 # number of writebacks +system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 791952 # number of replacements system.cpu.icache.tags.tagsinuse 510.663108 # Cycle average of tags in use system.cpu.icache.tags.total_refs 243645979 # Total number of references to valid blocks. @@ -376,157 +339,6 @@ system.cpu.itb_walker_cache.cache_copies 0 # nu system.cpu.itb_walker_cache.writebacks::writebacks 802 # number of writebacks system.cpu.itb_walker_cache.writebacks::total 802 # number of writebacks system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 8174 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.013947 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 12516 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 8188 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.528578 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5101311942500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.013947 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313372 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313372 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 53153 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 53153 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12517 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 12517 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12517 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 12517 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12517 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 12517 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9373 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 9373 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9373 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 9373 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9373 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 9373 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21890 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 21890 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21890 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 21890 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21890 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 21890 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.428186 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.428186 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.428186 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.428186 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.428186 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.428186 # miss rate for overall accesses -system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed -system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2794 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2794 # number of writebacks -system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1623441 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.999462 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20193263 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1623953 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.434635 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.999462 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 233 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88892882 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88892882 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 12028464 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12028464 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8103633 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8103633 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 58902 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 58902 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 20132097 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20132097 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20190999 # number of overall hits -system.cpu.dcache.overall_hits::total 20190999 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 905998 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 905998 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 317173 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 317173 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 403059 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 403059 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1223171 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1223171 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1626230 # number of overall misses -system.cpu.dcache.overall_misses::total 1626230 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 12934462 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12934462 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8420806 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8420806 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 461961 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 461961 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21355268 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21355268 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21817229 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21817229 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070045 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.070045 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037665 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037665 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872496 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.872496 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.057277 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.057277 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074539 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074539 # miss rate for overall accesses -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1536849 # number of writebacks -system.cpu.dcache.writebacks::total 1536849 # number of writebacks -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 15972786 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 15972786 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13911 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13911 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1540445 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2264 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2264 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 314909 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 314909 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1584942 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32531741 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9962 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 21540 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 34148185 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50718144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227716857 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 344448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 778688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 279558137 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 48008 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4020727 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.011846 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.108191 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 3973099 98.82% 98.82% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 47628 1.18% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4020727 # Request fanout histogram system.cpu.l2cache.tags.replacements 106197 # number of replacements system.cpu.l2cache.tags.tagsinuse 64825.457913 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3461872 # Total number of references to valid blocks. @@ -644,5 +456,193 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 98349 # number of writebacks system.cpu.l2cache.writebacks::total 98349 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 15972786 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 15972786 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13911 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13911 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1540445 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2264 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2264 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 314909 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 314909 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1584942 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32531741 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9962 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 21540 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 34148185 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50718144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227716857 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 344448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 778688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 279558137 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 48008 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4020727 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.011846 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.108191 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 3973099 98.82% 98.82% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 47628 1.18% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4020727 # Request fanout histogram +system.iobus.trans_dist::ReadReq 10012030 # Transaction distribution +system.iobus.trans_dist::ReadResp 10012030 # Transaction distribution +system.iobus.trans_dist::WriteReq 57692 # Transaction distribution +system.iobus.trans_dist::WriteResp 10972 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution +system.iobus.trans_dist::MessageReq 1696 # Transaction distribution +system.iobus.trans_dist::MessageResp 1696 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 19999988 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1098 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27812 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 20044188 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95256 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95256 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3392 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3392 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 20142836 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 9999994 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2196 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13906 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 10028212 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027808 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027808 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6784 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6784 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 13062804 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.replacements 47573 # number of replacements +system.iocache.tags.tagsinuse 0.042448 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 47589 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 4994875221009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042448 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 428652 # Number of tag accesses +system.iocache.tags.data_accesses 428652 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits +system.iocache.ReadReq_misses::pc.south_bridge.ide 908 # number of ReadReq misses +system.iocache.ReadReq_misses::total 908 # number of ReadReq misses +system.iocache.demand_misses::pc.south_bridge.ide 908 # number of demand (read+write) misses +system.iocache.demand_misses::total 908 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 908 # number of overall misses +system.iocache.overall_misses::total 908 # number of overall misses +system.iocache.ReadReq_accesses::pc.south_bridge.ide 908 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::pc.south_bridge.ide 908 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 908 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 908 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 908 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 46720 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 13903768 # Transaction distribution +system.membus.trans_dist::ReadResp 13903768 # Transaction distribution +system.membus.trans_dist::WriteReq 13911 # Transaction distribution +system.membus.trans_dist::WriteResp 13911 # Transaction distribution +system.membus.trans_dist::Writeback 98349 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2525 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2096 # Transaction distribution +system.membus.trans_dist::ReadExReq 134620 # Transaction distribution +system.membus.trans_dist::ReadExResp 134615 # Transaction distribution +system.membus.trans_dist::MessageReq 1696 # Transaction distribution +system.membus.trans_dist::MessageResp 1696 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3392 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044188 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 463315 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28205747 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95256 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 95256 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28304395 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028212 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 15396485 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17825216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43249913 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3048192 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 3048192 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 46304889 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 328677 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 328677 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 328677 # Request fanout histogram +system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. +system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. +system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. +system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. +system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. +system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini index b395adf7f..ccaf4ac7e 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini @@ -20,7 +20,7 @@ eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/usr/local/google/home/gabeblack/gem5/x86_system_files/binaries/x86_64-vmlinux-2.6.22.9 kernel_addr_check=true load_addr_mask=18446744073709551615 load_offset=0 @@ -28,7 +28,7 @@ mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/usr/local/google/home/gabeblack/gem5/hg/gem5/tests/halt.sh smbios_table=system.smbios_table symbolfile= work_begin_ckpt_count=0 @@ -1180,7 +1180,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-x86.img +image_file=/usr/local/google/home/gabeblack/gem5/x86_system_files/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1203,7 +1203,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-bigswap2.img +image_file=/usr/local/google/home/gabeblack/gem5/x86_system_files/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr index f30c0bc17..231efd798 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr @@ -1,7 +1,7 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting terminal connections -warn: Reading current count from inactive timer. warn: Sockets disabled, not accepting gdb connections +warn: Reading current count from inactive timer. warn: Don't know what interrupt to clear for console. warn: x86 cpuid: unknown family 0x8086 warn: Tried to clear PCI interrupt 14 diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout index a4565b1b8..f0d75ee6e 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 29 2014 09:18:07 -gem5 started Oct 29 2014 09:26:24 -gem5 executing on u200540-lin -command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re /work/gem5.latest/tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing +gem5 compiled Nov 16 2014 23:19:52 +gem5 started Nov 16 2014 23:20:03 +gem5 executing on gabeblackz620.mtv.corp.google.com +command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re /usr/local/google/home/gabeblack/gem5/hg/gem5/tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /usr/local/google/home/gabeblack/gem5/x86_system_files/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 5194410635000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 8675b3331..83f38fa06 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -4,40 +4,40 @@ sim_seconds 5.194411 # Nu sim_ticks 5194410635000 # Number of ticks simulated final_tick 5194410635000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1079720 # Simulator instruction rate (inst/s) -host_op_rate 2081347 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43672253601 # Simulator tick rate (ticks/s) -host_mem_usage 589096 # Number of bytes of host memory used -host_seconds 118.94 # Real time elapsed on the host +host_inst_rate 1282120 # Simulator instruction rate (inst/s) +host_op_rate 2471507 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51858853246 # Simulator tick rate (ticks/s) +host_mem_usage 594916 # Number of bytes of host memory used +host_seconds 100.16 # Real time elapsed on the host sim_insts 128422722 # Number of instructions simulated sim_ops 247557000 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 829440 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9099264 # Number of bytes read from this memory +system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory system.physmem.bytes_read::total 9957440 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 829440 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 829440 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 5149824 # Number of bytes written to this memory system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory system.physmem.bytes_written::total 8139904 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 12960 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 142176 # Number of read requests responded to by this memory +system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory system.physmem.num_reads::total 155585 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 80466 # Number of write requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory system.physmem.num_writes::total 127186 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 5458 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 159679 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 1751741 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5458 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 1916953 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 159679 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 159679 # Instruction read bandwidth from this memory (bytes/s) @@ -45,11 +45,11 @@ system.physmem.bw_write::writebacks 991416 # Wr system.physmem.bw_write::pc.south_bridge.ide 575634 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 1567051 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 991416 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 581092 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 159679 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1751741 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 581092 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 3484003 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 155585 # Number of read requests accepted system.physmem.writeReqs 127186 # Number of write requests accepted @@ -305,265 +305,6 @@ system.physmem.totalEnergy::0 3473770745370 # T system.physmem.totalEnergy::1 3473748494505 # Total energy per rank (pJ) system.physmem.averagePower::0 668.751736 # Core power per rank (mW) system.physmem.averagePower::1 668.747452 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 624009 # Transaction distribution -system.membus.trans_dist::ReadResp 624009 # Transaction distribution -system.membus.trans_dist::WriteReq 13889 # Transaction distribution -system.membus.trans_dist::WriteResp 13889 # Transaction distribution -system.membus.trans_dist::Writeback 80466 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2168 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1629 # Transaction distribution -system.membus.trans_dist::ReadExReq 113541 # Transaction distribution -system.membus.trans_dist::ReadExResp 113541 # Transaction distribution -system.membus.trans_dist::MessageReq 1655 # Transaction distribution -system.membus.trans_dist::MessageResp 1655 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3310 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3310 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480788 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710112 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394547 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1585447 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94730 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 94730 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1683487 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6620 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246674 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420221 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15078912 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16745807 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19770859 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 943 # Total snoops (count) -system.membus.snoop_fanout::samples 285344 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 285344 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 285344 # Request fanout histogram -system.membus.reqLayer0.occupancy 257196000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 358105500 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3310000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1311782500 # Layer occupancy (ticks) -system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1655000 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2622169871 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 54356499 # Layer occupancy (ticks) -system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47512 # number of replacements -system.iocache.tags.tagsinuse 0.118180 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47528 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5045851318000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.118180 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007386 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.007386 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428111 # Number of tag accesses -system.iocache.tags.data_accesses 428111 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits -system.iocache.ReadReq_misses::pc.south_bridge.ide 847 # number of ReadReq misses -system.iocache.ReadReq_misses::total 847 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 1 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 1 # number of WriteInvalidateReq misses -system.iocache.demand_misses::pc.south_bridge.ide 847 # number of demand (read+write) misses -system.iocache.demand_misses::total 847 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 847 # number of overall misses -system.iocache.overall_misses::total 847 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 141540186 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 141540186 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 141540186 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 141540186 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 141540186 # number of overall miss cycles -system.iocache.overall_miss_latency::total 141540186 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 847 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 847 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46721 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 46721 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 847 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 847 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 847 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 847 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 0.000021 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.000021 # miss rate for WriteInvalidateReq accesses -system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 167107.657615 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 167107.657615 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 167107.657615 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 471 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.076923 # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 46720 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 847 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 847 # number of ReadReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 847 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 847 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 847 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 847 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 97471186 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2827609160 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2827609160 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 97471186 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 97471186 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 115078.141677 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 115078.141677 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 115078.141677 # average overall mshr miss latency -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). -system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. -system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. -system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. -system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. -system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. -system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 230267 # Transaction distribution -system.iobus.trans_dist::ReadResp 230267 # Transaction distribution -system.iobus.trans_dist::WriteReq 57693 # Transaction distribution -system.iobus.trans_dist::WriteResp 57694 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 1 # Transaction distribution -system.iobus.trans_dist::MessageReq 1655 # Transaction distribution -system.iobus.trans_dist::MessageResp 1655 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27696 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 480788 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95134 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95134 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3310 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 579232 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13848 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 246674 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6620 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3280614 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3947664 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8813000 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) -system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) -system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 77000 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) -system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 218343000 # Layer occupancy (ticks) -system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) -system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) -system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 20719000 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 421906845 # Layer occupancy (ticks) -system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) -system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 469814000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 52234501 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1655000 # Layer occupancy (ticks) -system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.numCycles 10388821270 # number of cpu cycles simulated @@ -628,6 +369,237 @@ system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class::total 247558577 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu.dcache.tags.replacements 1622351 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.996907 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20038370 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1622863 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.347543 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.996907 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 88306374 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88306374 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 11941774 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11941774 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8035174 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8035174 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 59224 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 59224 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 19976948 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19976948 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20036172 # number of overall hits +system.cpu.dcache.overall_hits::total 20036172 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 907115 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 907115 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 325077 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 325077 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 402500 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 402500 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1232192 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1232192 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1634692 # number of overall misses +system.cpu.dcache.overall_misses::total 1634692 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12725992750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12725992750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11362158354 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11362158354 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24088151104 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24088151104 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24088151104 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24088151104 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 12848889 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12848889 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8360251 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8360251 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 461724 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 461724 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21209140 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21209140 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21670864 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21670864 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070599 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.070599 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038884 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.038884 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871733 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.871733 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.058097 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.058097 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.075433 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.075433 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14029.084240 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14029.084240 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34952.206259 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34952.206259 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19549.024100 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19549.024100 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14735.590010 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14735.590010 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 7616 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 81 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 94.024691 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 1538923 # number of writebacks +system.cpu.dcache.writebacks::total 1538923 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 288 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 288 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9252 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9252 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 9540 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 9540 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 9540 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 9540 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906827 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 906827 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315825 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 315825 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402464 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 402464 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1222652 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1222652 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1625116 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1625116 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10904887500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10904887500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10229869846 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10229869846 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5337291000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5337291000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21134757346 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21134757346 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26472048346 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26472048346 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94240373000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94240373000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2561690500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2561690500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96802063500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96802063500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070576 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070576 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037777 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037777 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871655 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871655 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057647 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057647 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074991 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074991 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12025.322912 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12025.322912 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32390.943864 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32390.943864 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13261.536436 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13261.536436 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17285.995807 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17285.995807 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16289.328482 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16289.328482 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dtb_walker_cache.tags.replacements 7576 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.056356 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 13259 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 7591 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.746674 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5163552885000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.056356 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.316022 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.316022 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 52917 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 52917 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13260 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13260 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13260 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13260 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13260 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13260 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8799 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8799 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8799 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8799 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8799 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8799 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 94478000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 94478000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 94478000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 94478000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 94478000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 94478000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22059 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 22059 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22059 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 22059 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22059 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 22059 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.398885 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.398885 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.398885 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.398885 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.398885 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.398885 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10737.356518 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10737.356518 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10737.356518 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10737.356518 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10737.356518 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10737.356518 # average overall miss latency +system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed +system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed +system.cpu.dtb_walker_cache.writebacks::writebacks 3010 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 3010 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8799 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8799 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8799 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 8799 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8799 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 8799 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 76879500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 76879500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 76879500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 76879500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 76879500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 76879500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.398885 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.398885 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.398885 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8737.299693 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8737.299693 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8737.299693 # average overall mshr miss latency +system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 791372 # number of replacements system.cpu.icache.tags.tagsinuse 510.348934 # Cycle average of tags in use system.cpu.icache.tags.total_refs 144679417 # Total number of references to valid blocks. @@ -806,283 +778,6 @@ system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8275.416396 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8275.416396 # average overall mshr miss latency system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8275.416396 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 7576 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.056356 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 13259 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 7591 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.746674 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5163552885000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.056356 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.316022 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.316022 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 52917 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 52917 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13260 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13260 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13260 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13260 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13260 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13260 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8799 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8799 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8799 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8799 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8799 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8799 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 94478000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 94478000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 94478000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 94478000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 94478000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 94478000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22059 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 22059 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22059 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 22059 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22059 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 22059 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.398885 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.398885 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.398885 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.398885 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.398885 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.398885 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10737.356518 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10737.356518 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10737.356518 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10737.356518 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10737.356518 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10737.356518 # average overall miss latency -system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed -system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 3010 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 3010 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8799 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8799 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8799 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 8799 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8799 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 8799 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 76879500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 76879500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 76879500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 76879500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 76879500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 76879500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.398885 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.398885 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.398885 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8737.299693 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8737.299693 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8737.299693 # average overall mshr miss latency -system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1622351 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.996907 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20038370 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1622863 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.347543 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.996907 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88306374 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88306374 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 11941774 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11941774 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8035174 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8035174 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 59224 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 59224 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 19976948 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19976948 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20036172 # number of overall hits -system.cpu.dcache.overall_hits::total 20036172 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 907115 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 907115 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 325077 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 325077 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 402500 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 402500 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1232192 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1232192 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1634692 # number of overall misses -system.cpu.dcache.overall_misses::total 1634692 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12725992750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12725992750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11362158354 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11362158354 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24088151104 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24088151104 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24088151104 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24088151104 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 12848889 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12848889 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8360251 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8360251 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 461724 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 461724 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21209140 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21209140 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21670864 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21670864 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070599 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.070599 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038884 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.038884 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871733 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.871733 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.058097 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.058097 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.075433 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.075433 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14029.084240 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14029.084240 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34952.206259 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34952.206259 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19549.024100 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19549.024100 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14735.590010 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14735.590010 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 7616 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 81 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 94.024691 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1538923 # number of writebacks -system.cpu.dcache.writebacks::total 1538923 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 288 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 288 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9252 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9252 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 9540 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 9540 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 9540 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 9540 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906827 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 906827 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315825 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 315825 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402464 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 402464 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1222652 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1222652 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1625116 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1625116 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10904887500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10904887500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10229869846 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10229869846 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5337291000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5337291000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21134757346 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21134757346 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26472048346 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26472048346 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94240373000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94240373000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2561690500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2561690500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96802063500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96802063500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070576 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070576 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037777 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037777 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871655 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871655 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057647 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.057647 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074991 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074991 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12025.322912 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12025.322912 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32390.943864 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32390.943864 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13261.536436 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13261.536436 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17285.995807 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17285.995807 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16289.328482 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16289.328482 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2697012 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2696490 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13889 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13889 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1542758 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46721 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2211 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2211 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 313627 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 313627 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1583769 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5979028 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8638 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18387 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7589822 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50680192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203991823 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 256960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 613632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 255542607 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 52938 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4020768 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.011831 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.108123 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 3973200 98.82% 98.82% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 47568 1.18% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4020768 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3834027500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 487500 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1190285118 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3054401379 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 6935250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 13198750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 87384 # number of replacements system.cpu.l2cache.tags.tagsinuse 64746.924059 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3489247 # Total number of references to valid blocks. @@ -1326,5 +1021,310 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 2697012 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2696490 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13889 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13889 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1542758 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46721 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2211 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2211 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 313627 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 313627 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1583769 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5979028 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8638 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18387 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7589822 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50680192 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203991823 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 256960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 613632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 255542607 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 52938 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4020768 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.011831 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.108123 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 3973200 98.82% 98.82% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 47568 1.18% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4020768 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3834027500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 487500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1190285118 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3054401379 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer2.occupancy 6935250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer3.occupancy 13198750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 230267 # Transaction distribution +system.iobus.trans_dist::ReadResp 230267 # Transaction distribution +system.iobus.trans_dist::WriteReq 57693 # Transaction distribution +system.iobus.trans_dist::WriteResp 57694 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 1 # Transaction distribution +system.iobus.trans_dist::MessageReq 1655 # Transaction distribution +system.iobus.trans_dist::MessageResp 1655 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27696 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 480788 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95134 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95134 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3310 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 579232 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13848 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 246674 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027320 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027320 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6620 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3280614 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3947664 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 8813000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 77000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer9.occupancy 218343000 # Layer occupancy (ticks) +system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) +system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 20719000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 421906845 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 469814000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer1.occupancy 52234501 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer2.occupancy 1655000 # Layer occupancy (ticks) +system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) +system.iocache.tags.replacements 47512 # number of replacements +system.iocache.tags.tagsinuse 0.118180 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 47528 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 5045851318000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.118180 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007386 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.007386 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 428111 # Number of tag accesses +system.iocache.tags.data_accesses 428111 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits +system.iocache.ReadReq_misses::pc.south_bridge.ide 847 # number of ReadReq misses +system.iocache.ReadReq_misses::total 847 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 1 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 1 # number of WriteInvalidateReq misses +system.iocache.demand_misses::pc.south_bridge.ide 847 # number of demand (read+write) misses +system.iocache.demand_misses::total 847 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 847 # number of overall misses +system.iocache.overall_misses::total 847 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 141540186 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 141540186 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 141540186 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 141540186 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 141540186 # number of overall miss cycles +system.iocache.overall_miss_latency::total 141540186 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 847 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 847 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46721 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 46721 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::pc.south_bridge.ide 847 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 847 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 847 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 847 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 0.000021 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.000021 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 167107.657615 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 167107.657615 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 167107.657615 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 471 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.076923 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 46720 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 847 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 847 # number of ReadReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 847 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 847 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 847 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 847 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 97471186 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2827609160 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2827609160 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 97471186 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 97471186 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 115078.141677 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 115078.141677 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 115078.141677 # average overall mshr miss latency +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 624009 # Transaction distribution +system.membus.trans_dist::ReadResp 624009 # Transaction distribution +system.membus.trans_dist::WriteReq 13889 # Transaction distribution +system.membus.trans_dist::WriteResp 13889 # Transaction distribution +system.membus.trans_dist::Writeback 80466 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2168 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1629 # Transaction distribution +system.membus.trans_dist::ReadExReq 113541 # Transaction distribution +system.membus.trans_dist::ReadExResp 113541 # Transaction distribution +system.membus.trans_dist::MessageReq 1655 # Transaction distribution +system.membus.trans_dist::MessageResp 1655 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3310 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3310 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480788 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710112 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394547 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1585447 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94730 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 94730 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1683487 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6620 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246674 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420221 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15078912 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16745807 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19770859 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 943 # Total snoops (count) +system.membus.snoop_fanout::samples 285344 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 285344 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 285344 # Request fanout histogram +system.membus.reqLayer0.occupancy 257196000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 358105500 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 3310000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer3.occupancy 1311782500 # Layer occupancy (ticks) +system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.membus.respLayer0.occupancy 1655000 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 2622169871 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.1 # Layer utilization (%) +system.membus.respLayer4.occupancy 54356499 # Layer occupancy (ticks) +system.membus.respLayer4.utilization 0.0 # Layer utilization (%) +system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. +system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. +system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. +system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. +system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. +system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. ---------- End Simulation Statistics ---------- |