stats: update stale config.ini files, eio and few other stats.

author: Nilay Vaish <nilay@cs.wisc.edu> 2015-07-04 10:43:47 -0500
committer: Nilay Vaish <nilay@cs.wisc.edu> 2015-07-04 10:43:47 -0500
commit: 9954eb74df98c4749651eb78098595f78d642105 (patch)
tree: 74766341f05f999e2ad00626284e09dc6d0a2c58 /tests
parent: 67925a833445a8b2ddce0fae4c86677ce0f4298d (diff)
download: gem5-9954eb74df98c4749651eb78098595f78d642105.tar.xz
106 files changed, 6245 insertions, 10002 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini
index 7683e2958..a7c751a3c 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini
@@ -15,19 +15,20 @@ boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
 cache_line_size=64
 clk_domain=system.clk_domain
-console=/dist/binaries/console
+console=/scratch/nilay/GEM5/system/binaries/console
 eventq_index=0
 init_param=0
-kernel=/dist/binaries/vmlinux
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
 kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
 mem_ranges=0:134217727
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
-pal=/dist/binaries/ts_osfpal
-readfile=/work/gem5.latest/tests/halt.sh
+pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 symbolfile=
 system_rev=1024
 system_type=34
@@ -124,7 +125,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
 BTBEntries=4096
 BTBTagSize=16
 RASSize=16
@@ -138,7 +139,6 @@ localCtrBits=2
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
-predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
@@ -150,7 +150,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -161,7 +161,6 @@ size=32768
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -574,7 +573,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -585,7 +584,6 @@ size=32768
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -624,7 +622,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -635,7 +633,6 @@ size=4194304
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
@@ -654,8 +651,11 @@ size=4194304
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
@@ -694,7 +694,7 @@ table_size=65536
 [system.disk0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/dist/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -717,7 +717,7 @@ table_size=65536
 [system.disk2.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/dist/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.dvfs_handler]
@@ -737,9 +737,11 @@ sys=system
 type=NoncoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
 use_default_range=true
-width=8
+width=16
 default=system.tsunami.pciconfig.pio
 master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
 slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
@@ -754,7 +756,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -765,7 +767,6 @@ size=1024
 system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[29]
 mem_side=system.membus.slave[2]
@@ -785,11 +786,14 @@ type=CoherentXBar
 children=badaddr_responder
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 default=system.membus.badaddr_responder.pio
 master=system.bridge.slave system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
@@ -839,7 +843,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -899,7 +903,7 @@ system=system
 [system.simple_disk.disk]
 type=RawDiskImage
 eventq_index=0
-image_file=/dist/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal
index 075c19401..455709c02 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal
@@ -24,7 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
 memcluster 1, usage 0, start      392, end    16384
 
 freeing pages 1069:16384
 
 reserving pages 1069:1070
-
-4096K Bcache detected; load hit latency 30 cycles, load miss latency 140 cycles
+
+4096K Bcache detected; load hit latency 30 cycles, load miss latency 152 cycles
 
 SMP: 1 CPUs probed -- cpu_present_mask = 1
 
 Built 1 zonelists
 
 Kernel command line: root=/dev/hda1 console=ttyS0
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
index aca399d8a..2b4d92c81 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
@@ -15,10 +15,10 @@ boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
 cache_line_size=64
 clk_domain=system.clk_domain
-console=/home/stever/m5/m5_system_2.0b3/binaries/console
+console=/scratch/nilay/GEM5/system/binaries/console
 eventq_index=0
 init_param=0
-kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
 kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
@@ -27,8 +27,8 @@ mem_ranges=0:134217727
 memories=system.physmem
 mmap_using_noreserve=false
 num_work_ids=16
-pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
-readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
+pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 symbolfile=
 system_rev=1024
 system_type=34
@@ -175,7 +175,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -186,7 +186,6 @@ size=32768
 system=system
 tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
@@ -222,9 +221,9 @@ opList=system.cpu0.fuPool.FUList0.opList
 [system.cpu0.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList1]
 type=FUDesc
@@ -236,16 +235,16 @@ opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
 [system.cpu0.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu0.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=19
 opClass=IntDiv
 opLat=20
+pipelined=false
 
 [system.cpu0.fuPool.FUList2]
 type=FUDesc
@@ -257,23 +256,23 @@ opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 sys
 [system.cpu0.fuPool.FUList2.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=2
+pipelined=true
 
 [system.cpu0.fuPool.FUList2.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=2
+pipelined=true
 
 [system.cpu0.fuPool.FUList2.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=2
+pipelined=true
 
 [system.cpu0.fuPool.FUList3]
 type=FUDesc
@@ -285,23 +284,23 @@ opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 sys
 [system.cpu0.fuPool.FUList3.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu0.fuPool.FUList3.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=FloatDiv
 opLat=12
+pipelined=false
 
 [system.cpu0.fuPool.FUList3.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=24
 opClass=FloatSqrt
 opLat=24
+pipelined=false
 
 [system.cpu0.fuPool.FUList4]
 type=FUDesc
@@ -313,9 +312,9 @@ opList=system.cpu0.fuPool.FUList4.opList
 [system.cpu0.fuPool.FUList4.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5]
 type=FUDesc
@@ -327,142 +326,142 @@ opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 s
 [system.cpu0.fuPool.FUList5.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList6]
 type=FUDesc
@@ -474,9 +473,9 @@ opList=system.cpu0.fuPool.FUList6.opList
 [system.cpu0.fuPool.FUList6.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList7]
 type=FUDesc
@@ -488,16 +487,16 @@ opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1
 [system.cpu0.fuPool.FUList7.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList7.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList8]
 type=FUDesc
@@ -509,9 +508,9 @@ opList=system.cpu0.fuPool.FUList8.opList
 [system.cpu0.fuPool.FUList8.opList]
 type=OpDesc
 eventq_index=0
-issueLat=3
 opClass=IprAccess
 opLat=3
+pipelined=false
 
 [system.cpu0.icache]
 type=BaseCache
@@ -523,7 +522,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -534,7 +533,6 @@ size=32768
 system=system
 tags=system.cpu0.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
@@ -682,7 +680,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -693,7 +691,6 @@ size=32768
 system=system
 tags=system.cpu1.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.dcache_port
 mem_side=system.toL2Bus.slave[3]
@@ -729,9 +726,9 @@ opList=system.cpu1.fuPool.FUList0.opList
 [system.cpu1.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList1]
 type=FUDesc
@@ -743,16 +740,16 @@ opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1
 [system.cpu1.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu1.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=19
 opClass=IntDiv
 opLat=20
+pipelined=false
 
 [system.cpu1.fuPool.FUList2]
 type=FUDesc
@@ -764,23 +761,23 @@ opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 sys
 [system.cpu1.fuPool.FUList2.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=2
+pipelined=true
 
 [system.cpu1.fuPool.FUList2.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=2
+pipelined=true
 
 [system.cpu1.fuPool.FUList2.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=2
+pipelined=true
 
 [system.cpu1.fuPool.FUList3]
 type=FUDesc
@@ -792,23 +789,23 @@ opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 sys
 [system.cpu1.fuPool.FUList3.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu1.fuPool.FUList3.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=FloatDiv
 opLat=12
+pipelined=false
 
 [system.cpu1.fuPool.FUList3.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=24
 opClass=FloatSqrt
 opLat=24
+pipelined=false
 
 [system.cpu1.fuPool.FUList4]
 type=FUDesc
@@ -820,9 +817,9 @@ opList=system.cpu1.fuPool.FUList4.opList
 [system.cpu1.fuPool.FUList4.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5]
 type=FUDesc
@@ -834,142 +831,142 @@ opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 s
 [system.cpu1.fuPool.FUList5.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList6]
 type=FUDesc
@@ -981,9 +978,9 @@ opList=system.cpu1.fuPool.FUList6.opList
 [system.cpu1.fuPool.FUList6.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList7]
 type=FUDesc
@@ -995,16 +992,16 @@ opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1
 [system.cpu1.fuPool.FUList7.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList7.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList8]
 type=FUDesc
@@ -1016,9 +1013,9 @@ opList=system.cpu1.fuPool.FUList8.opList
 [system.cpu1.fuPool.FUList8.opList]
 type=OpDesc
 eventq_index=0
-issueLat=3
 opClass=IprAccess
 opLat=3
+pipelined=false
 
 [system.cpu1.icache]
 type=BaseCache
@@ -1030,7 +1027,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -1041,7 +1038,6 @@ size=32768
 system=system
 tags=system.cpu1.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.icache_port
 mem_side=system.toL2Bus.slave[2]
@@ -1102,7 +1098,7 @@ table_size=65536
 [system.disk0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -1125,7 +1121,7 @@ table_size=65536
 [system.disk2.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.dvfs_handler]
@@ -1164,7 +1160,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -1175,7 +1171,6 @@ size=1024
 system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[29]
 mem_side=system.membus.slave[2]
@@ -1200,7 +1195,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -1211,7 +1206,6 @@ size=4194304
 system=system
 tags=system.l2c.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
@@ -1348,7 +1342,7 @@ system=system
 [system.simple_disk.disk]
 type=RawDiskImage
 eventq_index=0
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
index 7e0283697..1425d639e 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
@@ -27,7 +27,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
 memcluster 1, usage 0, start      392, end    16384
 
 freeing pages 1069:16384
 
 reserving pages 1069:1070
-
-4096K Bcache detected; load hit latency 30 cycles, load miss latency 154 cycles
+
+4096K Bcache detected; load hit latency 30 cycles, load miss latency 152 cycles
 
 SMP: 2 CPUs probed -- cpu_present_mask = 3
 
 Built 1 zonelists
 
 Kernel command line: root=/dev/hda1 console=ttyS0
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
index 4de22817f..3eacf4507 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
@@ -15,10 +15,10 @@ boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
 cache_line_size=64
 clk_domain=system.clk_domain
-console=/home/stever/m5/m5_system_2.0b3/binaries/console
+console=/scratch/nilay/GEM5/system/binaries/console
 eventq_index=0
 init_param=0
-kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
 kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
@@ -27,8 +27,8 @@ mem_ranges=0:134217727
 memories=system.physmem
 mmap_using_noreserve=false
 num_work_ids=16
-pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
-readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
+pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 symbolfile=
 system_rev=1024
 system_type=34
@@ -175,7 +175,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -186,7 +186,6 @@ size=32768
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -222,9 +221,9 @@ opList=system.cpu.fuPool.FUList0.opList
 [system.cpu.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList1]
 type=FUDesc
@@ -236,16 +235,16 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 [system.cpu.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=19
 opClass=IntDiv
 opLat=20
+pipelined=false
 
 [system.cpu.fuPool.FUList2]
 type=FUDesc
@@ -257,23 +256,23 @@ opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 syste
 [system.cpu.fuPool.FUList2.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList2.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList2.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList3]
 type=FUDesc
@@ -285,23 +284,23 @@ opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 syste
 [system.cpu.fuPool.FUList3.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList3.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=FloatDiv
 opLat=12
+pipelined=false
 
 [system.cpu.fuPool.FUList3.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=24
 opClass=FloatSqrt
 opLat=24
+pipelined=false
 
 [system.cpu.fuPool.FUList4]
 type=FUDesc
@@ -313,9 +312,9 @@ opList=system.cpu.fuPool.FUList4.opList
 [system.cpu.fuPool.FUList4.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5]
 type=FUDesc
@@ -327,142 +326,142 @@ opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 sys
 [system.cpu.fuPool.FUList5.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList6]
 type=FUDesc
@@ -474,9 +473,9 @@ opList=system.cpu.fuPool.FUList6.opList
 [system.cpu.fuPool.FUList6.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList7]
 type=FUDesc
@@ -488,16 +487,16 @@ opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 [system.cpu.fuPool.FUList7.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList7.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList8]
 type=FUDesc
@@ -509,9 +508,9 @@ opList=system.cpu.fuPool.FUList8.opList
 [system.cpu.fuPool.FUList8.opList]
 type=OpDesc
 eventq_index=0
-issueLat=3
 opClass=IprAccess
 opLat=3
+pipelined=false
 
 [system.cpu.icache]
 type=BaseCache
@@ -523,7 +522,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -534,7 +533,6 @@ size=32768
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -573,7 +571,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -584,7 +582,6 @@ size=4194304
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
@@ -646,7 +643,7 @@ table_size=65536
 [system.disk0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -669,7 +666,7 @@ table_size=65536
 [system.disk2.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.dvfs_handler]
@@ -708,7 +705,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -719,7 +716,6 @@ size=1024
 system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[29]
 mem_side=system.membus.slave[2]
@@ -856,7 +852,7 @@ system=system
 [system.simple_disk.disk]
 type=RawDiskImage
 eventq_index=0
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
index 008c44f37..455709c02 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
@@ -24,7 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
 memcluster 1, usage 0, start      392, end    16384
 
 freeing pages 1069:16384
 
 reserving pages 1069:1070
-
-4096K Bcache detected; load hit latency 30 cycles, load miss latency 154 cycles
+
+4096K Bcache detected; load hit latency 30 cycles, load miss latency 152 cycles
 
 SMP: 1 CPUs probed -- cpu_present_mask = 1
 
 Built 1 zonelists
 
 Kernel command line: root=/dev/hda1 console=ttyS0
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
index 2d4d2bc38..d49d26c09 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
@@ -15,10 +15,10 @@ boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
 cache_line_size=64
 clk_domain=system.clk_domain
-console=/home/stever/m5/m5_system_2.0b3/binaries/console
+console=/scratch/nilay/GEM5/system/binaries/console
 eventq_index=0
 init_param=0
-kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
 kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
@@ -27,8 +27,8 @@ mem_ranges=0:134217727
 memories=system.physmem
 mmap_using_noreserve=false
 num_work_ids=16
-pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
-readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
+pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 symbolfile=
 system_rev=1024
 system_type=34
@@ -107,7 +107,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -118,7 +118,6 @@ size=32768
 system=system
 tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
@@ -148,7 +147,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -159,7 +158,6 @@ size=32768
 system=system
 tags=system.cpu0.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
@@ -366,9 +364,9 @@ opList=system.cpu2.fuPool.FUList0.opList
 [system.cpu2.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList1]
 type=FUDesc
@@ -380,16 +378,16 @@ opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1
 [system.cpu2.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu2.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=19
 opClass=IntDiv
 opLat=20
+pipelined=false
 
 [system.cpu2.fuPool.FUList2]
 type=FUDesc
@@ -401,23 +399,23 @@ opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 sys
 [system.cpu2.fuPool.FUList2.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=2
+pipelined=true
 
 [system.cpu2.fuPool.FUList2.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=2
+pipelined=true
 
 [system.cpu2.fuPool.FUList2.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=2
+pipelined=true
 
 [system.cpu2.fuPool.FUList3]
 type=FUDesc
@@ -429,23 +427,23 @@ opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 sys
 [system.cpu2.fuPool.FUList3.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu2.fuPool.FUList3.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=FloatDiv
 opLat=12
+pipelined=false
 
 [system.cpu2.fuPool.FUList3.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=24
 opClass=FloatSqrt
 opLat=24
+pipelined=false
 
 [system.cpu2.fuPool.FUList4]
 type=FUDesc
@@ -457,9 +455,9 @@ opList=system.cpu2.fuPool.FUList4.opList
 [system.cpu2.fuPool.FUList4.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5]
 type=FUDesc
@@ -471,142 +469,142 @@ opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 s
 [system.cpu2.fuPool.FUList5.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList6]
 type=FUDesc
@@ -618,9 +616,9 @@ opList=system.cpu2.fuPool.FUList6.opList
 [system.cpu2.fuPool.FUList6.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList7]
 type=FUDesc
@@ -632,16 +630,16 @@ opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
 [system.cpu2.fuPool.FUList7.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList7.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList8]
 type=FUDesc
@@ -653,9 +651,9 @@ opList=system.cpu2.fuPool.FUList8.opList
 [system.cpu2.fuPool.FUList8.opList]
 type=OpDesc
 eventq_index=0
-issueLat=3
 opClass=IprAccess
 opLat=3
+pipelined=false
 
 [system.cpu2.isa]
 type=AlphaISA
@@ -699,7 +697,7 @@ table_size=65536
 [system.disk0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -722,7 +720,7 @@ table_size=65536
 [system.disk2.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.dvfs_handler]
@@ -761,7 +759,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -772,7 +770,6 @@ size=1024
 system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[29]
 mem_side=system.membus.slave[2]
@@ -797,7 +794,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -808,7 +805,6 @@ size=4194304
 system=system
 tags=system.l2c.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
@@ -945,7 +941,7 @@ system=system
 [system.simple_disk.disk]
 type=RawDiskImage
 eventq_index=0
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr
index ffff6ec3c..ae9247519 100755
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr
@@ -3,12 +3,12 @@ warn: Sockets disabled, not accepting terminal connections
 warn: Sockets disabled, not accepting gdb connections
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 8155, Bank: 7
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -20,7 +20,13 @@ Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: Bank is already active!
-Command: 0, Timestamp: 10136, Bank: 0
+Command: 0, Timestamp: 11185, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -48,6 +54,6 @@ Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: Bank is already active!
-Command: 0, Timestamp: 11138, Bank: 3
+Command: 0, Timestamp: 11369, Bank: 3
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini
index d9c429968..4e40ecf7a 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -188,7 +188,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=6
 prefetch_on_access=false
@@ -647,7 +647,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=1
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=2
 prefetch_on_access=false
@@ -757,7 +757,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=12
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=16
 prefetch_on_access=true
@@ -918,7 +918,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=6
 prefetch_on_access=false
@@ -1377,7 +1377,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=1
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=2
 prefetch_on_access=false
@@ -1487,7 +1487,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=12
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=16
 prefetch_on_access=true
@@ -1600,7 +1600,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -1635,7 +1635,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini
index 23230d1e0..ec83c8fb6 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -188,7 +188,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -647,7 +647,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -757,7 +757,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -845,7 +845,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
index 4dbc37659..6227da137 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
@@ -12,25 +12,23 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-boot_release_addr=65528
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
 flags_addr=469827632
 gic_cpu_addr=738205696
-have_generic_timer=false
 have_large_asid_64=false
 have_lpae=false
 have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -44,7 +42,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -87,7 +85,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -363,7 +361,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -374,7 +372,6 @@ size=32768
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -446,9 +443,9 @@ opList=system.cpu.fuPool.FUList0.opList
 [system.cpu.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList1]
 type=FUDesc
@@ -460,23 +457,23 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 syste
 [system.cpu.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=IntDiv
 opLat=12
+pipelined=false
 
 [system.cpu.fuPool.FUList1.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IprAccess
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList2]
 type=FUDesc
@@ -488,9 +485,9 @@ opList=system.cpu.fuPool.FUList2.opList
 [system.cpu.fuPool.FUList2.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList3]
 type=FUDesc
@@ -502,9 +499,9 @@ opList=system.cpu.fuPool.FUList3.opList
 [system.cpu.fuPool.FUList3.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList4]
 type=FUDesc
@@ -516,184 +513,184 @@ opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 sys
 [system.cpu.fuPool.FUList4.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=9
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=9
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList20]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList21]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList22]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList23]
 type=OpDesc
 eventq_index=0
-issueLat=9
 opClass=FloatDiv
 opLat=9
+pipelined=false
 
 [system.cpu.fuPool.FUList4.opList24]
 type=OpDesc
 eventq_index=0
-issueLat=33
 opClass=FloatSqrt
 opLat=33
+pipelined=false
 
 [system.cpu.fuPool.FUList4.opList25]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu.icache]
 type=BaseCache
@@ -705,7 +702,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -716,7 +713,6 @@ size=32768
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -816,7 +812,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -827,7 +823,6 @@ size=4194304
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
@@ -905,7 +900,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -916,7 +911,6 @@ size=1024
 system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[27]
 mem_side=system.membus.slave[3]
@@ -1284,7 +1278,8 @@ pio=system.iobus.master[25]
 type=GenericTimer
 eventq_index=0
 gic=system.realview.gic
-int_num=29
+int_phys=29
+int_virt=27
 system=system
 
 [system.realview.gic]
@@ -1314,6 +1309,7 @@ pio_latency=10000
 pixel_clock=7299
 system=system
 vnc=system.vncserver
+workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
 
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
index 9332ae5c7..06829ebfc 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
@@ -210,7 +210,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=6
 prefetch_on_access=false
@@ -551,7 +551,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=1
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=2
 prefetch_on_access=false
@@ -661,7 +661,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=12
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=16
 prefetch_on_access=true
@@ -844,7 +844,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=6
 prefetch_on_access=false
@@ -1185,7 +1185,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=1
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=2
 prefetch_on_access=false
@@ -1295,7 +1295,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=12
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=16
 prefetch_on_access=true
@@ -1408,7 +1408,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -1443,7 +1443,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
index d6745503c..b6712dc14 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
@@ -23,6 +23,7 @@ warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
 warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
 warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
 warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
+warn: CP14 unimplemented crn[4], opc1[4], crm[0], opc2[0]
 warn: Not doing anything for miscreg ACTLR
 warn: Not doing anything for write of miscreg ACTLR
 warn: 	instruction 'mcr bpiall' unimplemented
@@ -31,6 +32,7 @@ warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
 warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
 warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
 warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
+warn: allocating bonus target for snoop
 warn: Returning zero for read from miscreg pmcr
 warn: Ignoring write to miscreg pmcntenclr
 warn: Ignoring write to miscreg pmintenclr
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
index cd7aeb29d..3ad068601 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
@@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2625378187500 because m5_exit instruction encountered
+Exiting @ tick 2625394935000 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
index 51ea3fd8c..82662bafe 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.625395                       # Nu
 sim_ticks                                2625394935000                       # Number of ticks simulated
 final_tick                               2625394935000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  95356                       # Simulator instruction rate (inst/s)
-host_op_rate                                   115687                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2080724894                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 655064                       # Number of bytes of host memory used
-host_seconds                                  1261.77                       # Real time elapsed on the host
+host_inst_rate                                  71798                       # Simulator instruction rate (inst/s)
+host_op_rate                                    87106                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1566670818                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 647044                       # Number of bytes of host memory used
+host_seconds                                  1675.78                       # Real time elapsed on the host
 sim_insts                                   120317196                       # Number of instructions simulated
 sim_ops                                     145970023                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -774,9 +774,9 @@ system.cpu0.iew.iewDispNonSpecInsts            851631                       # Nu
 system.cpu0.iew.iewIQFullEvents                 24928                       # Number of times the IQ has become full, causing a stall
 system.cpu0.iew.iewLSQFullEvents               129599                       # Number of times the LSQ has become full, causing a stall
 system.cpu0.iew.memOrderViolationEvents         18950                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        275041                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedTakenIncorrect        275039                       # Number of branches that were predicted taken incorrectly
 system.cpu0.iew.predictedNotTakenIncorrect       375413                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              650454                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.branchMispredicts              650452                       # Number of branch mispredicts detected at execute
 system.cpu0.iew.iewExecutedInsts            126634007                       # Number of executed instructions
 system.cpu0.iew.iewExecLoadInsts             22982824                       # Number of load instructions executed
 system.cpu0.iew.iewExecSquashedInsts           968597                       # Number of squashed instructions skipped in execute
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
index 67d41e91a..367b2246b 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
@@ -212,7 +212,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -223,7 +223,6 @@ size=32768
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -295,9 +294,9 @@ opList=system.cpu.fuPool.FUList0.opList
 [system.cpu.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList1]
 type=FUDesc
@@ -309,23 +308,23 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 syste
 [system.cpu.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=IntDiv
 opLat=12
+pipelined=false
 
 [system.cpu.fuPool.FUList1.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IprAccess
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList2]
 type=FUDesc
@@ -337,9 +336,9 @@ opList=system.cpu.fuPool.FUList2.opList
 [system.cpu.fuPool.FUList2.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList3]
 type=FUDesc
@@ -351,9 +350,9 @@ opList=system.cpu.fuPool.FUList3.opList
 [system.cpu.fuPool.FUList3.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList4]
 type=FUDesc
@@ -365,184 +364,184 @@ opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 sys
 [system.cpu.fuPool.FUList4.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=9
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=9
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList20]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList21]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList22]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList23]
 type=OpDesc
 eventq_index=0
-issueLat=9
 opClass=FloatDiv
 opLat=9
+pipelined=false
 
 [system.cpu.fuPool.FUList4.opList24]
 type=OpDesc
 eventq_index=0
-issueLat=33
 opClass=FloatSqrt
 opLat=33
+pipelined=false
 
 [system.cpu.fuPool.FUList4.opList25]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu.icache]
 type=BaseCache
@@ -554,7 +553,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -565,7 +564,6 @@ size=32768
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -665,7 +663,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -676,7 +674,6 @@ size=4194304
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
@@ -754,7 +751,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -765,7 +762,6 @@ size=1024
 system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[27]
 mem_side=system.membus.slave[3]
@@ -1133,7 +1129,8 @@ pio=system.iobus.master[25]
 type=GenericTimer
 eventq_index=0
 gic=system.realview.gic
-int_num=29
+int_phys=29
+int_virt=27
 system=system
 
 [system.realview.gic]
@@ -1163,6 +1160,7 @@ pio_latency=10000
 pixel_clock=7299
 system=system
 vnc=system.vncserver
+workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
 
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
index ab972f12d..7a0ceb162 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
@@ -8,6 +8,8 @@ warn: Not doing anything for write of miscreg ACTLR
 warn: The clidr register always reports 0 caches.
 warn: clidr LoUIS field of 0b001 to match current ARM implementations.
 warn: The csselr register isn't implemented.
+warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0]
+warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0]
 warn: 	instruction 'mcr dccmvau' unimplemented
 warn: 	instruction 'mcr icimvau' unimplemented
 warn: 	instruction 'mcr bpiallis' unimplemented
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
index 200432120..13794ff0e 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
@@ -147,7 +147,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -158,7 +158,6 @@ size=32768
 system=system
 tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
@@ -224,7 +223,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -235,7 +234,6 @@ size=32768
 system=system
 tags=system.cpu0.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
@@ -637,9 +635,9 @@ opList=system.cpu2.fuPool.FUList0.opList
 [system.cpu2.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList1]
 type=FUDesc
@@ -651,16 +649,16 @@ opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1
 [system.cpu2.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu2.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=19
 opClass=IntDiv
 opLat=20
+pipelined=false
 
 [system.cpu2.fuPool.FUList2]
 type=FUDesc
@@ -672,23 +670,23 @@ opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 sys
 [system.cpu2.fuPool.FUList2.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=2
+pipelined=true
 
 [system.cpu2.fuPool.FUList2.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=2
+pipelined=true
 
 [system.cpu2.fuPool.FUList2.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=2
+pipelined=true
 
 [system.cpu2.fuPool.FUList3]
 type=FUDesc
@@ -700,23 +698,23 @@ opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 sys
 [system.cpu2.fuPool.FUList3.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu2.fuPool.FUList3.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=FloatDiv
 opLat=12
+pipelined=false
 
 [system.cpu2.fuPool.FUList3.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=24
 opClass=FloatSqrt
 opLat=24
+pipelined=false
 
 [system.cpu2.fuPool.FUList4]
 type=FUDesc
@@ -728,9 +726,9 @@ opList=system.cpu2.fuPool.FUList4.opList
 [system.cpu2.fuPool.FUList4.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5]
 type=FUDesc
@@ -742,142 +740,142 @@ opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 s
 [system.cpu2.fuPool.FUList5.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList6]
 type=FUDesc
@@ -889,9 +887,9 @@ opList=system.cpu2.fuPool.FUList6.opList
 [system.cpu2.fuPool.FUList6.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList7]
 type=FUDesc
@@ -903,16 +901,16 @@ opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
 [system.cpu2.fuPool.FUList7.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList7.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList8]
 type=FUDesc
@@ -924,9 +922,9 @@ opList=system.cpu2.fuPool.FUList8.opList
 [system.cpu2.fuPool.FUList8.opList]
 type=OpDesc
 eventq_index=0
-issueLat=3
 opClass=IprAccess
 opLat=3
+pipelined=false
 
 [system.cpu2.isa]
 type=ArmISA
@@ -1046,7 +1044,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -1057,7 +1055,6 @@ size=1024
 system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[27]
 mem_side=system.membus.slave[3]
@@ -1082,7 +1079,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -1093,7 +1090,6 @@ size=4194304
 system=system
 tags=system.l2c.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
@@ -1461,7 +1457,8 @@ pio=system.iobus.master[25]
 type=GenericTimer
 eventq_index=0
 gic=system.realview.gic
-int_num=29
+int_phys=29
+int_virt=27
 system=system
 
 [system.realview.gic]
@@ -1491,6 +1488,7 @@ pio_latency=10000
 pixel_clock=7299
 system=system
 vnc=system.vncserver
+workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
 
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr
index 2ca4d069e..1fcf437ee 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr
@@ -39,11 +39,11 @@ Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: Bank is already active!
-Command: 0, Timestamp: 7183, Bank: 4
+Command: 0, Timestamp: 7330, Bank: 4
 WARNING: Bank is already active!
-Command: 0, Timestamp: 9208, Bank: 3
+Command: 0, Timestamp: 9347, Bank: 3
 WARNING: Bank is already active!
-Command: 0, Timestamp: 9352, Bank: 2
+Command: 0, Timestamp: 9490, Bank: 2
 warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0]
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
@@ -55,12 +55,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6448, Bank: 7
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6590, Bank: 5
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6595, Bank: 6
 warn: Returning zero for read from miscreg pmcr
 warn: Ignoring write to miscreg pmcntenclr
 warn: Ignoring write to miscreg pmintenclr
@@ -68,6 +62,8 @@ warn: Ignoring write to miscreg pmovsr
 warn: Ignoring write to miscreg pmcr
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[2]
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
@@ -93,8 +89,8 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9610, Bank: 2
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -104,31 +100,41 @@ Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 warn: 	instruction 'mcr bpiall' unimplemented
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7104, Bank: 5
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7593, Bank: 6
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8685, Bank: 7
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8108, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10142, Bank: 1
 warn: 	instruction 'mcr dcisw' unimplemented
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: Bank is already active!
-Command: 0, Timestamp: 7230, Bank: 7
+Command: 0, Timestamp: 6533, Bank: 1
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
index f06fb64e9..df306f02a 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -42,7 +42,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -85,7 +85,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -213,7 +213,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -596,7 +596,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -1270,7 +1270,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -1305,7 +1305,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr
index 750274093..b551fcaf9 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr
@@ -26,7 +26,7 @@ warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
 warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
 warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
 warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
-warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[3]
+warn: CP14 unimplemented crn[5], opc1[4], crm[4], opc2[5]
 warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
 warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
 warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
@@ -34,6 +34,7 @@ warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
 warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
 warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0]
 warn: CP14 unimplemented crn[0], opc1[4], crm[8], opc2[1]
+warn: CP14 unimplemented crn[0], opc1[4], crm[0], opc2[0]
 warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[3]
 warn: CP14 unimplemented crn[6], opc1[5], crm[4], opc2[3]
 warn: Returning zero for read from miscreg pmcr
@@ -41,9 +42,9 @@ warn: Ignoring write to miscreg pmcntenclr
 warn: Ignoring write to miscreg pmintenclr
 warn: Ignoring write to miscreg pmovsr
 warn: Ignoring write to miscreg pmcr
-warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[2]
 warn: CP14 unimplemented crn[0], opc1[4], crm[12], opc2[2]
-warn: CP14 unimplemented crn[15], opc1[0], crm[8], opc2[0]
+warn: CP14 unimplemented crn[3], opc1[4], crm[0], opc2[3]
+warn: CP14 unimplemented crn[3], opc1[4], crm[4], opc2[3]
 warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[2]
 warn: 	instruction 'mcr bpiall' unimplemented
 warn: User mode does not have SPSR
@@ -54,3 +55,11 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
index a839f8e59..d8bee446b 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
@@ -1727,9 +1727,9 @@ system.cpu1.iew.iewDispNonSpecInsts            585452                       # Nu
 system.cpu1.iew.iewIQFullEvents                 40704                       # Number of times the IQ has become full, causing a stall
 system.cpu1.iew.iewLSQFullEvents               687401                       # Number of times the LSQ has become full, causing a stall
 system.cpu1.iew.memOrderViolationEvents         51353                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect        260476                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       222264                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              482740                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.predictedTakenIncorrect        260478                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       222263                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              482741                       # Number of branch mispredicts detected at execute
 system.cpu1.iew.iewExecutedInsts             79065408                       # Number of executed instructions
 system.cpu1.iew.iewExecLoadInsts             14638962                       # Number of load instructions executed
 system.cpu1.iew.iewExecSquashedInsts           552436                       # Number of squashed instructions skipped in execute
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini
index 33618dc77..66f5e8613 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini
@@ -165,7 +165,7 @@ dcache_port=system.cpu0.dcache.cpu_side
 icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.branchPred]
-type=BranchPredictor
+type=TournamentBP
 BTBEntries=4096
 BTBTagSize=16
 RASSize=16
@@ -179,7 +179,6 @@ localCtrBits=2
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
-predType=tournament
 
 [system.cpu0.dcache]
 type=BaseCache
@@ -191,7 +190,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=6
 prefetch_on_access=false
@@ -202,7 +201,6 @@ size=32768
 system=system
 tags=system.cpu0.dcache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=16
 cpu_side=system.cpu0.dcache_port
 mem_side=system.cpu0.toL2Bus.slave[1]
@@ -649,9 +647,9 @@ assoc=2
 clk_domain=system.cpu_clk_domain
 demand_mshr_reserve=1
 eventq_index=0
-forward_snoops=true
+forward_snoops=false
 hit_latency=1
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=2
 prefetch_on_access=false
@@ -662,7 +660,6 @@ size=32768
 system=system
 tags=system.cpu0.icache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.cpu0.toL2Bus.slave[0]
@@ -762,7 +759,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=12
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=16
 prefetch_on_access=true
@@ -773,7 +770,6 @@ size=1048576
 system=system
 tags=system.cpu0.l2cache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.toL2Bus.master[0]
 mem_side=system.toL2Bus.slave[0]
@@ -899,7 +895,7 @@ dcache_port=system.cpu1.dcache.cpu_side
 icache_port=system.cpu1.icache.cpu_side
 
 [system.cpu1.branchPred]
-type=BranchPredictor
+type=TournamentBP
 BTBEntries=4096
 BTBTagSize=16
 RASSize=16
@@ -913,7 +909,6 @@ localCtrBits=2
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
-predType=tournament
 
 [system.cpu1.dcache]
 type=BaseCache
@@ -925,7 +920,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=6
 prefetch_on_access=false
@@ -936,7 +931,6 @@ size=32768
 system=system
 tags=system.cpu1.dcache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=16
 cpu_side=system.cpu1.dcache_port
 mem_side=system.cpu1.toL2Bus.slave[1]
@@ -1383,9 +1377,9 @@ assoc=2
 clk_domain=system.cpu_clk_domain
 demand_mshr_reserve=1
 eventq_index=0
-forward_snoops=true
+forward_snoops=false
 hit_latency=1
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=2
 prefetch_on_access=false
@@ -1396,7 +1390,6 @@ size=32768
 system=system
 tags=system.cpu1.icache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.icache_port
 mem_side=system.cpu1.toL2Bus.slave[0]
@@ -1496,7 +1489,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=12
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=16
 prefetch_on_access=true
@@ -1507,7 +1500,6 @@ size=1048576
 system=system
 tags=system.cpu1.l2cache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.toL2Bus.master[0]
 mem_side=system.toL2Bus.slave[1]
@@ -1610,7 +1602,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -1621,7 +1613,6 @@ size=1024
 system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[27]
 mem_side=system.membus.slave[3]
@@ -1646,7 +1637,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -1657,7 +1648,6 @@ size=4194304
 system=system
 tags=system.l2c.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
@@ -1686,7 +1676,7 @@ system=system
 use_default_range=false
 width=16
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
 slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
 
 [system.membus.badaddr_responder]
@@ -2025,7 +2015,8 @@ pio=system.iobus.master[25]
 type=GenericTimer
 eventq_index=0
 gic=system.realview.gic
-int_num=29
+int_phys=29
+int_virt=27
 system=system
 
 [system.realview.gic]
@@ -2038,7 +2029,6 @@ dist_pio_delay=10000
 eventq_index=0
 int_latency=10000
 it_lines=128
-msix_addr=0
 platform=system.realview
 system=system
 pio=system.membus.master[2]
@@ -2056,6 +2046,7 @@ pio_latency=10000
 pixel_clock=7299
 system=system
 vnc=system.vncserver
+workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
 
@@ -2225,7 +2216,7 @@ int_num_watchdog=30
 pio_addr=738721792
 pio_latency=100000
 system=system
-pio=system.membus.master[3]
+pio=system.membus.master[4]
 
 [system.realview.mmc_fake]
 type=AmbaFake
@@ -2407,7 +2398,7 @@ platform=system.realview
 ppint=25
 system=system
 vcpu_addr=738222080
-pio=system.membus.master[4]
+pio=system.membus.master[3]
 
 [system.realview.vram]
 type=SimpleMemory
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini
index ef40366e9..7ef33a7a5 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini
@@ -165,7 +165,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
 BTBEntries=4096
 BTBTagSize=16
 RASSize=16
@@ -179,7 +179,6 @@ localCtrBits=2
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
-predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
@@ -191,7 +190,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -202,7 +201,6 @@ size=32768
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -651,7 +649,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -662,7 +660,6 @@ size=32768
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -762,7 +759,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -773,7 +770,6 @@ size=4194304
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
@@ -851,7 +847,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -862,7 +858,6 @@ size=1024
 system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[27]
 mem_side=system.membus.slave[3]
@@ -891,7 +886,7 @@ system=system
 use_default_range=false
 width=16
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
 slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
 
 [system.membus.badaddr_responder]
@@ -1230,7 +1225,8 @@ pio=system.iobus.master[25]
 type=GenericTimer
 eventq_index=0
 gic=system.realview.gic
-int_num=29
+int_phys=29
+int_virt=27
 system=system
 
 [system.realview.gic]
@@ -1243,7 +1239,6 @@ dist_pio_delay=10000
 eventq_index=0
 int_latency=10000
 it_lines=128
-msix_addr=0
 platform=system.realview
 system=system
 pio=system.membus.master[2]
@@ -1261,6 +1256,7 @@ pio_latency=10000
 pixel_clock=7299
 system=system
 vnc=system.vncserver
+workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
 
@@ -1430,7 +1426,7 @@ int_num_watchdog=30
 pio_addr=738721792
 pio_latency=100000
 system=system
-pio=system.membus.master[3]
+pio=system.membus.master[4]
 
 [system.realview.mmc_fake]
 type=AmbaFake
@@ -1612,7 +1608,7 @@ platform=system.realview
 ppint=25
 system=system
 vcpu_addr=738222080
-pio=system.membus.master[4]
+pio=system.membus.master[3]
 
 [system.realview.vram]
 type=SimpleMemory
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/config.ini
index 4d2b2f309..b4c7e90f4 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/config.ini
@@ -363,7 +363,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -374,7 +374,6 @@ size=32768
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -446,9 +445,9 @@ opList=system.cpu.fuPool.FUList0.opList
 [system.cpu.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList1]
 type=FUDesc
@@ -460,23 +459,23 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 syste
 [system.cpu.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=IntDiv
 opLat=12
+pipelined=false
 
 [system.cpu.fuPool.FUList1.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IprAccess
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList2]
 type=FUDesc
@@ -488,9 +487,9 @@ opList=system.cpu.fuPool.FUList2.opList
 [system.cpu.fuPool.FUList2.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList3]
 type=FUDesc
@@ -502,9 +501,9 @@ opList=system.cpu.fuPool.FUList3.opList
 [system.cpu.fuPool.FUList3.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList4]
 type=FUDesc
@@ -516,184 +515,184 @@ opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 sys
 [system.cpu.fuPool.FUList4.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=9
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=9
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList20]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList21]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList22]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList23]
 type=OpDesc
 eventq_index=0
-issueLat=9
 opClass=FloatDiv
 opLat=9
+pipelined=false
 
 [system.cpu.fuPool.FUList4.opList24]
 type=OpDesc
 eventq_index=0
-issueLat=33
 opClass=FloatSqrt
 opLat=33
+pipelined=false
 
 [system.cpu.fuPool.FUList4.opList25]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu.icache]
 type=BaseCache
@@ -705,7 +704,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -716,7 +715,6 @@ size=32768
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -816,7 +814,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -827,7 +825,6 @@ size=4194304
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
@@ -905,7 +902,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -916,7 +913,6 @@ size=1024
 system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[27]
 mem_side=system.membus.slave[3]
@@ -1284,7 +1280,8 @@ pio=system.iobus.master[25]
 type=GenericTimer
 eventq_index=0
 gic=system.realview.gic
-int_num=29
+int_phys=29
+int_virt=27
 system=system
 
 [system.realview.gic]
@@ -1314,6 +1311,7 @@ pio_latency=10000
 pixel_clock=7299
 system=system
 vnc=system.vncserver
+workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
 
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr
index c2a0ed9be..d76e2074b 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr
@@ -7,95 +7,88 @@ warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
 warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0
 warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
 warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-warn: 12458605972000: Instruction results do not match! (Values may not actually be integers) Inst: 0xffffffc00d07d780, checker: 0
-warn: 12458609273000: Instruction results do not match! (Values may not actually be integers) Inst: 0xffffffc00d07d7c0, checker: 0
+warn: 12461855003000: Instruction results do not match! (Values may not actually be integers) Inst: 0xffffffc00d07d780, checker: 0
+warn: 12461858210000: Instruction results do not match! (Values may not actually be integers) Inst: 0xffffffc00d07d7c0, checker: 0
 warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
 warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-warn: 13847380989000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 13886976040500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 13909524462000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 13910098545500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 13910493556500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 13910725565500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 13910949758000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 13919499191000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 13969109987000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 14211548964500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14211549180000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14219621260500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14227403410000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14227403653500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14227403893000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14227404099500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14235187327500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14235187571000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14235187810500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14235188017000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14240340342500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14240340582000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14246517945500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14246518185000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14256052185500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14256052714000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14256052957500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14256053197000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14256053403500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14267019457500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14267019664000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14276718921000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14276719431500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14276719666000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14276719896500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14276720103000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14292023524000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14292024562000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14292024768500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14297044932500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14297045442000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14297045676000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14297045906000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14297046112500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14313983409500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14313983919000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14313984153000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14313984383000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14313984589500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14376592133500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14376592349000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14434071886000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14434072706000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14434072954500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14434073170000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14562296155000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14562381650500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14562381898500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14562382116000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14562382402000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1
-warn: 14562382961000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14562383216500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14562383439500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14562383728500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14562384237500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14562385304500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14562385789500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14562386108000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14563103347000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14563103608000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x42
-warn: 14563103812500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14563174588000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91
-warn: 14563174798000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14563175069000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1
-warn: 14563175639500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14563175895000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91
-warn: 14563176118500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14563176407500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14563176916500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14563177979500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14563178471000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14563178773000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14611314421000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1
-warn: 14611314697500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14611314949500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14611315194000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14611315463500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14611315702500: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1
+warn: 13850221736500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13887901759500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13889201357500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13891026528000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13912972124000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13922135264000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13972304377500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 14214756028000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14214756243500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14222804811500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14230560980500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14230561210500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14230561417000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14238296234000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14238296464000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14238296670500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14243468378000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14243468608000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14249670454500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14249670684500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14259219992000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14259220222000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14259220428500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14270200247500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14270200481500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14270200711500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14270200918000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14279912002500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14279912512000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14279912746000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14279912976000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14279913182500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14295232623000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14295232862500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14300292322000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14300292552000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14307240927500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14307241161500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14307241391500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14307241598000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14317300126000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14317300896500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14317301130500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14317301360500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14317301567000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14379824982500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14379825231000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14379825446500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14437325800500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14437326869000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14437327084500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14565495184000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14565581739000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14565581956000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14565582249000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1
+warn: 14565582808000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14565583286500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14565583575500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14565584084500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14565585151500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14565585961500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14566302033500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14566302294500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x42
+warn: 14566302499000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14566373295000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91
+warn: 14566373505000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14566373776000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1
+warn: 14566374346500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14566374602000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91
+warn: 14566374825500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14566375114500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14566375623500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14566376687000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14566377185000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14566377487000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14614511931000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1
+warn: 14614512222000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14614512481000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14614512725500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14614512987500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14614513217000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini
index 05f59cec5..d3e5a5093 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini
@@ -212,7 +212,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=6
 prefetch_on_access=false
@@ -223,7 +223,6 @@ size=32768
 system=system
 tags=system.cpu0.dcache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=16
 cpu_side=system.cpu0.dcache_port
 mem_side=system.cpu0.toL2Bus.slave[1]
@@ -295,9 +294,9 @@ opList=system.cpu0.fuPool.FUList0.opList
 [system.cpu0.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList1]
 type=FUDesc
@@ -309,23 +308,23 @@ opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 sys
 [system.cpu0.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu0.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=IntDiv
 opLat=12
+pipelined=false
 
 [system.cpu0.fuPool.FUList1.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IprAccess
 opLat=3
+pipelined=true
 
 [system.cpu0.fuPool.FUList2]
 type=FUDesc
@@ -337,9 +336,9 @@ opList=system.cpu0.fuPool.FUList2.opList
 [system.cpu0.fuPool.FUList2.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=2
+pipelined=true
 
 [system.cpu0.fuPool.FUList3]
 type=FUDesc
@@ -351,9 +350,9 @@ opList=system.cpu0.fuPool.FUList3.opList
 [system.cpu0.fuPool.FUList3.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=2
+pipelined=true
 
 [system.cpu0.fuPool.FUList4]
 type=FUDesc
@@ -365,184 +364,184 @@ opList=system.cpu0.fuPool.FUList4.opList00 system.cpu0.fuPool.FUList4.opList01 s
 [system.cpu0.fuPool.FUList4.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=4
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=4
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=4
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=4
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=3
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=3
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=5
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=5
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=3
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=3
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=9
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=5
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=3
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=3
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=3
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=3
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=3
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=9
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList20]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList21]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=5
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList22]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=5
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList23]
 type=OpDesc
 eventq_index=0
-issueLat=9
 opClass=FloatDiv
 opLat=9
+pipelined=false
 
 [system.cpu0.fuPool.FUList4.opList24]
 type=OpDesc
 eventq_index=0
-issueLat=33
 opClass=FloatSqrt
 opLat=33
+pipelined=false
 
 [system.cpu0.fuPool.FUList4.opList25]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu0.icache]
 type=BaseCache
@@ -554,7 +553,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=1
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=2
 prefetch_on_access=false
@@ -565,7 +564,6 @@ size=32768
 system=system
 tags=system.cpu0.icache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.cpu0.toL2Bus.slave[0]
@@ -665,7 +663,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=12
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=16
 prefetch_on_access=true
@@ -676,7 +674,6 @@ size=1048576
 system=system
 tags=system.cpu0.l2cache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.toL2Bus.master[0]
 mem_side=system.toL2Bus.slave[0]
@@ -849,7 +846,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=6
 prefetch_on_access=false
@@ -860,7 +857,6 @@ size=32768
 system=system
 tags=system.cpu1.dcache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=16
 cpu_side=system.cpu1.dcache_port
 mem_side=system.cpu1.toL2Bus.slave[1]
@@ -932,9 +928,9 @@ opList=system.cpu1.fuPool.FUList0.opList
 [system.cpu1.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList1]
 type=FUDesc
@@ -946,23 +942,23 @@ opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 sys
 [system.cpu1.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu1.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=IntDiv
 opLat=12
+pipelined=false
 
 [system.cpu1.fuPool.FUList1.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IprAccess
 opLat=3
+pipelined=true
 
 [system.cpu1.fuPool.FUList2]
 type=FUDesc
@@ -974,9 +970,9 @@ opList=system.cpu1.fuPool.FUList2.opList
 [system.cpu1.fuPool.FUList2.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=2
+pipelined=true
 
 [system.cpu1.fuPool.FUList3]
 type=FUDesc
@@ -988,9 +984,9 @@ opList=system.cpu1.fuPool.FUList3.opList
 [system.cpu1.fuPool.FUList3.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=2
+pipelined=true
 
 [system.cpu1.fuPool.FUList4]
 type=FUDesc
@@ -1002,184 +998,184 @@ opList=system.cpu1.fuPool.FUList4.opList00 system.cpu1.fuPool.FUList4.opList01 s
 [system.cpu1.fuPool.FUList4.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=4
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=4
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=4
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=4
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=3
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=3
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=5
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=5
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=3
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=3
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=9
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=5
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=3
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=3
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=3
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=3
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=3
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=9
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList20]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList21]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=5
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList22]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=5
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList23]
 type=OpDesc
 eventq_index=0
-issueLat=9
 opClass=FloatDiv
 opLat=9
+pipelined=false
 
 [system.cpu1.fuPool.FUList4.opList24]
 type=OpDesc
 eventq_index=0
-issueLat=33
 opClass=FloatSqrt
 opLat=33
+pipelined=false
 
 [system.cpu1.fuPool.FUList4.opList25]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu1.icache]
 type=BaseCache
@@ -1191,7 +1187,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=1
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=2
 prefetch_on_access=false
@@ -1202,7 +1198,6 @@ size=32768
 system=system
 tags=system.cpu1.icache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.icache_port
 mem_side=system.cpu1.toL2Bus.slave[0]
@@ -1302,7 +1297,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=12
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=16
 prefetch_on_access=true
@@ -1313,7 +1308,6 @@ size=1048576
 system=system
 tags=system.cpu1.l2cache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.toL2Bus.master[0]
 mem_side=system.toL2Bus.slave[1]
@@ -1416,7 +1410,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -1427,7 +1421,6 @@ size=1024
 system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[27]
 mem_side=system.membus.slave[3]
@@ -1452,7 +1445,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -1463,7 +1456,6 @@ size=4194304
 system=system
 tags=system.l2c.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
@@ -1831,7 +1823,8 @@ pio=system.iobus.master[25]
 type=GenericTimer
 eventq_index=0
 gic=system.realview.gic
-int_num=29
+int_phys=29
+int_virt=27
 system=system
 
 [system.realview.gic]
@@ -1861,6 +1854,7 @@ pio_latency=10000
 pixel_clock=7299
 system=system
 vnc=system.vncserver
+workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
 
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini
index 852c1bc63..2c9a47114 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini
@@ -12,25 +12,23 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm64
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-boot_release_addr=65528
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
 flags_addr=469827632
 gic_cpu_addr=738205696
-have_generic_timer=false
 have_large_asid_64=false
 have_lpae=false
 have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch64.20140821
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -44,7 +42,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -87,7 +85,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/home/stever/m5/aarch-system-2014-10/disks/linaro-minimal-aarch64.img
+image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
 read_only=true
 
 [system.clk_domain]
@@ -212,7 +210,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -223,7 +221,6 @@ size=32768
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -295,9 +292,9 @@ opList=system.cpu.fuPool.FUList0.opList
 [system.cpu.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList1]
 type=FUDesc
@@ -309,23 +306,23 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 syste
 [system.cpu.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=IntDiv
 opLat=12
+pipelined=false
 
 [system.cpu.fuPool.FUList1.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IprAccess
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList2]
 type=FUDesc
@@ -337,9 +334,9 @@ opList=system.cpu.fuPool.FUList2.opList
 [system.cpu.fuPool.FUList2.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList3]
 type=FUDesc
@@ -351,9 +348,9 @@ opList=system.cpu.fuPool.FUList3.opList
 [system.cpu.fuPool.FUList3.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList4]
 type=FUDesc
@@ -365,184 +362,184 @@ opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 sys
 [system.cpu.fuPool.FUList4.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=9
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=9
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList20]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList21]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList22]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList23]
 type=OpDesc
 eventq_index=0
-issueLat=9
 opClass=FloatDiv
 opLat=9
+pipelined=false
 
 [system.cpu.fuPool.FUList4.opList24]
 type=OpDesc
 eventq_index=0
-issueLat=33
 opClass=FloatSqrt
 opLat=33
+pipelined=false
 
 [system.cpu.fuPool.FUList4.opList25]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu.icache]
 type=BaseCache
@@ -554,7 +551,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -565,7 +562,6 @@ size=32768
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -665,7 +661,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -676,7 +672,6 @@ size=4194304
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
@@ -754,7 +749,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -765,7 +760,6 @@ size=1024
 system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[27]
 mem_side=system.membus.slave[3]
@@ -1133,7 +1127,8 @@ pio=system.iobus.master[25]
 type=GenericTimer
 eventq_index=0
 gic=system.realview.gic
-int_num=29
+int_phys=29
+int_virt=27
 system=system
 
 [system.realview.gic]
@@ -1163,6 +1158,7 @@ pio_latency=10000
 pixel_clock=7299
 system=system
 vnc=system.vncserver
+workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
 
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.ini
index e9cf6e0ce..c1a5b024a 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.ini
@@ -146,7 +146,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -157,7 +157,6 @@ size=32768
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -223,7 +222,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -234,7 +233,6 @@ size=32768
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -334,7 +332,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -345,7 +343,6 @@ size=4194304
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
@@ -423,7 +420,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -434,7 +431,6 @@ size=1024
 system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[27]
 mem_side=system.membus.slave[3]
@@ -769,6 +765,7 @@ pio_latency=10000
 pixel_clock=7299
 system=system
 vnc=system.vncserver
+workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
 
@@ -1156,7 +1153,6 @@ port=3456
 
 [system.vncserver]
 type=VncServer
-capture_exit_frame=-1
 eventq_index=0
 frame_capture=false
 number=0
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini
index 6a2ebe226..d35c4ce4c 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini
@@ -14,7 +14,6 @@ children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl io
 atags_addr=134217728
 boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-boot_release_addr=65528
 cache_line_size=64
 clk_domain=system.clk_domain
 dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
@@ -23,7 +22,6 @@ enable_context_switch_stats_dump=false
 eventq_index=0
 flags_addr=469827632
 gic_cpu_addr=738205696
-have_generic_timer=false
 have_large_asid_64=false
 have_lpae=false
 have_security=false
@@ -147,7 +145,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=6
 prefetch_on_access=false
@@ -158,7 +156,6 @@ size=32768
 system=system
 tags=system.cpu0.dcache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=16
 cpu_side=system.cpu0.dcache_port
 mem_side=system.cpu0.toL2Bus.slave[1]
@@ -222,9 +219,9 @@ assoc=2
 clk_domain=system.cpu_clk_domain
 demand_mshr_reserve=1
 eventq_index=0
-forward_snoops=true
+forward_snoops=false
 hit_latency=1
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=2
 prefetch_on_access=false
@@ -235,7 +232,6 @@ size=32768
 system=system
 tags=system.cpu0.icache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.cpu0.toL2Bus.slave[0]
@@ -335,7 +331,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=12
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=16
 prefetch_on_access=true
@@ -346,7 +342,6 @@ size=1048576
 system=system
 tags=system.cpu0.l2cache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.toL2Bus.master[0]
 mem_side=system.toL2Bus.slave[0]
@@ -454,7 +449,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=6
 prefetch_on_access=false
@@ -465,7 +460,6 @@ size=32768
 system=system
 tags=system.cpu1.dcache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=16
 cpu_side=system.cpu1.dcache_port
 mem_side=system.cpu1.toL2Bus.slave[1]
@@ -529,9 +523,9 @@ assoc=2
 clk_domain=system.cpu_clk_domain
 demand_mshr_reserve=1
 eventq_index=0
-forward_snoops=true
+forward_snoops=false
 hit_latency=1
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=2
 prefetch_on_access=false
@@ -542,7 +536,6 @@ size=32768
 system=system
 tags=system.cpu1.icache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.icache_port
 mem_side=system.cpu1.toL2Bus.slave[0]
@@ -642,7 +635,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=12
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=16
 prefetch_on_access=true
@@ -653,7 +646,6 @@ size=1048576
 system=system
 tags=system.cpu1.l2cache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.toL2Bus.master[0]
 mem_side=system.toL2Bus.slave[1]
@@ -756,7 +748,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -767,7 +759,6 @@ size=1024
 system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[27]
 mem_side=system.membus.slave[3]
@@ -792,7 +783,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -803,7 +794,6 @@ size=4194304
 system=system
 tags=system.l2c.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
@@ -832,7 +822,7 @@ system=system
 use_default_range=false
 width=16
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
 slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
 
 [system.membus.badaddr_responder]
@@ -1107,7 +1097,8 @@ pio=system.iobus.master[25]
 type=GenericTimer
 eventq_index=0
 gic=system.realview.gic
-int_num=29
+int_phys=29
+int_virt=27
 system=system
 
 [system.realview.gic]
@@ -1120,7 +1111,6 @@ dist_pio_delay=10000
 eventq_index=0
 int_latency=10000
 it_lines=128
-msix_addr=0
 platform=system.realview
 system=system
 pio=system.membus.master[2]
@@ -1138,6 +1128,7 @@ pio_latency=10000
 pixel_clock=7299
 system=system
 vnc=system.vncserver
+workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
 
@@ -1307,7 +1298,7 @@ int_num_watchdog=30
 pio_addr=738721792
 pio_latency=100000
 system=system
-pio=system.membus.master[3]
+pio=system.membus.master[4]
 
 [system.realview.mmc_fake]
 type=AmbaFake
@@ -1489,7 +1480,7 @@ platform=system.realview
 ppint=25
 system=system
 vcpu_addr=738222080
-pio=system.membus.master[4]
+pio=system.membus.master[3]
 
 [system.realview.vram]
 type=SimpleMemory
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini
index f454bf736..b6cf1914a 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini
@@ -14,7 +14,6 @@ children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus io
 atags_addr=134217728
 boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-boot_release_addr=65528
 cache_line_size=64
 clk_domain=system.clk_domain
 dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
@@ -23,7 +22,6 @@ enable_context_switch_stats_dump=false
 eventq_index=0
 flags_addr=469827632
 gic_cpu_addr=738205696
-have_generic_timer=false
 have_large_asid_64=false
 have_lpae=false
 have_security=false
@@ -147,7 +145,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -158,7 +156,6 @@ size=32768
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -224,7 +221,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -235,7 +232,6 @@ size=32768
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -335,7 +331,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -346,7 +342,6 @@ size=4194304
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
@@ -424,7 +419,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -435,7 +430,6 @@ size=1024
 system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[27]
 mem_side=system.membus.slave[3]
@@ -464,7 +458,7 @@ system=system
 use_default_range=false
 width=16
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
 slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
 
 [system.membus.badaddr_responder]
@@ -739,7 +733,8 @@ pio=system.iobus.master[25]
 type=GenericTimer
 eventq_index=0
 gic=system.realview.gic
-int_num=29
+int_phys=29
+int_virt=27
 system=system
 
 [system.realview.gic]
@@ -752,7 +747,6 @@ dist_pio_delay=10000
 eventq_index=0
 int_latency=10000
 it_lines=128
-msix_addr=0
 platform=system.realview
 system=system
 pio=system.membus.master[2]
@@ -770,6 +764,7 @@ pio_latency=10000
 pixel_clock=7299
 system=system
 vnc=system.vncserver
+workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
 
@@ -939,7 +934,7 @@ int_num_watchdog=30
 pio_addr=738721792
 pio_latency=100000
 system=system
-pio=system.membus.master[3]
+pio=system.membus.master[4]
 
 [system.realview.mmc_fake]
 type=AmbaFake
@@ -1121,7 +1116,7 @@ platform=system.realview
 ppint=25
 system=system
 vcpu_addr=738222080
-pio=system.membus.master[4]
+pio=system.membus.master[3]
 
 [system.realview.vram]
 type=SimpleMemory
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini
index 1dec8a2fa..314709801 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini
@@ -14,7 +14,6 @@ children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl io
 atags_addr=134217728
 boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-boot_release_addr=65528
 cache_line_size=64
 clk_domain=system.clk_domain
 dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
@@ -23,7 +22,6 @@ enable_context_switch_stats_dump=false
 eventq_index=0
 flags_addr=469827632
 gic_cpu_addr=738205696
-have_generic_timer=false
 have_large_asid_64=false
 have_lpae=false
 have_security=false
@@ -143,7 +141,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=6
 prefetch_on_access=false
@@ -154,7 +152,6 @@ size=32768
 system=system
 tags=system.cpu0.dcache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=16
 cpu_side=system.cpu0.dcache_port
 mem_side=system.cpu0.toL2Bus.slave[1]
@@ -218,9 +215,9 @@ assoc=2
 clk_domain=system.cpu_clk_domain
 demand_mshr_reserve=1
 eventq_index=0
-forward_snoops=true
+forward_snoops=false
 hit_latency=1
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=2
 prefetch_on_access=false
@@ -231,7 +228,6 @@ size=32768
 system=system
 tags=system.cpu0.icache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.cpu0.toL2Bus.slave[0]
@@ -331,7 +327,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=12
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=16
 prefetch_on_access=true
@@ -342,7 +338,6 @@ size=1048576
 system=system
 tags=system.cpu0.l2cache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.toL2Bus.master[0]
 mem_side=system.toL2Bus.slave[0]
@@ -446,7 +441,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=6
 prefetch_on_access=false
@@ -457,7 +452,6 @@ size=32768
 system=system
 tags=system.cpu1.dcache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=16
 cpu_side=system.cpu1.dcache_port
 mem_side=system.cpu1.toL2Bus.slave[1]
@@ -521,9 +515,9 @@ assoc=2
 clk_domain=system.cpu_clk_domain
 demand_mshr_reserve=1
 eventq_index=0
-forward_snoops=true
+forward_snoops=false
 hit_latency=1
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=2
 prefetch_on_access=false
@@ -534,7 +528,6 @@ size=32768
 system=system
 tags=system.cpu1.icache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.icache_port
 mem_side=system.cpu1.toL2Bus.slave[0]
@@ -634,7 +627,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=12
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=16
 prefetch_on_access=true
@@ -645,7 +638,6 @@ size=1048576
 system=system
 tags=system.cpu1.l2cache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.toL2Bus.master[0]
 mem_side=system.toL2Bus.slave[1]
@@ -748,7 +740,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -759,7 +751,6 @@ size=1024
 system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[27]
 mem_side=system.membus.slave[3]
@@ -784,7 +775,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -795,7 +786,6 @@ size=4194304
 system=system
 tags=system.l2c.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
@@ -824,7 +814,7 @@ system=system
 use_default_range=false
 width=16
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
 slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
 
 [system.membus.badaddr_responder]
@@ -1163,7 +1153,8 @@ pio=system.iobus.master[25]
 type=GenericTimer
 eventq_index=0
 gic=system.realview.gic
-int_num=29
+int_phys=29
+int_virt=27
 system=system
 
 [system.realview.gic]
@@ -1176,7 +1167,6 @@ dist_pio_delay=10000
 eventq_index=0
 int_latency=10000
 it_lines=128
-msix_addr=0
 platform=system.realview
 system=system
 pio=system.membus.master[2]
@@ -1194,6 +1184,7 @@ pio_latency=10000
 pixel_clock=7299
 system=system
 vnc=system.vncserver
+workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
 
@@ -1363,7 +1354,7 @@ int_num_watchdog=30
 pio_addr=738721792
 pio_latency=100000
 system=system
-pio=system.membus.master[3]
+pio=system.membus.master[4]
 
 [system.realview.mmc_fake]
 type=AmbaFake
@@ -1545,7 +1536,7 @@ platform=system.realview
 ppint=25
 system=system
 vcpu_addr=738222080
-pio=system.membus.master[4]
+pio=system.membus.master[3]
 
 [system.realview.vram]
 type=SimpleMemory
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini
index 9587f8b73..e55c12b7f 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini
@@ -14,7 +14,6 @@ children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus io
 atags_addr=134217728
 boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-boot_release_addr=65528
 cache_line_size=64
 clk_domain=system.clk_domain
 dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
@@ -23,7 +22,6 @@ enable_context_switch_stats_dump=false
 eventq_index=0
 flags_addr=469827632
 gic_cpu_addr=738205696
-have_generic_timer=false
 have_large_asid_64=false
 have_lpae=false
 have_security=false
@@ -143,7 +141,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -154,7 +152,6 @@ size=32768
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -220,7 +217,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -231,7 +228,6 @@ size=32768
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -331,7 +327,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -342,7 +338,6 @@ size=4194304
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
@@ -420,7 +415,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -431,7 +426,6 @@ size=1024
 system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[27]
 mem_side=system.membus.slave[3]
@@ -460,7 +454,7 @@ system=system
 use_default_range=false
 width=16
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
 slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
 
 [system.membus.badaddr_responder]
@@ -799,7 +793,8 @@ pio=system.iobus.master[25]
 type=GenericTimer
 eventq_index=0
 gic=system.realview.gic
-int_num=29
+int_phys=29
+int_virt=27
 system=system
 
 [system.realview.gic]
@@ -812,7 +807,6 @@ dist_pio_delay=10000
 eventq_index=0
 int_latency=10000
 it_lines=128
-msix_addr=0
 platform=system.realview
 system=system
 pio=system.membus.master[2]
@@ -830,6 +824,7 @@ pio_latency=10000
 pixel_clock=7299
 system=system
 vnc=system.vncserver
+workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
 
@@ -999,7 +994,7 @@ int_num_watchdog=30
 pio_addr=738721792
 pio_latency=100000
 system=system
-pio=system.membus.master[3]
+pio=system.membus.master[4]
 
 [system.realview.mmc_fake]
 type=AmbaFake
@@ -1181,7 +1176,7 @@ platform=system.realview
 ppint=25
 system=system
 vcpu_addr=738222080
-pio=system.membus.master[4]
+pio=system.membus.master[3]
 
 [system.realview.vram]
 type=SimpleMemory
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini
index 7b6dda94d..a9d46c0d8 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini
@@ -14,7 +14,6 @@ children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl io
 atags_addr=134217728
 boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-boot_release_addr=65528
 cache_line_size=64
 clk_domain=system.clk_domain
 dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
@@ -23,7 +22,6 @@ enable_context_switch_stats_dump=false
 eventq_index=0
 flags_addr=469827632
 gic_cpu_addr=738205696
-have_generic_timer=false
 have_large_asid_64=false
 have_lpae=false
 have_security=false
@@ -147,7 +145,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -158,7 +156,6 @@ size=32768
 system=system
 tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
@@ -224,7 +221,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -235,7 +232,6 @@ size=32768
 system=system
 tags=system.cpu0.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
@@ -524,7 +520,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -535,7 +531,6 @@ size=1024
 system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[27]
 mem_side=system.membus.slave[3]
@@ -560,7 +555,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -571,7 +566,6 @@ size=4194304
 system=system
 tags=system.l2c.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
@@ -600,7 +594,7 @@ system=system
 use_default_range=false
 width=16
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
 slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
 
 [system.membus.badaddr_responder]
@@ -875,7 +869,8 @@ pio=system.iobus.master[25]
 type=GenericTimer
 eventq_index=0
 gic=system.realview.gic
-int_num=29
+int_phys=29
+int_virt=27
 system=system
 
 [system.realview.gic]
@@ -888,7 +883,6 @@ dist_pio_delay=10000
 eventq_index=0
 int_latency=10000
 it_lines=128
-msix_addr=0
 platform=system.realview
 system=system
 pio=system.membus.master[2]
@@ -906,6 +900,7 @@ pio_latency=10000
 pixel_clock=7299
 system=system
 vnc=system.vncserver
+workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
 
@@ -1075,7 +1070,7 @@ int_num_watchdog=30
 pio_addr=738721792
 pio_latency=100000
 system=system
-pio=system.membus.master[3]
+pio=system.membus.master[4]
 
 [system.realview.mmc_fake]
 type=AmbaFake
@@ -1257,7 +1252,7 @@ platform=system.realview
 ppint=25
 system=system
 vcpu_addr=738222080
-pio=system.membus.master[4]
+pio=system.membus.master[3]
 
 [system.realview.vram]
 type=SimpleMemory
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simerr
index 3137dc2c1..e6c37927e 100644..100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simerr
@@ -568,3 +568,39 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini
index 7bee47df1..e3aa5b681 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini
@@ -147,7 +147,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -158,7 +158,6 @@ size=32768
 system=system
 tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
@@ -224,7 +223,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -235,7 +234,6 @@ size=32768
 system=system
 tags=system.cpu0.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
@@ -637,9 +635,9 @@ opList=system.cpu2.fuPool.FUList0.opList
 [system.cpu2.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList1]
 type=FUDesc
@@ -651,16 +649,16 @@ opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1
 [system.cpu2.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu2.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=19
 opClass=IntDiv
 opLat=20
+pipelined=false
 
 [system.cpu2.fuPool.FUList2]
 type=FUDesc
@@ -672,23 +670,23 @@ opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 sys
 [system.cpu2.fuPool.FUList2.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=2
+pipelined=true
 
 [system.cpu2.fuPool.FUList2.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=2
+pipelined=true
 
 [system.cpu2.fuPool.FUList2.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=2
+pipelined=true
 
 [system.cpu2.fuPool.FUList3]
 type=FUDesc
@@ -700,23 +698,23 @@ opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 sys
 [system.cpu2.fuPool.FUList3.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu2.fuPool.FUList3.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=FloatDiv
 opLat=12
+pipelined=false
 
 [system.cpu2.fuPool.FUList3.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=24
 opClass=FloatSqrt
 opLat=24
+pipelined=false
 
 [system.cpu2.fuPool.FUList4]
 type=FUDesc
@@ -728,9 +726,9 @@ opList=system.cpu2.fuPool.FUList4.opList
 [system.cpu2.fuPool.FUList4.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5]
 type=FUDesc
@@ -742,142 +740,142 @@ opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 s
 [system.cpu2.fuPool.FUList5.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList6]
 type=FUDesc
@@ -889,9 +887,9 @@ opList=system.cpu2.fuPool.FUList6.opList
 [system.cpu2.fuPool.FUList6.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList7]
 type=FUDesc
@@ -903,16 +901,16 @@ opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
 [system.cpu2.fuPool.FUList7.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList7.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList8]
 type=FUDesc
@@ -924,9 +922,9 @@ opList=system.cpu2.fuPool.FUList8.opList
 [system.cpu2.fuPool.FUList8.opList]
 type=OpDesc
 eventq_index=0
-issueLat=3
 opClass=IprAccess
 opLat=3
+pipelined=false
 
 [system.cpu2.isa]
 type=ArmISA
@@ -1046,7 +1044,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -1057,7 +1055,6 @@ size=1024
 system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[27]
 mem_side=system.membus.slave[3]
@@ -1082,7 +1079,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -1093,7 +1090,6 @@ size=4194304
 system=system
 tags=system.l2c.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
@@ -1461,7 +1457,8 @@ pio=system.iobus.master[25]
 type=GenericTimer
 eventq_index=0
 gic=system.realview.gic
-int_num=29
+int_phys=29
+int_virt=27
 system=system
 
 [system.realview.gic]
@@ -1491,6 +1488,7 @@ pio_latency=10000
 pixel_clock=7299
 system=system
 vnc=system.vncserver
+workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
 
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr
index ce311b5c7..0db002d40 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr
@@ -7,20 +7,20 @@ warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
 warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7336, Bank: 7
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
 warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7858, Bank: 6
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11898, Bank: 3
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8890, Bank: 1
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -33,6 +33,8 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9145, Bank: 4
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -43,26 +45,28 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9168, Bank: 3
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10682, Bank: 5
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10118, Bank: 1
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -81,6 +85,8 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -121,10 +127,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -161,14 +163,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -181,16 +175,14 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -219,8 +211,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -235,6 +225,8 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -245,18 +237,22 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6745, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: Bank is already active!
-Command: 0, Timestamp: 7910, Bank: 6
+Command: 0, Timestamp: 7145, Bank: 1
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -265,22 +261,12 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6501, Bank: 1
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9251, Bank: 5
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7678, Bank: 1
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6735, Bank: 1
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7557, Bank: 6
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -295,18 +281,38 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9101, Bank: 7
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9235, Bank: 3
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7617, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 8572, Bank: 2
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6448, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10110, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7448, Bank: 6
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10610, Bank: 5
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -321,8 +327,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6448, Bank: 1
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -331,22 +335,24 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 8438, Bank: 3
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: Bank is already active!
-Command: 0, Timestamp: 6448, Bank: 3
+Command: 0, Timestamp: 10259, Bank: 6
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10259, Bank: 1
 WARNING: Bank is already active!
-Command: 0, Timestamp: 6449, Bank: 1
+Command: 0, Timestamp: 10264, Bank: 4
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -357,8 +363,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11346, Bank: 6
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -367,14 +371,12 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 WARNING: Bank is already active!
-Command: 0, Timestamp: 6718, Bank: 7
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+Command: 0, Timestamp: 8662, Bank: 3
+WARNING: Bank is already active!
+Command: 0, Timestamp: 8576, Bank: 2
+WARNING: Bank is already active!
+Command: 0, Timestamp: 8938, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -389,20 +391,22 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8596, Bank: 2
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9274, Bank: 2
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -415,30 +419,32 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7950, Bank: 1
+WARNING: Bank is already active!
+Command: 0, Timestamp: 8022, Bank: 6
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6606, Bank: 1
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7878, Bank: 5
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9487, Bank: 6
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8427, Bank: 5
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7189, Bank: 3
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -452,17 +458,7 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: Bank is already active!
-Command: 0, Timestamp: 10975, Bank: 5
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11256, Bank: 2
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+Command: 0, Timestamp: 9249, Bank: 5
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -487,16 +483,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6729, Bank: 3
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 12439, Bank: 2
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -515,18 +505,16 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7135, Bank: 3
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6921, Bank: 2
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7517, Bank: 5
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -535,16 +523,20 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11967, Bank: 5
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -559,8 +551,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -573,6 +563,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -589,30 +583,12 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11356, Bank: 5
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9054, Bank: 7
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -627,16 +603,12 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6571, Bank: 6
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -657,8 +629,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -667,16 +637,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -701,14 +665,22 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10927, Bank: 6
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7539, Bank: 3
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -723,10 +695,26 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -735,6 +723,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -759,38 +751,42 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6681, Bank: 7
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7983, Bank: 5
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -807,8 +803,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7384, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -825,14 +819,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10124, Bank: 1
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -845,24 +831,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6448, Bank: 3
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6758, Bank: 2
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8359, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6936, Bank: 1
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -875,6 +847,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -891,14 +867,14 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -907,6 +883,18 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -927,6 +915,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -963,10 +955,8 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -985,10 +975,18 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -1019,6 +1017,8 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1039,6 +1039,14 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -1057,6 +1065,18 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -1073,14 +1093,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -1089,16 +1101,18 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -1117,10 +1131,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1141,6 +1151,10 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -1199,16 +1213,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1219,8 +1223,8 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8631, Bank: 7
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1229,6 +1233,10 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1245,6 +1253,8 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1257,10 +1267,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -1291,24 +1297,20 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11511, Bank: 2
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -1323,8 +1325,8 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9988, Bank: 2
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
@@ -1332,39 +1334,23 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: Bank is already active!
-Command: 0, Timestamp: 7482, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+Command: 0, Timestamp: 6448, Bank: 5
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8240, Bank: 5
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6884, Bank: 4
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7065, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: Bank is already active!
-Command: 0, Timestamp: 7992, Bank: 0
+Command: 0, Timestamp: 9255, Bank: 4
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11880, Bank: 6
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: Bank is already active!
-Command: 0, Timestamp: 6448, Bank: 6
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6861, Bank: 4
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6994, Bank: 7
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+Command: 0, Timestamp: 7102, Bank: 7
 WARNING: Bank is already active!
-Command: 0, Timestamp: 7102, Bank: 2
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+Command: 0, Timestamp: 7405, Bank: 1
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1375,12 +1361,14 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1393,24 +1381,20 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9173, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1435,10 +1419,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1457,8 +1437,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9034, Bank: 2
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1479,8 +1457,8 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10338, Bank: 2
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/config.ini
index 7721c6927..2214964bc 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/config.ini
@@ -215,7 +215,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -226,7 +226,6 @@ size=32768
 system=system
 tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
@@ -298,9 +297,9 @@ opList=system.cpu0.fuPool.FUList0.opList
 [system.cpu0.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList1]
 type=FUDesc
@@ -312,16 +311,16 @@ opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
 [system.cpu0.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu0.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=19
 opClass=IntDiv
 opLat=20
+pipelined=false
 
 [system.cpu0.fuPool.FUList2]
 type=FUDesc
@@ -333,23 +332,23 @@ opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 sys
 [system.cpu0.fuPool.FUList2.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=2
+pipelined=true
 
 [system.cpu0.fuPool.FUList2.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=2
+pipelined=true
 
 [system.cpu0.fuPool.FUList2.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=2
+pipelined=true
 
 [system.cpu0.fuPool.FUList3]
 type=FUDesc
@@ -361,23 +360,23 @@ opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 sys
 [system.cpu0.fuPool.FUList3.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu0.fuPool.FUList3.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=FloatDiv
 opLat=12
+pipelined=false
 
 [system.cpu0.fuPool.FUList3.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=24
 opClass=FloatSqrt
 opLat=24
+pipelined=false
 
 [system.cpu0.fuPool.FUList4]
 type=FUDesc
@@ -389,9 +388,9 @@ opList=system.cpu0.fuPool.FUList4.opList
 [system.cpu0.fuPool.FUList4.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5]
 type=FUDesc
@@ -403,142 +402,142 @@ opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 s
 [system.cpu0.fuPool.FUList5.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList6]
 type=FUDesc
@@ -550,9 +549,9 @@ opList=system.cpu0.fuPool.FUList6.opList
 [system.cpu0.fuPool.FUList6.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList7]
 type=FUDesc
@@ -564,16 +563,16 @@ opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1
 [system.cpu0.fuPool.FUList7.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList7.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList8]
 type=FUDesc
@@ -585,9 +584,9 @@ opList=system.cpu0.fuPool.FUList8.opList
 [system.cpu0.fuPool.FUList8.opList]
 type=OpDesc
 eventq_index=0
-issueLat=3
 opClass=IprAccess
 opLat=3
+pipelined=false
 
 [system.cpu0.icache]
 type=BaseCache
@@ -599,7 +598,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -610,7 +609,6 @@ size=32768
 system=system
 tags=system.cpu0.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
@@ -865,9 +863,9 @@ opList=system.cpu1.fuPool.FUList0.opList
 [system.cpu1.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList1]
 type=FUDesc
@@ -879,16 +877,16 @@ opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1
 [system.cpu1.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu1.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=19
 opClass=IntDiv
 opLat=20
+pipelined=false
 
 [system.cpu1.fuPool.FUList2]
 type=FUDesc
@@ -900,23 +898,23 @@ opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 sys
 [system.cpu1.fuPool.FUList2.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=2
+pipelined=true
 
 [system.cpu1.fuPool.FUList2.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=2
+pipelined=true
 
 [system.cpu1.fuPool.FUList2.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=2
+pipelined=true
 
 [system.cpu1.fuPool.FUList3]
 type=FUDesc
@@ -928,23 +926,23 @@ opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 sys
 [system.cpu1.fuPool.FUList3.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu1.fuPool.FUList3.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=FloatDiv
 opLat=12
+pipelined=false
 
 [system.cpu1.fuPool.FUList3.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=24
 opClass=FloatSqrt
 opLat=24
+pipelined=false
 
 [system.cpu1.fuPool.FUList4]
 type=FUDesc
@@ -956,9 +954,9 @@ opList=system.cpu1.fuPool.FUList4.opList
 [system.cpu1.fuPool.FUList4.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5]
 type=FUDesc
@@ -970,142 +968,142 @@ opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 s
 [system.cpu1.fuPool.FUList5.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList6]
 type=FUDesc
@@ -1117,9 +1115,9 @@ opList=system.cpu1.fuPool.FUList6.opList
 [system.cpu1.fuPool.FUList6.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList7]
 type=FUDesc
@@ -1131,16 +1129,16 @@ opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1
 [system.cpu1.fuPool.FUList7.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList7.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList8]
 type=FUDesc
@@ -1152,9 +1150,9 @@ opList=system.cpu1.fuPool.FUList8.opList
 [system.cpu1.fuPool.FUList8.opList]
 type=OpDesc
 eventq_index=0
-issueLat=3
 opClass=IprAccess
 opLat=3
+pipelined=false
 
 [system.cpu1.isa]
 type=ArmISA
@@ -1274,7 +1272,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -1285,7 +1283,6 @@ size=1024
 system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[27]
 mem_side=system.membus.slave[3]
@@ -1310,7 +1307,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -1321,7 +1318,6 @@ size=4194304
 system=system
 tags=system.l2c.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
@@ -1689,7 +1685,8 @@ pio=system.iobus.master[25]
 type=GenericTimer
 eventq_index=0
 gic=system.realview.gic
-int_num=29
+int_phys=29
+int_virt=27
 system=system
 
 [system.realview.gic]
@@ -1719,6 +1716,7 @@ pio_latency=10000
 pixel_clock=7299
 system=system
 vnc=system.vncserver
+workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
 
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simerr
index 68af87dfe..4d4e040d3 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simerr
@@ -433,3 +433,67 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini
index 6cf886297..5a83a4136 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini
@@ -12,38 +12,37 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-boot_release_addr=65528
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
 flags_addr=469827632
 gic_cpu_addr=738205696
-have_generic_timer=false
 have_large_asid_64=false
 have_lpae=false
 have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
 machine_type=VExpress_EMM64
 mem_mode=timing
 mem_ranges=2147483648:2415919103
-memories=system.realview.nvmem system.physmem system.realview.vram
+memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
 multi_proc=true
 num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5.latest/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -86,7 +85,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img
+image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
 read_only=true
 
 [system.clk_domain]
@@ -138,10 +137,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -152,7 +152,6 @@ size=32768
 system=system
 tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
@@ -172,6 +171,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu0.dtb
 
 [system.cpu0.dstage2_mmu.stage2_tlb]
@@ -189,7 +189,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.toL2Bus.slave[5]
 
 [system.cpu0.dtb]
 type=ArmTLB
@@ -214,10 +213,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -228,7 +228,6 @@ size=32768
 system=system
 tags=system.cpu0.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
@@ -282,6 +281,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu0.itb
 
 [system.cpu0.istage2_mmu.stage2_tlb]
@@ -299,7 +299,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.toL2Bus.slave[4]
 
 [system.cpu0.itb]
 type=ArmTLB
@@ -360,6 +359,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu1.dtb
 
 [system.cpu1.dstage2_mmu.stage2_tlb]
@@ -429,6 +429,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu1.itb
 
 [system.cpu1.istage2_mmu.stage2_tlb]
@@ -492,9 +493,11 @@ sys=system
 type=NoncoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
 use_default_range=true
-width=8
+width=16
 default=system.realview.pciconfig.pio
 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
@@ -505,10 +508,11 @@ children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
 clk_domain=system.clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -519,7 +523,6 @@ size=1024
 system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[27]
 mem_side=system.membus.slave[3]
@@ -540,10 +543,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -554,7 +558,6 @@ size=4194304
 system=system
 tags=system.l2c.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
@@ -574,13 +577,16 @@ type=CoherentXBar
 children=badaddr_responder
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
 slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
 
 [system.membus.badaddr_responder]
@@ -628,7 +634,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -919,7 +925,8 @@ pio=system.iobus.master[25]
 type=GenericTimer
 eventq_index=0
 gic=system.realview.gic
-int_num=29
+int_phys=29
+int_virt=27
 system=system
 
 [system.realview.gic]
@@ -932,7 +939,6 @@ dist_pio_delay=10000
 eventq_index=0
 int_latency=10000
 it_lines=128
-msix_addr=0
 platform=system.realview
 system=system
 pio=system.membus.master[2]
@@ -950,6 +956,7 @@ pio_latency=10000
 pixel_clock=7299
 system=system
 vnc=system.vncserver
+workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
 
@@ -1119,7 +1126,7 @@ int_num_watchdog=30
 pio_addr=738721792
 pio_latency=100000
 system=system
-pio=system.membus.master[3]
+pio=system.membus.master[4]
 
 [system.realview.mmc_fake]
 type=AmbaFake
@@ -1301,7 +1308,7 @@ platform=system.realview
 ppint=25
 system=system
 vcpu_addr=738222080
-pio=system.membus.master[4]
+pio=system.membus.master[3]
 
 [system.realview.vram]
 type=SimpleMemory
@@ -1339,13 +1346,16 @@ port=3456
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
-width=8
+width=32
 master=system.l2c.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
 
 [system.vncserver]
 type=VncServer
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simerr
index 35422844e..bc8b17326 100644..100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simerr
@@ -1533,215 +1533,3 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini
index 2f7786e68..6bbe8c080 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini
@@ -27,6 +27,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=0:134217727
 memories=system.mem_ctrls
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 smbios_table=system.smbios_table
@@ -701,9 +702,11 @@ sys=system
 type=NoncoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
 use_default_range=false
-width=8
+width=16
 default=system.pc.pciconfig.pio
 master=system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.ruby.l1_cntrl0.sequencer.pio_slave_port system.ruby.l1_cntrl1.sequencer.pio_slave_port system.ruby.io_controller.dma_sequencer.slave
 slave=system.pc.south_bridge.io_apic.int_master system.ruby.l1_cntrl0.sequencer.pio_master_port system.ruby.l1_cntrl0.sequencer.mem_master_port system.ruby.l1_cntrl1.sequencer.pio_master_port system.ruby.l1_cntrl1.sequencer.mem_master_port
@@ -735,7 +738,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -1314,6 +1317,7 @@ pio=system.iobus.master[8]
 [system.ruby]
 type=RubySystem
 children=clk_domain dir_cntrl0 dma_cntrl0 io_controller l1_cntrl0 l1_cntrl1 l2_cntrl0 memctrl_clk_domain network
+access_backing_store=false
 all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
@@ -1490,7 +1494,6 @@ unit_filter=8
 
 [system.ruby.l1_cntrl0.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl0.L1Dcache
 deadlock_threshold=500000
@@ -1583,7 +1586,6 @@ unit_filter=8
 
 [system.ruby.l1_cntrl1.sequencer]
 type=RubySequencer
-access_backing_store=false
 clk_domain=system.cpu_clk_domain
 dcache=system.ruby.l1_cntrl1.L1Dcache
 deadlock_threshold=500000
@@ -1861,7 +1863,6 @@ version=
 
 [system.sys_port_proxy]
 type=RubyPortProxy
-access_backing_store=false
 clk_domain=system.clk_domain
 eventq_index=0
 ruby_system=system.ruby
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt
index 7d82f190a..221f5a4a8 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  5.305855                       # Nu
 sim_ticks                                5305855051000                       # Number of ticks simulated
 final_tick                               5305855051000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 186796                       # Simulator instruction rate (inst/s)
-host_op_rate                                   357991                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             9246678170                       # Simulator tick rate (ticks/s)
-host_mem_usage                                1105624                       # Number of bytes of host memory used
-host_seconds                                   573.81                       # Real time elapsed on the host
+host_inst_rate                                 136389                       # Simulator instruction rate (inst/s)
+host_op_rate                                   261386                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6751430632                       # Simulator tick rate (ticks/s)
+host_mem_usage                                1106140                       # Number of bytes of host memory used
+host_seconds                                   785.89                       # Real time elapsed on the host
 sim_insts                                   107186053                       # Number of instructions simulated
 sim_ops                                     205419480                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -566,9 +566,9 @@ system.ruby.clk_domain.clock                      500                       # Cl
 system.ruby.delayHist::bucket_size                  4                       # delay histogram for all message
 system.ruby.delayHist::max_bucket                  39                       # delay histogram for all message
 system.ruby.delayHist::samples               10891010                       # delay histogram for all message
-system.ruby.delayHist::mean                  0.442869                       # delay histogram for all message
-system.ruby.delayHist::stdev                 1.830823                       # delay histogram for all message
-system.ruby.delayHist                    |    10288616     94.47%     94.47% |        1282      0.01%     94.48% |      600649      5.52%    100.00% |         161      0.00%    100.00% |         257      0.00%    100.00% |          11      0.00%    100.00% |          34      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
+system.ruby.delayHist::mean                  0.442804                       # delay histogram for all message
+system.ruby.delayHist::stdev                 1.830720                       # delay histogram for all message
+system.ruby.delayHist                    |    10288683     94.47%     94.47% |        1238      0.01%     94.48% |      600635      5.51%    100.00% |         152      0.00%    100.00% |         257      0.00%    100.00% |          11      0.00%    100.00% |          34      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
 system.ruby.delayHist::total                 10891010                       # delay histogram for all message
 system.ruby.outstanding_req_hist::bucket_size            1                      
 system.ruby.outstanding_req_hist::max_bucket            9                      
@@ -880,9 +880,9 @@ system.ruby.network.routers6.throttle5.link_utilization            0
 system.ruby.delayVCHist.vnet_0::bucket_size            4                       # delay histogram for vnet_0
 system.ruby.delayVCHist.vnet_0::max_bucket           39                       # delay histogram for vnet_0
 system.ruby.delayVCHist.vnet_0::samples       6109475                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::mean         0.754420                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::stdev        2.340404                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0           |     5533989     90.58%     90.58% |         406      0.01%     90.59% |      574630      9.41%     99.99% |         158      0.00%    100.00% |         247      0.00%    100.00% |          11      0.00%    100.00% |          34      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::mean         0.754304                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::stdev        2.340275                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0           |     5534056     90.58%     90.58% |         362      0.01%     90.59% |      574616      9.41%     99.99% |         149      0.00%    100.00% |         247      0.00%    100.00% |          11      0.00%    100.00% |          34      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_0
 system.ruby.delayVCHist.vnet_0::total         6109475                       # delay histogram for vnet_0
 system.ruby.delayVCHist.vnet_1::bucket_size            2                       # delay histogram for vnet_1
 system.ruby.delayVCHist.vnet_1::max_bucket           19                       # delay histogram for vnet_1
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/system.pc.com_1.terminal
index 7f41384e2..e30654628 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/system.pc.com_1.terminal
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/system.pc.com_1.terminal
@@ -41,9 +41,10 @@ Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
 Mount-cache hash table entries: 256
 CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
 CPU: L2 Cache: 1024K (64 bytes/line)
+using mwait in idle threads.
 Freeing SMP alternatives: 34k freed
 Using local APIC timer interrupts.
-result 7812509
+result 7812512
 Detected 7.812 MHz APIC timer.
 Booting processor 1/2 APIC 0x1
 Initializing CPU#1
@@ -131,8 +132,8 @@ TCP cubic registered
 NET: Registered protocol family 1
 NET: Registered protocol family 10
 IPv6 over IPv4 tunneling driver
-NET: Registered protocol family 17
 input: PS/2 Generic Mouse as /class/input/input1
+NET: Registered protocol family 17
 EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended
 VFS: Mounted root (ext2 filesystem).
 Freeing unused kernel memory: 248k freed
diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
index 12828101a..dbb2a30b4 100644
--- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
+++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
@@ -27,7 +27,8 @@ load_addr_mask=1099511627775
 load_offset=0
 mem_mode=atomic
 mem_ranges=1048576:68157439 2147483648:2415919103
-memories=system.nvram system.physmem1 system.hypervisor_desc system.partition_desc system.physmem0 system.rom
+memories=system.hypervisor_desc system.nvram system.partition_desc system.physmem0 system.physmem1 system.rom
+mmap_using_noreserve=false
 num_work_ids=16
 nvram=system.nvram
 nvram_addr=133429198848
@@ -193,9 +194,11 @@ sys=system
 type=NoncoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
 use_default_range=false
-width=8
+width=16
 master=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.disk0.pio
 slave=system.bridge.master
 
@@ -204,11 +207,14 @@ type=CoherentXBar
 children=badaddr_responder
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 default=system.membus.badaddr_responder.pio
 master=system.t1000.iob.pio system.t1000.htod.pio system.bridge.slave system.rom.port system.nvram.port system.hypervisor_desc.port system.partition_desc.port system.physmem0.port system.physmem1.port
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini
index cdddacd16..3938653f4 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini
@@ -111,7 +111,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
 BTBEntries=4096
 BTBTagSize=16
 RASSize=16
@@ -125,7 +125,6 @@ localCtrBits=2
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
-predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
@@ -137,7 +136,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -148,7 +147,6 @@ size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -597,7 +595,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -608,7 +606,6 @@ size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -708,7 +705,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -719,7 +716,6 @@ size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
@@ -763,9 +759,9 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
 gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 kvmInSE=false
 max_stack_size=67108864
 output=cout
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
index 698e8108f..a092bf499 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
@@ -158,7 +158,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=6
 prefetch_on_access=false
@@ -169,7 +169,6 @@ size=32768
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=16
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -241,9 +240,9 @@ opList=system.cpu.fuPool.FUList0.opList
 [system.cpu.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList1]
 type=FUDesc
@@ -255,23 +254,23 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 syste
 [system.cpu.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=IntDiv
 opLat=12
+pipelined=false
 
 [system.cpu.fuPool.FUList1.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IprAccess
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList2]
 type=FUDesc
@@ -283,9 +282,9 @@ opList=system.cpu.fuPool.FUList2.opList
 [system.cpu.fuPool.FUList2.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList3]
 type=FUDesc
@@ -297,9 +296,9 @@ opList=system.cpu.fuPool.FUList3.opList
 [system.cpu.fuPool.FUList3.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList4]
 type=FUDesc
@@ -311,184 +310,184 @@ opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 sys
 [system.cpu.fuPool.FUList4.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=9
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=9
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList20]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList21]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList22]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList23]
 type=OpDesc
 eventq_index=0
-issueLat=9
 opClass=FloatDiv
 opLat=9
+pipelined=false
 
 [system.cpu.fuPool.FUList4.opList24]
 type=OpDesc
 eventq_index=0
-issueLat=33
 opClass=FloatSqrt
 opLat=33
+pipelined=false
 
 [system.cpu.fuPool.FUList4.opList25]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu.icache]
 type=BaseCache
@@ -500,7 +499,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=1
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=2
 prefetch_on_access=false
@@ -511,7 +510,6 @@ size=32768
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -611,7 +609,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=12
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=16
 prefetch_on_access=true
@@ -622,7 +620,6 @@ size=1048576
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
index e9a50bebb..263d31358 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -82,10 +83,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -96,7 +98,6 @@ size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -122,10 +123,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -136,7 +138,6 @@ size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -170,10 +171,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -184,7 +186,6 @@ size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
@@ -203,8 +204,11 @@ size=2097152
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
@@ -219,6 +223,7 @@ eventq_index=0
 type=LiveProcess
 cmd=mcf mcf.in
 cwd=build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
+drivers=
 egid=100
 env=
 errout=cerr
@@ -227,6 +232,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/mcf
 gid=100
 input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -256,11 +262,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini
index 956669942..9aa92cf18 100644
--- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -108,7 +109,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
 BTBEntries=4096
 BTBTagSize=16
 RASSize=16
@@ -122,7 +123,6 @@ localCtrBits=2
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
-predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
@@ -130,10 +130,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -144,7 +145,6 @@ size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -553,10 +553,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -567,7 +568,6 @@ size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -602,10 +602,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -616,7 +617,6 @@ size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
@@ -635,8 +635,11 @@ size=2097152
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
@@ -651,6 +654,7 @@ eventq_index=0
 type=LiveProcess
 cmd=parser 2.1.dict -batch
 cwd=build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-timing
+drivers=
 egid=100
 env=
 errout=cerr
@@ -659,6 +663,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/parser
 gid=100
 input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -688,11 +693,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
@@ -723,7 +731,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -732,6 +740,7 @@ clk_domain=system.clk_domain
 conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
+device_size=536870912
 devices_per_rank=8
 dll=true
 eventq_index=0
diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini
index e9edac26f..482664dec 100644
--- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini
@@ -111,7 +111,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
 BTBEntries=4096
 BTBTagSize=16
 RASSize=16
@@ -125,7 +125,6 @@ localCtrBits=2
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
-predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
@@ -137,7 +136,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -148,7 +147,6 @@ size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -597,7 +595,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -608,7 +606,6 @@ size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -708,7 +705,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -719,7 +716,6 @@ size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
index 845c48f32..8909daba1 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
@@ -158,7 +158,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=6
 prefetch_on_access=false
@@ -169,7 +169,6 @@ size=32768
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=16
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -241,9 +240,9 @@ opList=system.cpu.fuPool.FUList0.opList
 [system.cpu.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList1]
 type=FUDesc
@@ -255,23 +254,23 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 syste
 [system.cpu.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=IntDiv
 opLat=12
+pipelined=false
 
 [system.cpu.fuPool.FUList1.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IprAccess
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList2]
 type=FUDesc
@@ -283,9 +282,9 @@ opList=system.cpu.fuPool.FUList2.opList
 [system.cpu.fuPool.FUList2.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList3]
 type=FUDesc
@@ -297,9 +296,9 @@ opList=system.cpu.fuPool.FUList3.opList
 [system.cpu.fuPool.FUList3.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList4]
 type=FUDesc
@@ -311,184 +310,184 @@ opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 sys
 [system.cpu.fuPool.FUList4.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=9
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=9
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList20]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList21]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList22]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList23]
 type=OpDesc
 eventq_index=0
-issueLat=9
 opClass=FloatDiv
 opLat=9
+pipelined=false
 
 [system.cpu.fuPool.FUList4.opList24]
 type=OpDesc
 eventq_index=0
-issueLat=33
 opClass=FloatSqrt
 opLat=33
+pipelined=false
 
 [system.cpu.fuPool.FUList4.opList25]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu.icache]
 type=BaseCache
@@ -500,7 +499,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=1
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=2
 prefetch_on_access=false
@@ -511,7 +510,6 @@ size=32768
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -611,7 +609,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=12
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=16
 prefetch_on_access=true
@@ -622,7 +620,6 @@ size=1048576
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
index 0288139dc..8010a167e 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=atomic
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -87,6 +88,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.dtb
 
 [system.cpu.dstage2_mmu.stage2_tlb]
@@ -104,7 +106,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.membus.slave[6]
 
 [system.cpu.dtb]
 type=ArmTLB
@@ -154,6 +155,7 @@ id_mmfr3=34611729
 id_pfr0=49
 id_pfr1=4113
 midr=1091551472
+pmu=Null
 system=system
 
 [system.cpu.istage2_mmu]
@@ -161,6 +163,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.itb
 
 [system.cpu.istage2_mmu.stage2_tlb]
@@ -178,7 +181,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.membus.slave[5]
 
 [system.cpu.itb]
 type=ArmTLB
@@ -205,6 +207,7 @@ eventq_index=0
 type=LiveProcess
 cmd=parser 2.1.dict -batch
 cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic
+drivers=
 egid=100
 env=
 errout=cerr
@@ -213,6 +216,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
 gid=100
 input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -242,13 +246,16 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
-slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.physmem]
 type=SimpleMemory
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
index abc8be573..0b92236c6 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -84,10 +85,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -98,7 +100,6 @@ size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -118,6 +119,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.dtb
 
 [system.cpu.dstage2_mmu.stage2_tlb]
@@ -135,7 +137,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu.toL2Bus.slave[5]
 
 [system.cpu.dtb]
 type=ArmTLB
@@ -160,10 +161,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -174,7 +176,6 @@ size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -220,6 +221,7 @@ id_mmfr3=34611729
 id_pfr0=49
 id_pfr1=4113
 midr=1091551472
+pmu=Null
 system=system
 
 [system.cpu.istage2_mmu]
@@ -227,6 +229,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.itb
 
 [system.cpu.istage2_mmu.stage2_tlb]
@@ -244,7 +247,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu.toL2Bus.slave[4]
 
 [system.cpu.itb]
 type=ArmTLB
@@ -269,10 +271,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -283,7 +286,6 @@ size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
@@ -302,13 +304,16 @@ size=2097152
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -318,6 +323,7 @@ eventq_index=0
 type=LiveProcess
 cmd=parser 2.1.dict -batch
 cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing
+drivers=
 egid=100
 env=
 errout=cerr
@@ -326,6 +332,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
 gid=100
 input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -355,11 +362,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini
index f0acfeb88..607fa4fde 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -108,7 +109,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
 BTBEntries=4096
 BTBTagSize=16
 RASSize=16
@@ -122,7 +123,6 @@ localCtrBits=2
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
-predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
@@ -130,10 +130,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -144,7 +145,6 @@ size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -553,10 +553,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -567,7 +568,6 @@ size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -602,10 +602,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -616,7 +617,6 @@ size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
@@ -635,8 +635,11 @@ size=2097152
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
@@ -651,6 +654,7 @@ eventq_index=0
 type=LiveProcess
 cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
 cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing
+drivers=
 egid=100
 env=
 errout=cerr
@@ -659,6 +663,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -688,11 +693,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
@@ -723,7 +731,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -732,6 +740,7 @@ clk_domain=system.clk_domain
 conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
+device_size=536870912
 devices_per_rank=8
 dll=true
 eventq_index=0
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
index b858d7bf1..b0756d2d6 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
@@ -159,7 +159,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -170,7 +170,6 @@ size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -206,9 +205,9 @@ opList=system.cpu.fuPool.FUList0.opList
 [system.cpu.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList1]
 type=FUDesc
@@ -220,16 +219,16 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 [system.cpu.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=19
 opClass=IntDiv
 opLat=20
+pipelined=false
 
 [system.cpu.fuPool.FUList2]
 type=FUDesc
@@ -241,23 +240,23 @@ opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 syste
 [system.cpu.fuPool.FUList2.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList2.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList2.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList3]
 type=FUDesc
@@ -269,23 +268,23 @@ opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 syste
 [system.cpu.fuPool.FUList3.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList3.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=FloatDiv
 opLat=12
+pipelined=false
 
 [system.cpu.fuPool.FUList3.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=24
 opClass=FloatSqrt
 opLat=24
+pipelined=false
 
 [system.cpu.fuPool.FUList4]
 type=FUDesc
@@ -297,9 +296,9 @@ opList=system.cpu.fuPool.FUList4.opList
 [system.cpu.fuPool.FUList4.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5]
 type=FUDesc
@@ -311,142 +310,142 @@ opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 sys
 [system.cpu.fuPool.FUList5.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList6]
 type=FUDesc
@@ -458,9 +457,9 @@ opList=system.cpu.fuPool.FUList6.opList
 [system.cpu.fuPool.FUList6.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList7]
 type=FUDesc
@@ -472,16 +471,16 @@ opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 [system.cpu.fuPool.FUList7.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList7.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList8]
 type=FUDesc
@@ -493,9 +492,9 @@ opList=system.cpu.fuPool.FUList8.opList
 [system.cpu.fuPool.FUList8.opList]
 type=OpDesc
 eventq_index=0
-issueLat=3
 opClass=IprAccess
 opLat=3
+pipelined=false
 
 [system.cpu.icache]
 type=BaseCache
@@ -507,7 +506,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -518,7 +517,6 @@ size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -557,7 +555,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -568,7 +566,6 @@ size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
index 601735401..ca6ea576a 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -82,10 +83,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -96,7 +98,6 @@ size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -122,10 +123,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -136,7 +138,6 @@ size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -171,10 +172,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -185,7 +187,6 @@ size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
@@ -204,8 +205,11 @@ size=2097152
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
@@ -220,6 +224,7 @@ eventq_index=0
 type=LiveProcess
 cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
 cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing
+drivers=
 egid=100
 env=
 errout=cerr
@@ -228,6 +233,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -257,11 +263,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini
index e1f177c8e..e8259a3e5 100644
--- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini
@@ -111,7 +111,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
 BTBEntries=4096
 BTBTagSize=16
 RASSize=16
@@ -125,7 +125,6 @@ localCtrBits=2
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
-predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
@@ -137,7 +136,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -148,7 +147,6 @@ size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -597,7 +595,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -608,7 +606,6 @@ size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -708,7 +705,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -719,7 +716,6 @@ size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
index b4eb9458f..e201ba957 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
@@ -158,7 +158,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=6
 prefetch_on_access=false
@@ -169,7 +169,6 @@ size=32768
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=16
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -241,9 +240,9 @@ opList=system.cpu.fuPool.FUList0.opList
 [system.cpu.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList1]
 type=FUDesc
@@ -255,23 +254,23 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 syste
 [system.cpu.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=IntDiv
 opLat=12
+pipelined=false
 
 [system.cpu.fuPool.FUList1.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IprAccess
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList2]
 type=FUDesc
@@ -283,9 +282,9 @@ opList=system.cpu.fuPool.FUList2.opList
 [system.cpu.fuPool.FUList2.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList3]
 type=FUDesc
@@ -297,9 +296,9 @@ opList=system.cpu.fuPool.FUList3.opList
 [system.cpu.fuPool.FUList3.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList4]
 type=FUDesc
@@ -311,184 +310,184 @@ opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 sys
 [system.cpu.fuPool.FUList4.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=9
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=9
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList20]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList21]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList22]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList23]
 type=OpDesc
 eventq_index=0
-issueLat=9
 opClass=FloatDiv
 opLat=9
+pipelined=false
 
 [system.cpu.fuPool.FUList4.opList24]
 type=OpDesc
 eventq_index=0
-issueLat=33
 opClass=FloatSqrt
 opLat=33
+pipelined=false
 
 [system.cpu.fuPool.FUList4.opList25]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu.icache]
 type=BaseCache
@@ -500,7 +499,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=1
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=2
 prefetch_on_access=false
@@ -511,7 +510,6 @@ size=32768
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -611,7 +609,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=12
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=16
 prefetch_on_access=true
@@ -622,7 +620,6 @@ size=1048576
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
index a03e92cf3..4e3e7fbd7 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=atomic
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -87,6 +88,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.dtb
 
 [system.cpu.dstage2_mmu.stage2_tlb]
@@ -104,7 +106,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.membus.slave[6]
 
 [system.cpu.dtb]
 type=ArmTLB
@@ -154,6 +155,7 @@ id_mmfr3=34611729
 id_pfr0=49
 id_pfr1=4113
 midr=1091551472
+pmu=Null
 system=system
 
 [system.cpu.istage2_mmu]
@@ -161,6 +163,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.itb
 
 [system.cpu.istage2_mmu.stage2_tlb]
@@ -178,7 +181,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.membus.slave[5]
 
 [system.cpu.itb]
 type=ArmTLB
@@ -205,6 +207,7 @@ eventq_index=0
 type=LiveProcess
 cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
 cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic
+drivers=
 egid=100
 env=
 errout=cerr
@@ -213,6 +216,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -242,13 +246,16 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
-slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.physmem]
 type=SimpleMemory
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
index f7026168d..b055586ab 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -84,10 +85,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -98,7 +100,6 @@ size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -118,6 +119,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.dtb
 
 [system.cpu.dstage2_mmu.stage2_tlb]
@@ -135,7 +137,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu.toL2Bus.slave[5]
 
 [system.cpu.dtb]
 type=ArmTLB
@@ -160,10 +161,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -174,7 +176,6 @@ size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -220,6 +221,7 @@ id_mmfr3=34611729
 id_pfr0=49
 id_pfr1=4113
 midr=1091551472
+pmu=Null
 system=system
 
 [system.cpu.istage2_mmu]
@@ -227,6 +229,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.itb
 
 [system.cpu.istage2_mmu.stage2_tlb]
@@ -244,7 +247,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu.toL2Bus.slave[4]
 
 [system.cpu.itb]
 type=ArmTLB
@@ -269,10 +271,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -283,7 +286,6 @@ size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
@@ -302,13 +304,16 @@ size=2097152
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -318,6 +323,7 @@ eventq_index=0
 type=LiveProcess
 cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
 cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing
+drivers=
 egid=100
 env=
 errout=cerr
@@ -326,6 +332,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -355,11 +362,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini
index 503aa08b6..7c811432f 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -108,7 +109,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
 BTBEntries=4096
 BTBTagSize=16
 RASSize=16
@@ -122,7 +123,6 @@ localCtrBits=2
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
-predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
@@ -130,10 +130,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -144,7 +145,6 @@ size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -553,10 +553,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -567,7 +568,6 @@ size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -602,10 +602,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -616,7 +617,6 @@ size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
@@ -635,8 +635,11 @@ size=2097152
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
@@ -651,6 +654,7 @@ eventq_index=0
 type=LiveProcess
 cmd=perlbmk -I. -I lib mdred.makerand.pl
 cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing
+drivers=
 egid=100
 env=
 errout=cerr
@@ -659,6 +663,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -688,11 +693,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
@@ -723,7 +731,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -732,6 +740,7 @@ clk_domain=system.clk_domain
 conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
+device_size=536870912
 devices_per_rank=8
 dll=true
 eventq_index=0
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout
index 0fcd7392a..fadc32183 100644..100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout
@@ -3,1388 +3,651 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  7 2014 10:41:53
-gem5 started May  7 2014 15:12:23
-gem5 executing on cz3212c2d7
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing
+gem5 compiled Jul  3 2015 14:54:12
+gem5 started Jul  3 2015 15:19:41
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing
+
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
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-Exiting @ tick 1192700952000 because target called exit()
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+Exiting @ tick 560939897000 because target called exit()
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
index f01e763b0..3af7f6d2b 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
@@ -159,7 +159,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -170,7 +170,6 @@ size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -206,9 +205,9 @@ opList=system.cpu.fuPool.FUList0.opList
 [system.cpu.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList1]
 type=FUDesc
@@ -220,16 +219,16 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 [system.cpu.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=19
 opClass=IntDiv
 opLat=20
+pipelined=false
 
 [system.cpu.fuPool.FUList2]
 type=FUDesc
@@ -241,23 +240,23 @@ opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 syste
 [system.cpu.fuPool.FUList2.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList2.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList2.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList3]
 type=FUDesc
@@ -269,23 +268,23 @@ opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 syste
 [system.cpu.fuPool.FUList3.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList3.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=FloatDiv
 opLat=12
+pipelined=false
 
 [system.cpu.fuPool.FUList3.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=24
 opClass=FloatSqrt
 opLat=24
+pipelined=false
 
 [system.cpu.fuPool.FUList4]
 type=FUDesc
@@ -297,9 +296,9 @@ opList=system.cpu.fuPool.FUList4.opList
 [system.cpu.fuPool.FUList4.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5]
 type=FUDesc
@@ -311,142 +310,142 @@ opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 sys
 [system.cpu.fuPool.FUList5.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList6]
 type=FUDesc
@@ -458,9 +457,9 @@ opList=system.cpu.fuPool.FUList6.opList
 [system.cpu.fuPool.FUList6.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList7]
 type=FUDesc
@@ -472,16 +471,16 @@ opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 [system.cpu.fuPool.FUList7.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList7.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList8]
 type=FUDesc
@@ -493,9 +492,9 @@ opList=system.cpu.fuPool.FUList8.opList
 [system.cpu.fuPool.FUList8.opList]
 type=OpDesc
 eventq_index=0
-issueLat=3
 opClass=IprAccess
 opLat=3
+pipelined=false
 
 [system.cpu.icache]
 type=BaseCache
@@ -507,7 +506,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -518,7 +517,6 @@ size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -557,7 +555,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -568,7 +566,6 @@ size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
index 02a01f5db..bcb4e48fb 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=atomic
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -107,6 +108,7 @@ eventq_index=0
 type=LiveProcess
 cmd=perlbmk -I. -I lib mdred.makerand.pl
 cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic
+drivers=
 egid=100
 env=
 errout=cerr
@@ -115,6 +117,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -144,11 +147,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
index 385d89721..0dd51a4d4 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
@@ -1,1388 +1,653 @@
+Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 22 2014 16:27:55
-gem5 started Jan 22 2014 17:53:08
-gem5 executing on u200540-lin
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic
+gem5 compiled Jul  3 2015 14:54:12
+gem5 started Jul  3 2015 15:11:16
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic
+
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
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+0: 290958364
+Exiting @ tick 464394627000 because target called exit()
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
index 48df53b70..588b633d1 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -82,10 +83,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -96,7 +98,6 @@ size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -122,10 +123,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -136,7 +138,6 @@ size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -171,10 +172,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -185,7 +187,6 @@ size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
@@ -204,8 +205,11 @@ size=2097152
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
@@ -220,6 +224,7 @@ eventq_index=0
 type=LiveProcess
 cmd=perlbmk -I. -I lib mdred.makerand.pl
 cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing
+drivers=
 egid=100
 env=
 errout=cerr
@@ -228,6 +233,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -257,11 +263,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout
index f48beb892..9bc789b35 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout
@@ -1,1388 +1,653 @@
+Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 22 2014 16:27:55
-gem5 started Jan 22 2014 18:02:12
-gem5 executing on u200540-lin
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing
+gem5 compiled Jul  3 2015 14:54:12
+gem5 started Jul  3 2015 15:04:10
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing
+
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
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-Exiting @ tick 2769739533000 because target called exit()
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+Exiting @ tick 1286278511500 because target called exit()
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini
index 3d0a9003e..c3a686fba 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini
@@ -111,7 +111,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
 BTBEntries=4096
 BTBTagSize=16
 RASSize=16
@@ -125,7 +125,6 @@ localCtrBits=2
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
-predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
@@ -137,7 +136,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -148,7 +147,6 @@ size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -597,7 +595,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -608,7 +606,6 @@ size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -708,7 +705,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -719,7 +716,6 @@ size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
index 000c8b0e4..2898b2e51 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
@@ -158,7 +158,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=6
 prefetch_on_access=false
@@ -169,7 +169,6 @@ size=32768
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=16
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -241,9 +240,9 @@ opList=system.cpu.fuPool.FUList0.opList
 [system.cpu.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList1]
 type=FUDesc
@@ -255,23 +254,23 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 syste
 [system.cpu.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=IntDiv
 opLat=12
+pipelined=false
 
 [system.cpu.fuPool.FUList1.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IprAccess
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList2]
 type=FUDesc
@@ -283,9 +282,9 @@ opList=system.cpu.fuPool.FUList2.opList
 [system.cpu.fuPool.FUList2.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList3]
 type=FUDesc
@@ -297,9 +296,9 @@ opList=system.cpu.fuPool.FUList3.opList
 [system.cpu.fuPool.FUList3.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList4]
 type=FUDesc
@@ -311,184 +310,184 @@ opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 sys
 [system.cpu.fuPool.FUList4.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=9
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=9
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList20]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList21]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList22]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList23]
 type=OpDesc
 eventq_index=0
-issueLat=9
 opClass=FloatDiv
 opLat=9
+pipelined=false
 
 [system.cpu.fuPool.FUList4.opList24]
 type=OpDesc
 eventq_index=0
-issueLat=33
 opClass=FloatSqrt
 opLat=33
+pipelined=false
 
 [system.cpu.fuPool.FUList4.opList25]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu.icache]
 type=BaseCache
@@ -500,7 +499,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=1
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=2
 prefetch_on_access=false
@@ -511,7 +510,6 @@ size=32768
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -611,7 +609,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=12
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=16
 prefetch_on_access=true
@@ -622,7 +620,6 @@ size=1048576
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
index 7eb73e466..af71e081d 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=atomic
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -87,6 +88,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.dtb
 
 [system.cpu.dstage2_mmu.stage2_tlb]
@@ -104,7 +106,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.membus.slave[6]
 
 [system.cpu.dtb]
 type=ArmTLB
@@ -154,6 +155,7 @@ id_mmfr3=34611729
 id_pfr0=49
 id_pfr1=4113
 midr=1091551472
+pmu=Null
 system=system
 
 [system.cpu.istage2_mmu]
@@ -161,6 +163,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.itb
 
 [system.cpu.istage2_mmu.stage2_tlb]
@@ -178,7 +181,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.membus.slave[5]
 
 [system.cpu.itb]
 type=ArmTLB
@@ -205,6 +207,7 @@ eventq_index=0
 type=LiveProcess
 cmd=perlbmk -I. -I lib mdred.makerand.pl
 cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic
+drivers=
 egid=100
 env=
 errout=cerr
@@ -213,6 +216,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -242,13 +246,16 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
-slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.physmem]
 type=SimpleMemory
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout
index c4e0dd481..82929fd24 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout
@@ -1,1389 +1,653 @@
+Redirecting stdout to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 17:35:34
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic
+gem5 compiled Jul  3 2015 17:56:07
+gem5 started Jul  3 2015 22:26:16
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic
+
 Global frequency set at 1000000000000 ticks per second
-      0: system.cpu.isa: ISA system set to: 0 0x49db380
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
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+1000: 2068042552
+0: 290958364
+Exiting @ tick 395726778500 because target called exit()
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
index 0c1f952a4..fc759c123 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -84,10 +85,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -98,7 +100,6 @@ size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -118,6 +119,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.dtb
 
 [system.cpu.dstage2_mmu.stage2_tlb]
@@ -135,7 +137,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu.toL2Bus.slave[5]
 
 [system.cpu.dtb]
 type=ArmTLB
@@ -160,10 +161,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -174,7 +176,6 @@ size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -220,6 +221,7 @@ id_mmfr3=34611729
 id_pfr0=49
 id_pfr1=4113
 midr=1091551472
+pmu=Null
 system=system
 
 [system.cpu.istage2_mmu]
@@ -227,6 +229,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.itb
 
 [system.cpu.istage2_mmu.stage2_tlb]
@@ -244,7 +247,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu.toL2Bus.slave[4]
 
 [system.cpu.itb]
 type=ArmTLB
@@ -269,10 +271,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -283,7 +286,6 @@ size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
@@ -302,13 +304,16 @@ size=2097152
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -318,6 +323,7 @@ eventq_index=0
 type=LiveProcess
 cmd=perlbmk -I. -I lib mdred.makerand.pl
 cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing
+drivers=
 egid=100
 env=
 errout=cerr
@@ -326,6 +332,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -355,11 +362,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
index f8adf17ee..1fa1e0e5c 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
@@ -1,1389 +1,653 @@
+Redirecting stdout to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 17:50:08
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing
+gem5 compiled Jul  3 2015 17:56:07
+gem5 started Jul  3 2015 18:33:02
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing
+
 Global frequency set at 1000000000000 ticks per second
-      0: system.cpu.isa: ISA system set to: 0 0x56b7d00
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
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-Exiting @ tick 2326118592000 because target called exit()
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+Exiting @ tick 1043722398500 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini
index e4bee3f35..75824f793 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -108,7 +109,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
 BTBEntries=4096
 BTBTagSize=16
 RASSize=16
@@ -122,7 +123,6 @@ localCtrBits=2
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
-predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
@@ -130,10 +130,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -144,7 +145,6 @@ size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -553,10 +553,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -567,7 +568,6 @@ size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -602,10 +602,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -616,7 +617,6 @@ size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
@@ -635,8 +635,11 @@ size=2097152
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
@@ -651,6 +654,7 @@ eventq_index=0
 type=LiveProcess
 cmd=vortex lendian.raw
 cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing
+drivers=
 egid=100
 env=
 errout=cerr
@@ -659,6 +663,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -688,11 +693,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
@@ -723,7 +731,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -732,6 +740,7 @@ clk_domain=system.clk_domain
 conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
+device_size=536870912
 devices_per_rank=8
 dll=true
 eventq_index=0
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
index 30f498cad..7662c92f8 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
@@ -159,7 +159,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -170,7 +170,6 @@ size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -206,9 +205,9 @@ opList=system.cpu.fuPool.FUList0.opList
 [system.cpu.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList1]
 type=FUDesc
@@ -220,16 +219,16 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 [system.cpu.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=19
 opClass=IntDiv
 opLat=20
+pipelined=false
 
 [system.cpu.fuPool.FUList2]
 type=FUDesc
@@ -241,23 +240,23 @@ opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 syste
 [system.cpu.fuPool.FUList2.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList2.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList2.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList3]
 type=FUDesc
@@ -269,23 +268,23 @@ opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 syste
 [system.cpu.fuPool.FUList3.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList3.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=FloatDiv
 opLat=12
+pipelined=false
 
 [system.cpu.fuPool.FUList3.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=24
 opClass=FloatSqrt
 opLat=24
+pipelined=false
 
 [system.cpu.fuPool.FUList4]
 type=FUDesc
@@ -297,9 +296,9 @@ opList=system.cpu.fuPool.FUList4.opList
 [system.cpu.fuPool.FUList4.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5]
 type=FUDesc
@@ -311,142 +310,142 @@ opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 sys
 [system.cpu.fuPool.FUList5.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList6]
 type=FUDesc
@@ -458,9 +457,9 @@ opList=system.cpu.fuPool.FUList6.opList
 [system.cpu.fuPool.FUList6.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList7]
 type=FUDesc
@@ -472,16 +471,16 @@ opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 [system.cpu.fuPool.FUList7.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList7.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList8]
 type=FUDesc
@@ -493,9 +492,9 @@ opList=system.cpu.fuPool.FUList8.opList
 [system.cpu.fuPool.FUList8.opList]
 type=OpDesc
 eventq_index=0
-issueLat=3
 opClass=IprAccess
 opLat=3
+pipelined=false
 
 [system.cpu.icache]
 type=BaseCache
@@ -507,7 +506,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -518,7 +517,6 @@ size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -557,7 +555,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -568,7 +566,6 @@ size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini
index 97bcd61c2..5bde02f67 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini
@@ -111,7 +111,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
 BTBEntries=4096
 BTBTagSize=16
 RASSize=16
@@ -125,7 +125,6 @@ localCtrBits=2
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
-predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
@@ -137,7 +136,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -148,7 +147,6 @@ size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -597,7 +595,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -608,7 +606,6 @@ size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -708,7 +705,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -719,7 +716,6 @@ size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
index d5bef4cae..4695f21d9 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
@@ -158,7 +158,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=6
 prefetch_on_access=false
@@ -169,7 +169,6 @@ size=32768
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=16
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -241,9 +240,9 @@ opList=system.cpu.fuPool.FUList0.opList
 [system.cpu.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList1]
 type=FUDesc
@@ -255,23 +254,23 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 syste
 [system.cpu.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=IntDiv
 opLat=12
+pipelined=false
 
 [system.cpu.fuPool.FUList1.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IprAccess
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList2]
 type=FUDesc
@@ -283,9 +282,9 @@ opList=system.cpu.fuPool.FUList2.opList
 [system.cpu.fuPool.FUList2.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList3]
 type=FUDesc
@@ -297,9 +296,9 @@ opList=system.cpu.fuPool.FUList3.opList
 [system.cpu.fuPool.FUList3.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList4]
 type=FUDesc
@@ -311,184 +310,184 @@ opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 sys
 [system.cpu.fuPool.FUList4.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=9
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=9
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList20]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList21]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList22]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList23]
 type=OpDesc
 eventq_index=0
-issueLat=9
 opClass=FloatDiv
 opLat=9
+pipelined=false
 
 [system.cpu.fuPool.FUList4.opList24]
 type=OpDesc
 eventq_index=0
-issueLat=33
 opClass=FloatSqrt
 opLat=33
+pipelined=false
 
 [system.cpu.fuPool.FUList4.opList25]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu.icache]
 type=BaseCache
@@ -500,7 +499,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=1
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=2
 prefetch_on_access=false
@@ -511,7 +510,6 @@ size=32768
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -611,7 +609,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=12
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=16
 prefetch_on_access=true
@@ -622,7 +620,6 @@ size=1048576
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini
index 706f923dd..e5802151f 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -108,7 +109,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
 BTBEntries=4096
 BTBTagSize=16
 RASSize=16
@@ -122,7 +123,6 @@ localCtrBits=2
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
-predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
@@ -130,10 +130,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -144,7 +145,6 @@ size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -553,10 +553,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -567,7 +568,6 @@ size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -602,10 +602,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -616,7 +617,6 @@ size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
@@ -635,8 +635,11 @@ size=2097152
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
@@ -651,6 +654,7 @@ eventq_index=0
 type=LiveProcess
 cmd=bzip2 input.source 1
 cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/minor-timing
+drivers=
 egid=100
 env=
 errout=cerr
@@ -659,6 +663,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -688,11 +693,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
@@ -723,7 +731,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -732,6 +740,7 @@ clk_domain=system.clk_domain
 conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
+device_size=536870912
 devices_per_rank=8
 dll=true
 eventq_index=0
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
index 0aec3b5e9..0be38fe21 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
@@ -159,7 +159,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -170,7 +170,6 @@ size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -206,9 +205,9 @@ opList=system.cpu.fuPool.FUList0.opList
 [system.cpu.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList1]
 type=FUDesc
@@ -220,16 +219,16 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 [system.cpu.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=19
 opClass=IntDiv
 opLat=20
+pipelined=false
 
 [system.cpu.fuPool.FUList2]
 type=FUDesc
@@ -241,23 +240,23 @@ opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 syste
 [system.cpu.fuPool.FUList2.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList2.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList2.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList3]
 type=FUDesc
@@ -269,23 +268,23 @@ opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 syste
 [system.cpu.fuPool.FUList3.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList3.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=FloatDiv
 opLat=12
+pipelined=false
 
 [system.cpu.fuPool.FUList3.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=24
 opClass=FloatSqrt
 opLat=24
+pipelined=false
 
 [system.cpu.fuPool.FUList4]
 type=FUDesc
@@ -297,9 +296,9 @@ opList=system.cpu.fuPool.FUList4.opList
 [system.cpu.fuPool.FUList4.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5]
 type=FUDesc
@@ -311,142 +310,142 @@ opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 sys
 [system.cpu.fuPool.FUList5.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList6]
 type=FUDesc
@@ -458,9 +457,9 @@ opList=system.cpu.fuPool.FUList6.opList
 [system.cpu.fuPool.FUList6.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList7]
 type=FUDesc
@@ -472,16 +471,16 @@ opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 [system.cpu.fuPool.FUList7.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList7.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList8]
 type=FUDesc
@@ -493,9 +492,9 @@ opList=system.cpu.fuPool.FUList8.opList
 [system.cpu.fuPool.FUList8.opList]
 type=OpDesc
 eventq_index=0
-issueLat=3
 opClass=IprAccess
 opLat=3
+pipelined=false
 
 [system.cpu.icache]
 type=BaseCache
@@ -507,7 +506,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -518,7 +517,6 @@ size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -557,7 +555,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -568,7 +566,6 @@ size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
index 2e63bb33b..d3c80bc18 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=atomic
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -107,6 +108,7 @@ eventq_index=0
 type=LiveProcess
 cmd=bzip2 input.source 1
 cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic
+drivers=
 egid=100
 env=
 errout=cerr
@@ -115,6 +117,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -144,11 +147,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
index fc2fe20b8..a70b71696 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -82,10 +83,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -96,7 +98,6 @@ size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -122,10 +123,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -136,7 +138,6 @@ size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -171,10 +172,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -185,7 +187,6 @@ size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
@@ -204,8 +205,11 @@ size=2097152
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
@@ -220,6 +224,7 @@ eventq_index=0
 type=LiveProcess
 cmd=bzip2 input.source 1
 cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing
+drivers=
 egid=100
 env=
 errout=cerr
@@ -228,6 +233,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -257,11 +263,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini
index 634fc5445..ca8e0ac4e 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini
@@ -111,7 +111,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
 BTBEntries=4096
 BTBTagSize=16
 RASSize=16
@@ -125,7 +125,6 @@ localCtrBits=2
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
-predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
@@ -137,7 +136,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -148,7 +147,6 @@ size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -597,7 +595,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -608,7 +606,6 @@ size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -708,7 +705,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -719,7 +716,6 @@ size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
index eadc51bd2..eea4d6225 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
@@ -158,7 +158,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=6
 prefetch_on_access=false
@@ -169,7 +169,6 @@ size=32768
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=16
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -241,9 +240,9 @@ opList=system.cpu.fuPool.FUList0.opList
 [system.cpu.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList1]
 type=FUDesc
@@ -255,23 +254,23 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 syste
 [system.cpu.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=IntDiv
 opLat=12
+pipelined=false
 
 [system.cpu.fuPool.FUList1.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IprAccess
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList2]
 type=FUDesc
@@ -283,9 +282,9 @@ opList=system.cpu.fuPool.FUList2.opList
 [system.cpu.fuPool.FUList2.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList3]
 type=FUDesc
@@ -297,9 +296,9 @@ opList=system.cpu.fuPool.FUList3.opList
 [system.cpu.fuPool.FUList3.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList4]
 type=FUDesc
@@ -311,184 +310,184 @@ opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 sys
 [system.cpu.fuPool.FUList4.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=9
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=9
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList20]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList21]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList22]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList23]
 type=OpDesc
 eventq_index=0
-issueLat=9
 opClass=FloatDiv
 opLat=9
+pipelined=false
 
 [system.cpu.fuPool.FUList4.opList24]
 type=OpDesc
 eventq_index=0
-issueLat=33
 opClass=FloatSqrt
 opLat=33
+pipelined=false
 
 [system.cpu.fuPool.FUList4.opList25]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu.icache]
 type=BaseCache
@@ -500,7 +499,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=1
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=2
 prefetch_on_access=false
@@ -511,7 +510,6 @@ size=32768
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -611,7 +609,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=12
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=16
 prefetch_on_access=true
@@ -622,7 +620,6 @@ size=1048576
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
@@ -691,7 +688,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/bzip2
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2
 gid=100
 input=cin
 kvmInSE=false
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
index c5adbf84c..dce12b6b3 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=atomic
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -87,6 +88,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.dtb
 
 [system.cpu.dstage2_mmu.stage2_tlb]
@@ -104,7 +106,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.membus.slave[6]
 
 [system.cpu.dtb]
 type=ArmTLB
@@ -154,6 +155,7 @@ id_mmfr3=34611729
 id_pfr0=49
 id_pfr1=4113
 midr=1091551472
+pmu=Null
 system=system
 
 [system.cpu.istage2_mmu]
@@ -161,6 +163,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.itb
 
 [system.cpu.istage2_mmu.stage2_tlb]
@@ -178,7 +181,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.membus.slave[5]
 
 [system.cpu.itb]
 type=ArmTLB
@@ -205,6 +207,7 @@ eventq_index=0
 type=LiveProcess
 cmd=bzip2 input.source 1
 cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic
+drivers=
 egid=100
 env=
 errout=cerr
@@ -213,6 +216,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -242,13 +246,16 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
-slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.physmem]
 type=SimpleMemory
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
index 3bcac58f7..bc5565f58 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -84,10 +85,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -98,7 +100,6 @@ size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -118,6 +119,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.dtb
 
 [system.cpu.dstage2_mmu.stage2_tlb]
@@ -135,7 +137,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu.toL2Bus.slave[5]
 
 [system.cpu.dtb]
 type=ArmTLB
@@ -160,10 +161,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -174,7 +176,6 @@ size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -220,6 +221,7 @@ id_mmfr3=34611729
 id_pfr0=49
 id_pfr1=4113
 midr=1091551472
+pmu=Null
 system=system
 
 [system.cpu.istage2_mmu]
@@ -227,6 +229,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.itb
 
 [system.cpu.istage2_mmu.stage2_tlb]
@@ -244,7 +247,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu.toL2Bus.slave[4]
 
 [system.cpu.itb]
 type=ArmTLB
@@ -269,10 +271,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -283,7 +286,6 @@ size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
@@ -302,13 +304,16 @@ size=2097152
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -318,6 +323,7 @@ eventq_index=0
 type=LiveProcess
 cmd=bzip2 input.source 1
 cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing
+drivers=
 egid=100
 env=
 errout=cerr
@@ -326,6 +332,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -355,11 +362,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini
index 250783f94..459f492af 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -108,7 +109,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
 BTBEntries=4096
 BTBTagSize=16
 RASSize=16
@@ -122,7 +123,6 @@ localCtrBits=2
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
-predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
@@ -130,10 +130,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -144,7 +145,6 @@ size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -553,10 +553,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -567,7 +568,6 @@ size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -602,10 +602,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -616,7 +617,6 @@ size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
@@ -635,8 +635,11 @@ size=2097152
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
@@ -651,6 +654,7 @@ eventq_index=0
 type=LiveProcess
 cmd=twolf smred
 cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing
+drivers=
 egid=100
 env=
 errout=cerr
@@ -659,6 +663,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -688,11 +693,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
@@ -723,7 +731,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -732,6 +740,7 @@ clk_domain=system.clk_domain
 conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
+device_size=536870912
 devices_per_rank=8
 dll=true
 eventq_index=0
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
index aa4b312c2..4e01cb733 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
@@ -159,7 +159,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -170,7 +170,6 @@ size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -206,9 +205,9 @@ opList=system.cpu.fuPool.FUList0.opList
 [system.cpu.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList1]
 type=FUDesc
@@ -220,16 +219,16 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 [system.cpu.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=19
 opClass=IntDiv
 opLat=20
+pipelined=false
 
 [system.cpu.fuPool.FUList2]
 type=FUDesc
@@ -241,23 +240,23 @@ opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 syste
 [system.cpu.fuPool.FUList2.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList2.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList2.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList3]
 type=FUDesc
@@ -269,23 +268,23 @@ opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 syste
 [system.cpu.fuPool.FUList3.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList3.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=FloatDiv
 opLat=12
+pipelined=false
 
 [system.cpu.fuPool.FUList3.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=24
 opClass=FloatSqrt
 opLat=24
+pipelined=false
 
 [system.cpu.fuPool.FUList4]
 type=FUDesc
@@ -297,9 +296,9 @@ opList=system.cpu.fuPool.FUList4.opList
 [system.cpu.fuPool.FUList4.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5]
 type=FUDesc
@@ -311,142 +310,142 @@ opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 sys
 [system.cpu.fuPool.FUList5.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList6]
 type=FUDesc
@@ -458,9 +457,9 @@ opList=system.cpu.fuPool.FUList6.opList
 [system.cpu.fuPool.FUList6.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList7]
 type=FUDesc
@@ -472,16 +471,16 @@ opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 [system.cpu.fuPool.FUList7.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList7.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList8]
 type=FUDesc
@@ -493,9 +492,9 @@ opList=system.cpu.fuPool.FUList8.opList
 [system.cpu.fuPool.FUList8.opList]
 type=OpDesc
 eventq_index=0
-issueLat=3
 opClass=IprAccess
 opLat=3
+pipelined=false
 
 [system.cpu.icache]
 type=BaseCache
@@ -507,7 +506,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -518,7 +517,6 @@ size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -557,7 +555,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -568,7 +566,6 @@ size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
@@ -612,7 +609,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
 gid=100
 input=cin
 kvmInSE=false
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini
index 00a1bf85d..29e916711 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini
@@ -111,7 +111,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
 BTBEntries=4096
 BTBTagSize=16
 RASSize=16
@@ -125,7 +125,6 @@ localCtrBits=2
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
-predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
@@ -137,7 +136,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -148,7 +147,6 @@ size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -597,7 +595,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -608,7 +606,6 @@ size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -708,7 +705,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -719,7 +716,6 @@ size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
index a3174479b..962fb9596 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
@@ -158,7 +158,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=6
 prefetch_on_access=false
@@ -169,7 +169,6 @@ size=32768
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=16
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -241,9 +240,9 @@ opList=system.cpu.fuPool.FUList0.opList
 [system.cpu.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList1]
 type=FUDesc
@@ -255,23 +254,23 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 syste
 [system.cpu.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=IntDiv
 opLat=12
+pipelined=false
 
 [system.cpu.fuPool.FUList1.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IprAccess
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList2]
 type=FUDesc
@@ -283,9 +282,9 @@ opList=system.cpu.fuPool.FUList2.opList
 [system.cpu.fuPool.FUList2.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList3]
 type=FUDesc
@@ -297,9 +296,9 @@ opList=system.cpu.fuPool.FUList3.opList
 [system.cpu.fuPool.FUList3.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList4]
 type=FUDesc
@@ -311,184 +310,184 @@ opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 sys
 [system.cpu.fuPool.FUList4.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=9
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=9
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList20]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList21]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList22]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList23]
 type=OpDesc
 eventq_index=0
-issueLat=9
 opClass=FloatDiv
 opLat=9
+pipelined=false
 
 [system.cpu.fuPool.FUList4.opList24]
 type=OpDesc
 eventq_index=0
-issueLat=33
 opClass=FloatSqrt
 opLat=33
+pipelined=false
 
 [system.cpu.fuPool.FUList4.opList25]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu.icache]
 type=BaseCache
@@ -500,7 +499,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=1
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=2
 prefetch_on_access=false
@@ -511,7 +510,6 @@ size=32768
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -611,7 +609,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=12
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=16
 prefetch_on_access=true
@@ -622,7 +620,6 @@ size=1048576
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
index 4f89807d5..4494621d8 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
@@ -87,7 +87,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -98,7 +98,6 @@ size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -128,7 +127,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -139,7 +138,6 @@ size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -178,7 +176,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -189,7 +187,6 @@ size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini
index b89f21c49..58c25e2f3 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini
@@ -109,7 +109,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
 BTBEntries=4096
 BTBTagSize=16
 RASSize=16
@@ -123,7 +123,6 @@ localCtrBits=2
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
-predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
@@ -135,7 +134,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -146,7 +145,6 @@ size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -559,7 +557,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -570,7 +568,6 @@ size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -609,7 +606,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -620,7 +617,6 @@ size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
index 51b805140..09a1c4524 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -159,7 +159,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -170,7 +170,6 @@ size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -206,9 +205,9 @@ opList=system.cpu.fuPool.FUList0.opList
 [system.cpu.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList1]
 type=FUDesc
@@ -220,16 +219,16 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 [system.cpu.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=19
 opClass=IntDiv
 opLat=20
+pipelined=false
 
 [system.cpu.fuPool.FUList2]
 type=FUDesc
@@ -241,23 +240,23 @@ opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 syste
 [system.cpu.fuPool.FUList2.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList2.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList2.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList3]
 type=FUDesc
@@ -269,23 +268,23 @@ opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 syste
 [system.cpu.fuPool.FUList3.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList3.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=FloatDiv
 opLat=12
+pipelined=false
 
 [system.cpu.fuPool.FUList3.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=24
 opClass=FloatSqrt
 opLat=24
+pipelined=false
 
 [system.cpu.fuPool.FUList4]
 type=FUDesc
@@ -297,9 +296,9 @@ opList=system.cpu.fuPool.FUList4.opList
 [system.cpu.fuPool.FUList4.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5]
 type=FUDesc
@@ -311,142 +310,142 @@ opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 sys
 [system.cpu.fuPool.FUList5.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList6]
 type=FUDesc
@@ -458,9 +457,9 @@ opList=system.cpu.fuPool.FUList6.opList
 [system.cpu.fuPool.FUList6.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList7]
 type=FUDesc
@@ -472,16 +471,16 @@ opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 [system.cpu.fuPool.FUList7.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList7.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList8]
 type=FUDesc
@@ -493,9 +492,9 @@ opList=system.cpu.fuPool.FUList8.opList
 [system.cpu.fuPool.FUList8.opList]
 type=OpDesc
 eventq_index=0
-issueLat=3
 opClass=IprAccess
 opLat=3
+pipelined=false
 
 [system.cpu.icache]
 type=BaseCache
@@ -507,7 +506,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -518,7 +517,6 @@ size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -557,7 +555,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -568,7 +566,6 @@ size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
index 60f2b3295..7319a71af 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
@@ -87,7 +87,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -98,7 +98,6 @@ size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -128,7 +127,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -139,7 +138,6 @@ size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -177,7 +175,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -188,7 +186,6 @@ size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
index 9d4907542..998b24edb 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
@@ -159,7 +159,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -170,7 +170,6 @@ size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -206,9 +205,9 @@ opList=system.cpu.fuPool.FUList0.opList
 [system.cpu.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList1]
 type=FUDesc
@@ -220,16 +219,16 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 [system.cpu.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=19
 opClass=IntDiv
 opLat=20
+pipelined=false
 
 [system.cpu.fuPool.FUList2]
 type=FUDesc
@@ -241,23 +240,23 @@ opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 syste
 [system.cpu.fuPool.FUList2.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList2.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList2.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList3]
 type=FUDesc
@@ -269,23 +268,23 @@ opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 syste
 [system.cpu.fuPool.FUList3.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList3.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=FloatDiv
 opLat=12
+pipelined=false
 
 [system.cpu.fuPool.FUList3.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=24
 opClass=FloatSqrt
 opLat=24
+pipelined=false
 
 [system.cpu.fuPool.FUList4]
 type=FUDesc
@@ -297,9 +296,9 @@ opList=system.cpu.fuPool.FUList4.opList
 [system.cpu.fuPool.FUList4.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5]
 type=FUDesc
@@ -311,142 +310,142 @@ opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 sys
 [system.cpu.fuPool.FUList5.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList6]
 type=FUDesc
@@ -458,9 +457,9 @@ opList=system.cpu.fuPool.FUList6.opList
 [system.cpu.fuPool.FUList6.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList7]
 type=FUDesc
@@ -472,16 +471,16 @@ opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 [system.cpu.fuPool.FUList7.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList7.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList8]
 type=FUDesc
@@ -493,9 +492,9 @@ opList=system.cpu.fuPool.FUList8.opList
 [system.cpu.fuPool.FUList8.opList]
 type=OpDesc
 eventq_index=0
-issueLat=3
 opClass=IprAccess
 opLat=3
+pipelined=false
 
 [system.cpu.icache]
 type=BaseCache
@@ -507,7 +506,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -518,7 +517,6 @@ size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -562,7 +560,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -573,7 +571,6 @@ size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
index 392920ac8..9da046447 100644
--- a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=atomic
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -87,6 +88,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.dtb
 
 [system.cpu.dstage2_mmu.stage2_tlb]
@@ -104,7 +106,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.membus.slave[6]
 
 [system.cpu.dtb]
 type=ArmTLB
@@ -154,6 +155,7 @@ id_mmfr3=34611729
 id_pfr0=49
 id_pfr1=4113
 midr=1091551472
+pmu=Null
 system=system
 
 [system.cpu.istage2_mmu]
@@ -161,6 +163,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.itb
 
 [system.cpu.istage2_mmu.stage2_tlb]
@@ -178,7 +181,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.membus.slave[5]
 
 [system.cpu.itb]
 type=ArmTLB
@@ -204,7 +206,8 @@ eventq_index=0
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic
+cwd=build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-atomic
+drivers=
 egid=100
 env=
 errout=cerr
@@ -213,6 +216,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
 gid=100
 input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -242,13 +246,16 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
-slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.physmem]
 type=SimpleMemory
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
index 7d45c36b9..bc136f4c7 100644
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000727                       # Nu
 sim_ticks                                   727072500                       # Number of ticks simulated
 final_tick                                  727072500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 639322                       # Simulator instruction rate (inst/s)
-host_op_rate                                   639300                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              929601467                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 223596                       # Number of bytes of host memory used
-host_seconds                                     0.78                       # Real time elapsed on the host
+host_inst_rate                                1010970                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1010933                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1469988465                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 285244                       # Number of bytes of host memory used
+host_seconds                                     0.49                       # Real time elapsed on the host
 sim_insts                                      500001                       # Number of instructions simulated
 sim_ops                                        500001                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -122,14 +122,14 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                     500019                       # Class of executed instruction
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           287.258890                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse           287.258578                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs              180321                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               454                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs            397.182819                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   287.258890                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.070132                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.070132                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data   287.258578                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.070131                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.070131                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          454                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           26                       # Occupied blocks per task id
@@ -201,14 +201,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          454
 system.cpu.dcache.demand_mshr_misses::total          454                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          454                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          454                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     16852500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     16852500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      7436500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      7436500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     24289000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     24289000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     24289000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     24289000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     17010000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     17010000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      7506000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      7506000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     24516000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     24516000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     24516000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     24516000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002531                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002531                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002467                       # mshr miss rate for WriteReq accesses
@@ -217,22 +217,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002511
 system.cpu.dcache.demand_mshr_miss_rate::total     0.002511                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002511                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.002511                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        53500                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        53500                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53500                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        53500                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        53500                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total        53500                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53500                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total        53500                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        54000                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        54000                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        54000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        54000                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        54000                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total        54000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        54000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total        54000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           265.012564                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           265.012287                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs              499617                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               403                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs           1239.744417                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   265.012564                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst   265.012287                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.129401                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.129401                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          403                       # Occupied blocks per task id
@@ -290,33 +290,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          403
 system.cpu.icache.demand_mshr_misses::total          403                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          403                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          403                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     21561000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     21561000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     21561000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     21561000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     21561000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     21561000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     21762500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     21762500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     21762500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     21762500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     21762500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     21762500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000806                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000806                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000806                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000806                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000806                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000806                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53501.240695                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53501.240695                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53501.240695                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 53501.240695                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53501.240695                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 53501.240695                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54001.240695                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54001.240695                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54001.240695                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 54001.240695                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54001.240695                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 54001.240695                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          481.541188                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          481.539213                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  0                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              718                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs                    0                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   265.019216                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   216.521972                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   265.018107                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   216.521106                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.008088                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.006608                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.014695                       # Average percentage of cache occupancy
@@ -327,55 +327,60 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2          714
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.021912                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             7713                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            7713                       # Number of data accesses
-system.cpu.l2cache.ReadReq_misses::cpu.inst          403                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          315                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          718                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data          139                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total          139                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          403                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          403                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data          315                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total          315                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst          403                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data          454                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total           857                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst          403                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          454                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          857                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     21158000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     16537500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     37695500                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      7297500                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total      7297500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     21158000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     21158000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     16537500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     16537500                       # number of ReadSharedReq miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.inst     21158000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.data     23835000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::total     44993000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.inst     21158000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.data     23835000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::total     44993000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          403                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data          315                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          718                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data          139                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total          139                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          403                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          403                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          315                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total          315                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst          403                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data          454                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total          857                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst          403                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data          454                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total          857                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total            1                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst            1                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total            1                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total            1                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total            1                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.240695                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52500                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.696379                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52500                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52500                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52501.240695                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52501.240695                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data        52500                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total        52500                       # average ReadSharedReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.240695                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52500                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::total 52500.583431                       # average overall miss latency
@@ -390,55 +395,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          403                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          315                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          718                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          139                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total          139                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          403                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          403                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          315                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          315                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst          403                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data          454                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total          857                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          403                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          454                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          857                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     16321500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     12757500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     29079000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      5629500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      5629500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     16321500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     18387000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     34708500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     16321500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     18387000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     34708500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      5907500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      5907500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     17128000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     17128000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     13387500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     13387500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     17128000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     19295000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     36423000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     17128000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     19295000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     36423000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40500                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        42500                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        42500                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42501.240695                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42501.240695                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        42500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        42500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.240695                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        42500                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.583431                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.240695                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        42500                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.583431                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq            718                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           718                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq          139                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp          139                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          403                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq          315                       # Transaction distribution
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          806                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          908                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total              1714                       # Packet count per connected master and slave (bytes)
@@ -463,10 +473,10 @@ system.cpu.toL2Bus.respLayer0.occupancy        604500                       # La
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        681000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.membus.trans_dist::ReadReq                 718                       # Transaction distribution
 system.membus.trans_dist::ReadResp                718                       # Transaction distribution
 system.membus.trans_dist::ReadExReq               139                       # Transaction distribution
 system.membus.trans_dist::ReadExResp              139                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq           718                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         1714                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                   1714                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        54848                       # Cumulative packet size per connected master and slave (bytes)
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
index 8ea14a565..ee3422841 100644
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
@@ -91,7 +91,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -102,7 +102,6 @@ size=32768
 system=system
 tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
@@ -132,7 +131,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -143,7 +142,6 @@ size=32768
 system=system
 tags=system.cpu0.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
@@ -236,7 +234,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -247,7 +245,6 @@ size=32768
 system=system
 tags=system.cpu1.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.dcache_port
 mem_side=system.toL2Bus.slave[3]
@@ -277,7 +274,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -288,7 +285,6 @@ size=32768
 system=system
 tags=system.cpu1.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.icache_port
 mem_side=system.toL2Bus.slave[2]
@@ -381,7 +377,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -392,7 +388,6 @@ size=32768
 system=system
 tags=system.cpu2.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.dcache_port
 mem_side=system.toL2Bus.slave[5]
@@ -422,7 +417,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -433,7 +428,6 @@ size=32768
 system=system
 tags=system.cpu2.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.icache_port
 mem_side=system.toL2Bus.slave[4]
@@ -526,7 +520,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -537,7 +531,6 @@ size=32768
 system=system
 tags=system.cpu3.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.dcache_port
 mem_side=system.toL2Bus.slave[7]
@@ -567,7 +560,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -578,7 +571,6 @@ size=32768
 system=system
 tags=system.cpu3.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.icache_port
 mem_side=system.toL2Bus.slave[6]
@@ -650,7 +642,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -661,7 +653,6 @@ size=4194304
 system=system
 tags=system.l2c.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
index 7a94e3207..8a18a4d03 100644
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000250                       # Nu
 sim_ticks                                   250015500                       # Number of ticks simulated
 final_tick                                  250015500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1548972                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1548948                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              193626740                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 235568                       # Number of bytes of host memory used
-host_seconds                                     1.29                       # Real time elapsed on the host
+host_inst_rate                                2352807                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2352743                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              294103962                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 298060                       # Number of bytes of host memory used
+host_seconds                                     0.85                       # Real time elapsed on the host
 sim_insts                                     2000004                       # Number of instructions simulated
 sim_ops                                       2000004                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -854,9 +854,9 @@ system.cpu3.icache.cache_copies                     0                       # nu
 system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.l2c.tags.replacements                        0                       # number of replacements
 system.l2c.tags.tagsinuse                 1962.780232                       # Cycle average of tags in use
-system.l2c.tags.total_refs                        332                       # Total number of references to valid blocks.
+system.l2c.tags.total_refs                       1068                       # Total number of references to valid blocks.
 system.l2c.tags.sampled_refs                     2932                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     0.113233                       # Average number of references to valid blocks.
+system.l2c.tags.avg_refs                     0.364256                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
 system.l2c.tags.occ_blocks::writebacks      17.466765                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu0.inst      267.152061                       # Average occupied blocks per requestor
@@ -882,19 +882,20 @@ system.l2c.tags.age_task_id_blocks_1024::0            8                       #
 system.l2c.tags.age_task_id_blocks_1024::1         1088                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::2         1836                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_percent::1024     0.044739                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                    34048                       # Number of tag accesses
-system.l2c.tags.data_accesses                   34048                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.inst                 60                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst                 60                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst                 60                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.inst                 60                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                    276                       # number of ReadReq hits
+system.l2c.tags.tag_accesses                    39936                       # Number of tag accesses
+system.l2c.tags.data_accesses                   39936                       # Number of data accesses
 system.l2c.Writeback_hits::writebacks             116                       # number of Writeback hits
 system.l2c.Writeback_hits::total                  116                       # number of Writeback hits
+system.l2c.ReadCleanReq_hits::cpu0.inst            60                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu1.inst            60                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu2.inst            60                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu3.inst            60                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::total               240                       # number of ReadCleanReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data            9                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data            9                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu2.data            9                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu3.data            9                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total               36                       # number of ReadSharedReq hits
 system.l2c.demand_hits::cpu0.inst                  60                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu0.data                   9                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu1.inst                  60                       # number of demand (read+write) hits
@@ -913,20 +914,21 @@ system.l2c.overall_hits::cpu2.data                  9                       # nu
 system.l2c.overall_hits::cpu3.inst                 60                       # number of overall hits
 system.l2c.overall_hits::cpu3.data                  9                       # number of overall hits
 system.l2c.overall_hits::total                    276                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst              403                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data              315                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst              403                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data              315                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst              403                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data              315                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.inst              403                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.data              315                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                 2872                       # number of ReadReq misses
 system.l2c.ReadExReq_misses::cpu0.data            139                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::cpu1.data            139                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::cpu2.data            139                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::cpu3.data            139                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::total                556                       # number of ReadExReq misses
+system.l2c.ReadCleanReq_misses::cpu0.inst          403                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu1.inst          403                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu2.inst          403                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu3.inst          403                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::total            1612                       # number of ReadCleanReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data          315                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data          315                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu2.data          315                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu3.data          315                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total           1260                       # number of ReadSharedReq misses
 system.l2c.demand_misses::cpu0.inst               403                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.data               454                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu1.inst               403                       # number of demand (read+write) misses
@@ -945,15 +947,6 @@ system.l2c.overall_misses::cpu2.data              454                       # nu
 system.l2c.overall_misses::cpu3.inst              403                       # number of overall misses
 system.l2c.overall_misses::cpu3.data              454                       # number of overall misses
 system.l2c.overall_misses::total                 3428                       # number of overall misses
-system.l2c.ReadReq_accesses::cpu0.inst            463                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data            324                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst            463                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data            324                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst            463                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.data            324                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.inst            463                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.data            324                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total               3148                       # number of ReadReq accesses(hits+misses)
 system.l2c.Writeback_accesses::writebacks          116                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_accesses::total              116                       # number of Writeback accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu0.data          139                       # number of ReadExReq accesses(hits+misses)
@@ -961,6 +954,16 @@ system.l2c.ReadExReq_accesses::cpu1.data          139                       # nu
 system.l2c.ReadExReq_accesses::cpu2.data          139                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu3.data          139                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::total              556                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu0.inst          463                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu1.inst          463                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu2.inst          463                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu3.inst          463                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total          1852                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data          324                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data          324                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu2.data          324                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu3.data          324                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total         1296                       # number of ReadSharedReq accesses(hits+misses)
 system.l2c.demand_accesses::cpu0.inst             463                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu0.data             463                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu1.inst             463                       # number of demand (read+write) accesses
@@ -979,20 +982,21 @@ system.l2c.overall_accesses::cpu2.data            463                       # nu
 system.l2c.overall_accesses::cpu3.inst            463                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu3.data            463                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total               3704                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.870410                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.972222                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.870410                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.972222                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst      0.870410                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data      0.972222                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.inst      0.870410                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.data      0.972222                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.912325                       # miss rate for ReadReq accesses
 system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.870410                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.870410                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.870410                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.870410                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.870410                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.972222                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.972222                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.972222                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.972222                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.972222                       # miss rate for ReadSharedReq accesses
 system.l2c.demand_miss_rate::cpu0.inst       0.870410                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu0.data       0.980562                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu1.inst       0.870410                       # miss rate for demand accesses
@@ -1020,10 +1024,10 @@ system.l2c.avg_blocked_cycles::no_targets          nan                       # a
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq                2872                       # Transaction distribution
 system.membus.trans_dist::ReadResp               2872                       # Transaction distribution
 system.membus.trans_dist::ReadExReq               556                       # Transaction distribution
 system.membus.trans_dist::ReadExResp              556                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          2872                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         6856                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                   6856                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.physmem.port       219392                       # Cumulative packet size per connected master and slave (bytes)
@@ -1039,20 +1043,22 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                3428                       # Request fanout histogram
-system.toL2Bus.trans_dist::ReadReq               3148                       # Transaction distribution
 system.toL2Bus.trans_dist::ReadResp              3148                       # Transaction distribution
 system.toL2Bus.trans_dist::Writeback              116                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict             736                       # Transaction distribution
 system.toL2Bus.trans_dist::ReadExReq              556                       # Transaction distribution
 system.toL2Bus.trans_dist::ReadExResp             556                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side          926                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          955                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side          926                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          955                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side          926                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          955                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side          926                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          955                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total                  7524                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.trans_dist::ReadCleanReq          1852                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq         1296                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1078                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          987                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side         1078                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          987                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side         1078                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          987                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side         1078                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          987                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total                  8260                       # Packet count per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        29632                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side        31488                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        29632                       # Cumulative packet size per connected master and slave (bytes)
@@ -1063,7 +1069,7 @@ system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side
 system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side        31488                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size::total                 244480                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.snoops                               0                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples             3820                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::samples             4556                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::mean                   7                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::stdev                  0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
@@ -1074,11 +1080,11 @@ system.toL2Bus.snoop_fanout::3                      0      0.00%      0.00% # Re
 system.toL2Bus.snoop_fanout::4                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::5                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::6                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7                   3820    100.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7                   4556    100.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              7                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              7                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total               3820                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::total               4556                       # Request fanout histogram
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
index 098ebf393..7b3ac07e0 100644
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
@@ -87,7 +87,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -98,7 +98,6 @@ size=32768
 system=system
 tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
@@ -128,7 +127,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -139,7 +138,6 @@ size=32768
 system=system
 tags=system.cpu0.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
@@ -228,7 +226,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -239,7 +237,6 @@ size=32768
 system=system
 tags=system.cpu1.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.dcache_port
 mem_side=system.toL2Bus.slave[3]
@@ -269,7 +266,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -280,7 +277,6 @@ size=32768
 system=system
 tags=system.cpu1.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.icache_port
 mem_side=system.toL2Bus.slave[2]
@@ -369,7 +365,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -380,7 +376,6 @@ size=32768
 system=system
 tags=system.cpu2.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.dcache_port
 mem_side=system.toL2Bus.slave[5]
@@ -410,7 +405,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -421,7 +416,6 @@ size=32768
 system=system
 tags=system.cpu2.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.icache_port
 mem_side=system.toL2Bus.slave[4]
@@ -510,7 +504,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -521,7 +515,6 @@ size=32768
 system=system
 tags=system.cpu3.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.dcache_port
 mem_side=system.toL2Bus.slave[7]
@@ -551,7 +544,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -562,7 +555,6 @@ size=32768
 system=system
 tags=system.cpu3.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.icache_port
 mem_side=system.toL2Bus.slave[6]
@@ -634,7 +626,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -645,7 +637,6 @@ size=4194304
 system=system
 tags=system.l2c.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
index 42278656d..640568869 100644
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000728                       # Number of seconds simulated
-sim_ticks                                   727903500                       # Number of ticks simulated
-final_tick                                  727903500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                   727902500                       # Number of ticks simulated
+final_tick                                  727902500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 639540                       # Simulator instruction rate (inst/s)
-host_op_rate                                   639535                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              232760737                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 235576                       # Number of bytes of host memory used
-host_seconds                                     3.13                       # Real time elapsed on the host
+host_inst_rate                                 969116                       # Simulator instruction rate (inst/s)
+host_op_rate                                   969107                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              352708611                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 298060                       # Number of bytes of host memory used
+host_seconds                                     2.06                       # Real time elapsed on the host
 sim_insts                                     1999978                       # Number of instructions simulated
 sim_ops                                       1999978                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -36,29 +36,29 @@ system.physmem.num_reads::cpu2.data               454                       # Nu
 system.physmem.num_reads::cpu3.inst               403                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu3.data               454                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  3428                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst            35433268                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            39917379                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst            35433268                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data            39917379                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst            35433268                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data            39917379                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst            35433268                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data            39917379                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               301402590                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst       35433268                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst       35433268                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst       35433268                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst       35433268                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          141733073                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst           35433268                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           39917379                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst           35433268                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data           39917379                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst           35433268                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data           39917379                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst           35433268                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data           39917379                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              301402590                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst            35433317                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            39917434                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst            35433317                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data            39917434                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst            35433317                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data            39917434                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst            35433317                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data            39917434                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               301403004                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst       35433317                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst       35433317                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst       35433317                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst       35433317                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          141733268                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst           35433317                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           39917434                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst           35433317                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data           39917434                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst           35433317                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data           39917434                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst           35433317                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data           39917434                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              301403004                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dtb.fetch_hits                          0                       # ITB hits
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
@@ -93,7 +93,7 @@ system.cpu0.itb.data_misses                         0                       # DT
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
 system.cpu0.workload.num_syscalls                  18                       # Number of system calls
-system.cpu0.numCycles                         1455807                       # number of cpu cycles simulated
+system.cpu0.numCycles                         1455805                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.committedInsts                     500001                       # Number of instructions committed
@@ -112,7 +112,7 @@ system.cpu0.num_mem_refs                       180793                       # nu
 system.cpu0.num_load_insts                     124443                       # Number of load instructions
 system.cpu0.num_store_insts                     56350                       # Number of store instructions
 system.cpu0.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu0.num_busy_cycles                   1455807                       # Number of busy cycles
+system.cpu0.num_busy_cycles                   1455805                       # Number of busy cycles
 system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
 system.cpu0.Branches                            59023                       # Number of branches fetched
@@ -152,14 +152,14 @@ system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Cl
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::total                    500019                       # Class of executed instruction
 system.cpu0.dcache.tags.replacements               61                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          273.598283                       # Cycle average of tags in use
+system.cpu0.dcache.tags.tagsinuse          273.597897                       # Cycle average of tags in use
 system.cpu0.dcache.tags.total_refs             180312                       # Total number of references to valid blocks.
 system.cpu0.dcache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
 system.cpu0.dcache.tags.avg_refs           389.442765                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   273.598283                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.534372                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.534372                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   273.597897                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.534371                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.534371                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          402                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::1           33                       # Occupied blocks per task id
@@ -183,14 +183,14 @@ system.cpu0.dcache.demand_misses::cpu0.data          463                       #
 system.cpu0.dcache.demand_misses::total           463                       # number of demand (read+write) misses
 system.cpu0.dcache.overall_misses::cpu0.data          463                       # number of overall misses
 system.cpu0.dcache.overall_misses::total          463                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     17443000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total     17443000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     17442000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total     17442000                       # number of ReadReq miss cycles
 system.cpu0.dcache.WriteReq_miss_latency::cpu0.data      7645000                       # number of WriteReq miss cycles
 system.cpu0.dcache.WriteReq_miss_latency::total      7645000                       # number of WriteReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data     25088000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total     25088000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data     25088000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total     25088000                       # number of overall miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data     25087000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total     25087000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data     25087000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total     25087000                       # number of overall miss cycles
 system.cpu0.dcache.ReadReq_accesses::cpu0.data       124435                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.ReadReq_accesses::total       124435                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.WriteReq_accesses::cpu0.data        56340                       # number of WriteReq accesses(hits+misses)
@@ -207,14 +207,14 @@ system.cpu0.dcache.demand_miss_rate::cpu0.data     0.002561
 system.cpu0.dcache.demand_miss_rate::total     0.002561                       # miss rate for demand accesses
 system.cpu0.dcache.overall_miss_rate::cpu0.data     0.002561                       # miss rate for overall accesses
 system.cpu0.dcache.overall_miss_rate::total     0.002561                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 53836.419753                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 53836.419753                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 53833.333333                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 53833.333333                       # average ReadReq miss latency
 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data        55000                       # average WriteReq miss latency
 system.cpu0.dcache.WriteReq_avg_miss_latency::total        55000                       # average WriteReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 54185.745140                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 54185.745140                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 54185.745140                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 54185.745140                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 54183.585313                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 54183.585313                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 54183.585313                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 54183.585313                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -233,14 +233,14 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data          463
 system.cpu0.dcache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
 system.cpu0.dcache.overall_mshr_misses::cpu0.data          463                       # number of overall MSHR misses
 system.cpu0.dcache.overall_mshr_misses::total          463                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data     16957000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total     16957000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      7436500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total      7436500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     24393500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total     24393500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     24393500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total     24393500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data     17118000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total     17118000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      7506000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total      7506000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     24624000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total     24624000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     24624000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total     24624000                       # number of overall MSHR miss cycles
 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002604                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002604                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.002467                       # mshr miss rate for WriteReq accesses
@@ -249,24 +249,24 @@ system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002561
 system.cpu0.dcache.demand_mshr_miss_rate::total     0.002561                       # mshr miss rate for demand accesses
 system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002561                       # mshr miss rate for overall accesses
 system.cpu0.dcache.overall_mshr_miss_rate::total     0.002561                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 52336.419753                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 52336.419753                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data        53500                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total        53500                       # average WriteReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 52685.745140                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 52685.745140                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 52685.745140                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 52685.745140                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 52833.333333                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 52833.333333                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data        54000                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total        54000                       # average WriteReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 53183.585313                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 53183.585313                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 53183.585313                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 53183.585313                       # average overall mshr miss latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.icache.tags.replacements              152                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          216.437634                       # Cycle average of tags in use
+system.cpu0.icache.tags.tagsinuse          216.437309                       # Cycle average of tags in use
 system.cpu0.icache.tags.total_refs             499557                       # Total number of references to valid blocks.
 system.cpu0.icache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
 system.cpu0.icache.tags.avg_refs          1078.956803                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   216.437634                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.422730                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.422730                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   216.437309                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.422729                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.422729                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          311                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          311                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024     0.607422                       # Percentage of cache occupancy per task id
@@ -322,24 +322,24 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst          463
 system.cpu0.icache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
 system.cpu0.icache.overall_mshr_misses::cpu0.inst          463                       # number of overall MSHR misses
 system.cpu0.icache.overall_mshr_misses::total          463                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     22253000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total     22253000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     22253000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total     22253000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     22253000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total     22253000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     22484500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total     22484500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     22484500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total     22484500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     22484500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total     22484500                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.000926                       # mshr miss rate for ReadReq accesses
 system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.000926                       # mshr miss rate for ReadReq accesses
 system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.000926                       # mshr miss rate for demand accesses
 system.cpu0.icache.demand_mshr_miss_rate::total     0.000926                       # mshr miss rate for demand accesses
 system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.000926                       # mshr miss rate for overall accesses
 system.cpu0.icache.overall_mshr_miss_rate::total     0.000926                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 48062.634989                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 48062.634989                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 48062.634989                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 48062.634989                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 48062.634989                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 48062.634989                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 48562.634989                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 48562.634989                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 48562.634989                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 48562.634989                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 48562.634989                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 48562.634989                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
@@ -374,7 +374,7 @@ system.cpu1.itb.data_misses                         0                       # DT
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
 system.cpu1.workload.num_syscalls                  18                       # Number of system calls
-system.cpu1.numCycles                         1455807                       # number of cpu cycles simulated
+system.cpu1.numCycles                         1455805                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.committedInsts                     499997                       # Number of instructions committed
@@ -393,7 +393,7 @@ system.cpu1.num_mem_refs                       180792                       # nu
 system.cpu1.num_load_insts                     124443                       # Number of load instructions
 system.cpu1.num_store_insts                     56349                       # Number of store instructions
 system.cpu1.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu1.num_busy_cycles                   1455807                       # Number of busy cycles
+system.cpu1.num_busy_cycles                   1455805                       # Number of busy cycles
 system.cpu1.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu1.idle_fraction                           0                       # Percentage of idle cycles
 system.cpu1.Branches                            59022                       # Number of branches fetched
@@ -433,14 +433,14 @@ system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Cl
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::total                    500015                       # Class of executed instruction
 system.cpu1.dcache.tags.replacements               61                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          273.595522                       # Cycle average of tags in use
+system.cpu1.dcache.tags.tagsinuse          273.595136                       # Cycle average of tags in use
 system.cpu1.dcache.tags.total_refs             180311                       # Total number of references to valid blocks.
 system.cpu1.dcache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
 system.cpu1.dcache.tags.avg_refs           389.440605                       # Average number of references to valid blocks.
 system.cpu1.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   273.595522                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.534366                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.534366                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   273.595136                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.534365                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.534365                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_task_id_blocks::1024          402                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::1           33                       # Occupied blocks per task id
@@ -464,14 +464,14 @@ system.cpu1.dcache.demand_misses::cpu1.data          463                       #
 system.cpu1.dcache.demand_misses::total           463                       # number of demand (read+write) misses
 system.cpu1.dcache.overall_misses::cpu1.data          463                       # number of overall misses
 system.cpu1.dcache.overall_misses::total          463                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data     17443000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total     17443000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data     17442000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total     17442000                       # number of ReadReq miss cycles
 system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      7645000                       # number of WriteReq miss cycles
 system.cpu1.dcache.WriteReq_miss_latency::total      7645000                       # number of WriteReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data     25088000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total     25088000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data     25088000                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total     25088000                       # number of overall miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data     25087000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total     25087000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data     25087000                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total     25087000                       # number of overall miss cycles
 system.cpu1.dcache.ReadReq_accesses::cpu1.data       124435                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.ReadReq_accesses::total       124435                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.WriteReq_accesses::cpu1.data        56339                       # number of WriteReq accesses(hits+misses)
@@ -488,14 +488,14 @@ system.cpu1.dcache.demand_miss_rate::cpu1.data     0.002561
 system.cpu1.dcache.demand_miss_rate::total     0.002561                       # miss rate for demand accesses
 system.cpu1.dcache.overall_miss_rate::cpu1.data     0.002561                       # miss rate for overall accesses
 system.cpu1.dcache.overall_miss_rate::total     0.002561                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 53836.419753                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 53836.419753                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 53833.333333                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 53833.333333                       # average ReadReq miss latency
 system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data        55000                       # average WriteReq miss latency
 system.cpu1.dcache.WriteReq_avg_miss_latency::total        55000                       # average WriteReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 54185.745140                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 54185.745140                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 54185.745140                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 54185.745140                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 54183.585313                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 54183.585313                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 54183.585313                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 54183.585313                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -514,14 +514,14 @@ system.cpu1.dcache.demand_mshr_misses::cpu1.data          463
 system.cpu1.dcache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
 system.cpu1.dcache.overall_mshr_misses::cpu1.data          463                       # number of overall MSHR misses
 system.cpu1.dcache.overall_mshr_misses::total          463                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data     16957000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total     16957000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      7436500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total      7436500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data     24393500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total     24393500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data     24393500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total     24393500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data     17118000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total     17118000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      7506000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total      7506000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data     24624000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total     24624000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data     24624000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total     24624000                       # number of overall MSHR miss cycles
 system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.002604                       # mshr miss rate for ReadReq accesses
 system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.002604                       # mshr miss rate for ReadReq accesses
 system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.002467                       # mshr miss rate for WriteReq accesses
@@ -530,24 +530,24 @@ system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.002561
 system.cpu1.dcache.demand_mshr_miss_rate::total     0.002561                       # mshr miss rate for demand accesses
 system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.002561                       # mshr miss rate for overall accesses
 system.cpu1.dcache.overall_mshr_miss_rate::total     0.002561                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 52336.419753                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 52336.419753                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data        53500                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total        53500                       # average WriteReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 52685.745140                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 52685.745140                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 52685.745140                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 52685.745140                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 52833.333333                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 52833.333333                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data        54000                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total        54000                       # average WriteReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 53183.585313                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 53183.585313                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 53183.585313                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 53183.585313                       # average overall mshr miss latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.icache.tags.replacements              152                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          216.435498                       # Cycle average of tags in use
+system.cpu1.icache.tags.tagsinuse          216.435172                       # Cycle average of tags in use
 system.cpu1.icache.tags.total_refs             499553                       # Total number of references to valid blocks.
 system.cpu1.icache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
 system.cpu1.icache.tags.avg_refs          1078.948164                       # Average number of references to valid blocks.
 system.cpu1.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   216.435498                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.422726                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.422726                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   216.435172                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.422725                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.422725                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          311                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::2          311                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024     0.607422                       # Percentage of cache occupancy per task id
@@ -603,24 +603,24 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst          463
 system.cpu1.icache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
 system.cpu1.icache.overall_mshr_misses::cpu1.inst          463                       # number of overall MSHR misses
 system.cpu1.icache.overall_mshr_misses::total          463                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst     22258000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total     22258000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst     22258000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total     22258000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst     22258000                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total     22258000                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst     22489500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total     22489500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst     22489500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total     22489500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst     22489500                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total     22489500                       # number of overall MSHR miss cycles
 system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.000926                       # mshr miss rate for ReadReq accesses
 system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.000926                       # mshr miss rate for ReadReq accesses
 system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.000926                       # mshr miss rate for demand accesses
 system.cpu1.icache.demand_mshr_miss_rate::total     0.000926                       # mshr miss rate for demand accesses
 system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.000926                       # mshr miss rate for overall accesses
 system.cpu1.icache.overall_mshr_miss_rate::total     0.000926                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 48073.434125                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 48073.434125                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 48073.434125                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 48073.434125                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 48073.434125                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 48073.434125                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 48573.434125                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 48573.434125                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 48573.434125                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 48573.434125                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 48573.434125                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 48573.434125                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu2.dtb.fetch_hits                          0                       # ITB hits
 system.cpu2.dtb.fetch_misses                        0                       # ITB misses
@@ -655,7 +655,7 @@ system.cpu2.itb.data_misses                         0                       # DT
 system.cpu2.itb.data_acv                            0                       # DTB access violations
 system.cpu2.itb.data_accesses                       0                       # DTB accesses
 system.cpu2.workload.num_syscalls                  18                       # Number of system calls
-system.cpu2.numCycles                         1455807                       # number of cpu cycles simulated
+system.cpu2.numCycles                         1455805                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu2.committedInsts                     499992                       # Number of instructions committed
@@ -674,7 +674,7 @@ system.cpu2.num_mem_refs                       180792                       # nu
 system.cpu2.num_load_insts                     124443                       # Number of load instructions
 system.cpu2.num_store_insts                     56349                       # Number of store instructions
 system.cpu2.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu2.num_busy_cycles                   1455807                       # Number of busy cycles
+system.cpu2.num_busy_cycles                   1455805                       # Number of busy cycles
 system.cpu2.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu2.idle_fraction                           0                       # Percentage of idle cycles
 system.cpu2.Branches                            59022                       # Number of branches fetched
@@ -714,14 +714,14 @@ system.cpu2.op_class::IprAccess                     0      0.00%    100.00% # Cl
 system.cpu2.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
 system.cpu2.op_class::total                    500010                       # Class of executed instruction
 system.cpu2.dcache.tags.replacements               61                       # number of replacements
-system.cpu2.dcache.tags.tagsinuse          273.592761                       # Cycle average of tags in use
+system.cpu2.dcache.tags.tagsinuse          273.592374                       # Cycle average of tags in use
 system.cpu2.dcache.tags.total_refs             180311                       # Total number of references to valid blocks.
 system.cpu2.dcache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
 system.cpu2.dcache.tags.avg_refs           389.440605                       # Average number of references to valid blocks.
 system.cpu2.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.tags.occ_blocks::cpu2.data   273.592761                       # Average occupied blocks per requestor
-system.cpu2.dcache.tags.occ_percent::cpu2.data     0.534361                       # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total     0.534361                       # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_blocks::cpu2.data   273.592374                       # Average occupied blocks per requestor
+system.cpu2.dcache.tags.occ_percent::cpu2.data     0.534360                       # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_percent::total     0.534360                       # Average percentage of cache occupancy
 system.cpu2.dcache.tags.occ_task_id_blocks::1024          402                       # Occupied blocks per task id
 system.cpu2.dcache.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
 system.cpu2.dcache.tags.age_task_id_blocks_1024::1           33                       # Occupied blocks per task id
@@ -745,14 +745,14 @@ system.cpu2.dcache.demand_misses::cpu2.data          463                       #
 system.cpu2.dcache.demand_misses::total           463                       # number of demand (read+write) misses
 system.cpu2.dcache.overall_misses::cpu2.data          463                       # number of overall misses
 system.cpu2.dcache.overall_misses::total          463                       # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency::cpu2.data     17443000                       # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_latency::total     17443000                       # number of ReadReq miss cycles
+system.cpu2.dcache.ReadReq_miss_latency::cpu2.data     17442000                       # number of ReadReq miss cycles
+system.cpu2.dcache.ReadReq_miss_latency::total     17442000                       # number of ReadReq miss cycles
 system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      7645000                       # number of WriteReq miss cycles
 system.cpu2.dcache.WriteReq_miss_latency::total      7645000                       # number of WriteReq miss cycles
-system.cpu2.dcache.demand_miss_latency::cpu2.data     25088000                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_latency::total     25088000                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency::cpu2.data     25088000                       # number of overall miss cycles
-system.cpu2.dcache.overall_miss_latency::total     25088000                       # number of overall miss cycles
+system.cpu2.dcache.demand_miss_latency::cpu2.data     25087000                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.demand_miss_latency::total     25087000                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.overall_miss_latency::cpu2.data     25087000                       # number of overall miss cycles
+system.cpu2.dcache.overall_miss_latency::total     25087000                       # number of overall miss cycles
 system.cpu2.dcache.ReadReq_accesses::cpu2.data       124435                       # number of ReadReq accesses(hits+misses)
 system.cpu2.dcache.ReadReq_accesses::total       124435                       # number of ReadReq accesses(hits+misses)
 system.cpu2.dcache.WriteReq_accesses::cpu2.data        56339                       # number of WriteReq accesses(hits+misses)
@@ -769,14 +769,14 @@ system.cpu2.dcache.demand_miss_rate::cpu2.data     0.002561
 system.cpu2.dcache.demand_miss_rate::total     0.002561                       # miss rate for demand accesses
 system.cpu2.dcache.overall_miss_rate::cpu2.data     0.002561                       # miss rate for overall accesses
 system.cpu2.dcache.overall_miss_rate::total     0.002561                       # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 53836.419753                       # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_miss_latency::total 53836.419753                       # average ReadReq miss latency
+system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 53833.333333                       # average ReadReq miss latency
+system.cpu2.dcache.ReadReq_avg_miss_latency::total 53833.333333                       # average ReadReq miss latency
 system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data        55000                       # average WriteReq miss latency
 system.cpu2.dcache.WriteReq_avg_miss_latency::total        55000                       # average WriteReq miss latency
-system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 54185.745140                       # average overall miss latency
-system.cpu2.dcache.demand_avg_miss_latency::total 54185.745140                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 54185.745140                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::total 54185.745140                       # average overall miss latency
+system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 54183.585313                       # average overall miss latency
+system.cpu2.dcache.demand_avg_miss_latency::total 54183.585313                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 54183.585313                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::total 54183.585313                       # average overall miss latency
 system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -795,14 +795,14 @@ system.cpu2.dcache.demand_mshr_misses::cpu2.data          463
 system.cpu2.dcache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
 system.cpu2.dcache.overall_mshr_misses::cpu2.data          463                       # number of overall MSHR misses
 system.cpu2.dcache.overall_mshr_misses::total          463                       # number of overall MSHR misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data     16957000                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_latency::total     16957000                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      7436500                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::total      7436500                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data     24393500                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::total     24393500                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data     24393500                       # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::total     24393500                       # number of overall MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data     17118000                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::total     17118000                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      7506000                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::total      7506000                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data     24624000                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::total     24624000                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data     24624000                       # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::total     24624000                       # number of overall MSHR miss cycles
 system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.002604                       # mshr miss rate for ReadReq accesses
 system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.002604                       # mshr miss rate for ReadReq accesses
 system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.002467                       # mshr miss rate for WriteReq accesses
@@ -811,22 +811,22 @@ system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.002561
 system.cpu2.dcache.demand_mshr_miss_rate::total     0.002561                       # mshr miss rate for demand accesses
 system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.002561                       # mshr miss rate for overall accesses
 system.cpu2.dcache.overall_mshr_miss_rate::total     0.002561                       # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 52336.419753                       # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 52336.419753                       # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data        53500                       # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total        53500                       # average WriteReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 52685.745140                       # average overall mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::total 52685.745140                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 52685.745140                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 52685.745140                       # average overall mshr miss latency
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 52833.333333                       # average ReadReq mshr miss latency
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 52833.333333                       # average ReadReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data        54000                       # average WriteReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total        54000                       # average WriteReq mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 53183.585313                       # average overall mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::total 53183.585313                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 53183.585313                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::total 53183.585313                       # average overall mshr miss latency
 system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu2.icache.tags.replacements              152                       # number of replacements
-system.cpu2.icache.tags.tagsinuse          216.433362                       # Cycle average of tags in use
+system.cpu2.icache.tags.tagsinuse          216.433036                       # Cycle average of tags in use
 system.cpu2.icache.tags.total_refs             499548                       # Total number of references to valid blocks.
 system.cpu2.icache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
 system.cpu2.icache.tags.avg_refs          1078.937365                       # Average number of references to valid blocks.
 system.cpu2.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu2.icache.tags.occ_blocks::cpu2.inst   216.433362                       # Average occupied blocks per requestor
+system.cpu2.icache.tags.occ_blocks::cpu2.inst   216.433036                       # Average occupied blocks per requestor
 system.cpu2.icache.tags.occ_percent::cpu2.inst     0.422721                       # Average percentage of cache occupancy
 system.cpu2.icache.tags.occ_percent::total     0.422721                       # Average percentage of cache occupancy
 system.cpu2.icache.tags.occ_task_id_blocks::1024          311                       # Occupied blocks per task id
@@ -884,24 +884,24 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst          463
 system.cpu2.icache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
 system.cpu2.icache.overall_mshr_misses::cpu2.inst          463                       # number of overall MSHR misses
 system.cpu2.icache.overall_mshr_misses::total          463                       # number of overall MSHR misses
-system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst     22263000                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_latency::total     22263000                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst     22263000                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::total     22263000                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst     22263000                       # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::total     22263000                       # number of overall MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst     22494500                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_latency::total     22494500                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst     22494500                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::total     22494500                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst     22494500                       # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::total     22494500                       # number of overall MSHR miss cycles
 system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.000926                       # mshr miss rate for ReadReq accesses
 system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.000926                       # mshr miss rate for ReadReq accesses
 system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.000926                       # mshr miss rate for demand accesses
 system.cpu2.icache.demand_mshr_miss_rate::total     0.000926                       # mshr miss rate for demand accesses
 system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.000926                       # mshr miss rate for overall accesses
 system.cpu2.icache.overall_mshr_miss_rate::total     0.000926                       # mshr miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 48084.233261                       # average ReadReq mshr miss latency
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 48084.233261                       # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 48084.233261                       # average overall mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::total 48084.233261                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 48084.233261                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::total 48084.233261                       # average overall mshr miss latency
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 48584.233261                       # average ReadReq mshr miss latency
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 48584.233261                       # average ReadReq mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 48584.233261                       # average overall mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::total 48584.233261                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 48584.233261                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::total 48584.233261                       # average overall mshr miss latency
 system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu3.dtb.fetch_hits                          0                       # ITB hits
 system.cpu3.dtb.fetch_misses                        0                       # ITB misses
@@ -936,7 +936,7 @@ system.cpu3.itb.data_misses                         0                       # DT
 system.cpu3.itb.data_acv                            0                       # DTB access violations
 system.cpu3.itb.data_accesses                       0                       # DTB accesses
 system.cpu3.workload.num_syscalls                  18                       # Number of system calls
-system.cpu3.numCycles                         1455807                       # number of cpu cycles simulated
+system.cpu3.numCycles                         1455805                       # number of cpu cycles simulated
 system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu3.committedInsts                     499988                       # Number of instructions committed
@@ -955,7 +955,7 @@ system.cpu3.num_mem_refs                       180790                       # nu
 system.cpu3.num_load_insts                     124441                       # Number of load instructions
 system.cpu3.num_store_insts                     56349                       # Number of store instructions
 system.cpu3.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu3.num_busy_cycles                   1455807                       # Number of busy cycles
+system.cpu3.num_busy_cycles                   1455805                       # Number of busy cycles
 system.cpu3.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu3.idle_fraction                           0                       # Percentage of idle cycles
 system.cpu3.Branches                            59022                       # Number of branches fetched
@@ -995,12 +995,12 @@ system.cpu3.op_class::IprAccess                     0      0.00%    100.00% # Cl
 system.cpu3.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
 system.cpu3.op_class::total                    500006                       # Class of executed instruction
 system.cpu3.dcache.tags.replacements               61                       # number of replacements
-system.cpu3.dcache.tags.tagsinuse          273.589931                       # Cycle average of tags in use
+system.cpu3.dcache.tags.tagsinuse          273.589530                       # Cycle average of tags in use
 system.cpu3.dcache.tags.total_refs             180309                       # Total number of references to valid blocks.
 system.cpu3.dcache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
 system.cpu3.dcache.tags.avg_refs           389.436285                       # Average number of references to valid blocks.
 system.cpu3.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.tags.occ_blocks::cpu3.data   273.589931                       # Average occupied blocks per requestor
+system.cpu3.dcache.tags.occ_blocks::cpu3.data   273.589530                       # Average occupied blocks per requestor
 system.cpu3.dcache.tags.occ_percent::cpu3.data     0.534355                       # Average percentage of cache occupancy
 system.cpu3.dcache.tags.occ_percent::total     0.534355                       # Average percentage of cache occupancy
 system.cpu3.dcache.tags.occ_task_id_blocks::1024          402                       # Occupied blocks per task id
@@ -1026,14 +1026,14 @@ system.cpu3.dcache.demand_misses::cpu3.data          463                       #
 system.cpu3.dcache.demand_misses::total           463                       # number of demand (read+write) misses
 system.cpu3.dcache.overall_misses::cpu3.data          463                       # number of overall misses
 system.cpu3.dcache.overall_misses::total          463                       # number of overall misses
-system.cpu3.dcache.ReadReq_miss_latency::cpu3.data     17443500                       # number of ReadReq miss cycles
-system.cpu3.dcache.ReadReq_miss_latency::total     17443500                       # number of ReadReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      7645500                       # number of WriteReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::total      7645500                       # number of WriteReq miss cycles
-system.cpu3.dcache.demand_miss_latency::cpu3.data     25089000                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_latency::total     25089000                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.overall_miss_latency::cpu3.data     25089000                       # number of overall miss cycles
-system.cpu3.dcache.overall_miss_latency::total     25089000                       # number of overall miss cycles
+system.cpu3.dcache.ReadReq_miss_latency::cpu3.data     17442500                       # number of ReadReq miss cycles
+system.cpu3.dcache.ReadReq_miss_latency::total     17442500                       # number of ReadReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      7645000                       # number of WriteReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::total      7645000                       # number of WriteReq miss cycles
+system.cpu3.dcache.demand_miss_latency::cpu3.data     25087500                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.demand_miss_latency::total     25087500                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.overall_miss_latency::cpu3.data     25087500                       # number of overall miss cycles
+system.cpu3.dcache.overall_miss_latency::total     25087500                       # number of overall miss cycles
 system.cpu3.dcache.ReadReq_accesses::cpu3.data       124433                       # number of ReadReq accesses(hits+misses)
 system.cpu3.dcache.ReadReq_accesses::total       124433                       # number of ReadReq accesses(hits+misses)
 system.cpu3.dcache.WriteReq_accesses::cpu3.data        56339                       # number of WriteReq accesses(hits+misses)
@@ -1050,14 +1050,14 @@ system.cpu3.dcache.demand_miss_rate::cpu3.data     0.002561
 system.cpu3.dcache.demand_miss_rate::total     0.002561                       # miss rate for demand accesses
 system.cpu3.dcache.overall_miss_rate::cpu3.data     0.002561                       # miss rate for overall accesses
 system.cpu3.dcache.overall_miss_rate::total     0.002561                       # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 53837.962963                       # average ReadReq miss latency
-system.cpu3.dcache.ReadReq_avg_miss_latency::total 53837.962963                       # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 55003.597122                       # average WriteReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::total 55003.597122                       # average WriteReq miss latency
-system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 54187.904968                       # average overall miss latency
-system.cpu3.dcache.demand_avg_miss_latency::total 54187.904968                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 54187.904968                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::total 54187.904968                       # average overall miss latency
+system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 53834.876543                       # average ReadReq miss latency
+system.cpu3.dcache.ReadReq_avg_miss_latency::total 53834.876543                       # average ReadReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data        55000                       # average WriteReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::total        55000                       # average WriteReq miss latency
+system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 54184.665227                       # average overall miss latency
+system.cpu3.dcache.demand_avg_miss_latency::total 54184.665227                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 54184.665227                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::total 54184.665227                       # average overall miss latency
 system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1076,14 +1076,14 @@ system.cpu3.dcache.demand_mshr_misses::cpu3.data          463
 system.cpu3.dcache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
 system.cpu3.dcache.overall_mshr_misses::cpu3.data          463                       # number of overall MSHR misses
 system.cpu3.dcache.overall_mshr_misses::total          463                       # number of overall MSHR misses
-system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data     16957500                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_latency::total     16957500                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      7437000                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::total      7437000                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data     24394500                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::total     24394500                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data     24394500                       # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::total     24394500                       # number of overall MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data     17118500                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_latency::total     17118500                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      7506000                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::total      7506000                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data     24624500                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::total     24624500                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data     24624500                       # number of overall MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::total     24624500                       # number of overall MSHR miss cycles
 system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.002604                       # mshr miss rate for ReadReq accesses
 system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.002604                       # mshr miss rate for ReadReq accesses
 system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.002467                       # mshr miss rate for WriteReq accesses
@@ -1092,24 +1092,24 @@ system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.002561
 system.cpu3.dcache.demand_mshr_miss_rate::total     0.002561                       # mshr miss rate for demand accesses
 system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.002561                       # mshr miss rate for overall accesses
 system.cpu3.dcache.overall_mshr_miss_rate::total     0.002561                       # mshr miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 52337.962963                       # average ReadReq mshr miss latency
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 52337.962963                       # average ReadReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 53503.597122                       # average WriteReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 53503.597122                       # average WriteReq mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 52687.904968                       # average overall mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::total 52687.904968                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 52687.904968                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::total 52687.904968                       # average overall mshr miss latency
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 52834.876543                       # average ReadReq mshr miss latency
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 52834.876543                       # average ReadReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data        54000                       # average WriteReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total        54000                       # average WriteReq mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 53184.665227                       # average overall mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::total 53184.665227                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 53184.665227                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::total 53184.665227                       # average overall mshr miss latency
 system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu3.icache.tags.replacements              152                       # number of replacements
-system.cpu3.icache.tags.tagsinuse          216.431169                       # Cycle average of tags in use
+system.cpu3.icache.tags.tagsinuse          216.430826                       # Cycle average of tags in use
 system.cpu3.icache.tags.total_refs             499544                       # Total number of references to valid blocks.
 system.cpu3.icache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
 system.cpu3.icache.tags.avg_refs          1078.928726                       # Average number of references to valid blocks.
 system.cpu3.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu3.icache.tags.occ_blocks::cpu3.inst   216.431169                       # Average occupied blocks per requestor
-system.cpu3.icache.tags.occ_percent::cpu3.inst     0.422717                       # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_percent::total     0.422717                       # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_blocks::cpu3.inst   216.430826                       # Average occupied blocks per requestor
+system.cpu3.icache.tags.occ_percent::cpu3.inst     0.422716                       # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_percent::total     0.422716                       # Average percentage of cache occupancy
 system.cpu3.icache.tags.occ_task_id_blocks::1024          311                       # Occupied blocks per task id
 system.cpu3.icache.tags.age_task_id_blocks_1024::2          311                       # Occupied blocks per task id
 system.cpu3.icache.tags.occ_task_id_percent::1024     0.607422                       # Percentage of cache occupancy per task id
@@ -1127,12 +1127,12 @@ system.cpu3.icache.demand_misses::cpu3.inst          463                       #
 system.cpu3.icache.demand_misses::total           463                       # number of demand (read+write) misses
 system.cpu3.icache.overall_misses::cpu3.inst          463                       # number of overall misses
 system.cpu3.icache.overall_misses::total          463                       # number of overall misses
-system.cpu3.icache.ReadReq_miss_latency::cpu3.inst     22962500                       # number of ReadReq miss cycles
-system.cpu3.icache.ReadReq_miss_latency::total     22962500                       # number of ReadReq miss cycles
-system.cpu3.icache.demand_miss_latency::cpu3.inst     22962500                       # number of demand (read+write) miss cycles
-system.cpu3.icache.demand_miss_latency::total     22962500                       # number of demand (read+write) miss cycles
-system.cpu3.icache.overall_miss_latency::cpu3.inst     22962500                       # number of overall miss cycles
-system.cpu3.icache.overall_miss_latency::total     22962500                       # number of overall miss cycles
+system.cpu3.icache.ReadReq_miss_latency::cpu3.inst     22963000                       # number of ReadReq miss cycles
+system.cpu3.icache.ReadReq_miss_latency::total     22963000                       # number of ReadReq miss cycles
+system.cpu3.icache.demand_miss_latency::cpu3.inst     22963000                       # number of demand (read+write) miss cycles
+system.cpu3.icache.demand_miss_latency::total     22963000                       # number of demand (read+write) miss cycles
+system.cpu3.icache.overall_miss_latency::cpu3.inst     22963000                       # number of overall miss cycles
+system.cpu3.icache.overall_miss_latency::total     22963000                       # number of overall miss cycles
 system.cpu3.icache.ReadReq_accesses::cpu3.inst       500007                       # number of ReadReq accesses(hits+misses)
 system.cpu3.icache.ReadReq_accesses::total       500007                       # number of ReadReq accesses(hits+misses)
 system.cpu3.icache.demand_accesses::cpu3.inst       500007                       # number of demand (read+write) accesses
@@ -1145,12 +1145,12 @@ system.cpu3.icache.demand_miss_rate::cpu3.inst     0.000926
 system.cpu3.icache.demand_miss_rate::total     0.000926                       # miss rate for demand accesses
 system.cpu3.icache.overall_miss_rate::cpu3.inst     0.000926                       # miss rate for overall accesses
 system.cpu3.icache.overall_miss_rate::total     0.000926                       # miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 49595.032397                       # average ReadReq miss latency
-system.cpu3.icache.ReadReq_avg_miss_latency::total 49595.032397                       # average ReadReq miss latency
-system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 49595.032397                       # average overall miss latency
-system.cpu3.icache.demand_avg_miss_latency::total 49595.032397                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 49595.032397                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::total 49595.032397                       # average overall miss latency
+system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 49596.112311                       # average ReadReq miss latency
+system.cpu3.icache.ReadReq_avg_miss_latency::total 49596.112311                       # average ReadReq miss latency
+system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 49596.112311                       # average overall miss latency
+system.cpu3.icache.demand_avg_miss_latency::total 49596.112311                       # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 49596.112311                       # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::total 49596.112311                       # average overall miss latency
 system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1165,40 +1165,40 @@ system.cpu3.icache.demand_mshr_misses::cpu3.inst          463
 system.cpu3.icache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
 system.cpu3.icache.overall_mshr_misses::cpu3.inst          463                       # number of overall MSHR misses
 system.cpu3.icache.overall_mshr_misses::total          463                       # number of overall MSHR misses
-system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst     22268000                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_latency::total     22268000                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst     22268000                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::total     22268000                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst     22268000                       # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::total     22268000                       # number of overall MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst     22500000                       # number of ReadReq MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_latency::total     22500000                       # number of ReadReq MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst     22500000                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::total     22500000                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst     22500000                       # number of overall MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::total     22500000                       # number of overall MSHR miss cycles
 system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.000926                       # mshr miss rate for ReadReq accesses
 system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.000926                       # mshr miss rate for ReadReq accesses
 system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.000926                       # mshr miss rate for demand accesses
 system.cpu3.icache.demand_mshr_miss_rate::total     0.000926                       # mshr miss rate for demand accesses
 system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.000926                       # mshr miss rate for overall accesses
 system.cpu3.icache.overall_mshr_miss_rate::total     0.000926                       # mshr miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 48095.032397                       # average ReadReq mshr miss latency
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 48095.032397                       # average ReadReq mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 48095.032397                       # average overall mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::total 48095.032397                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 48095.032397                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::total 48095.032397                       # average overall mshr miss latency
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 48596.112311                       # average ReadReq mshr miss latency
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 48596.112311                       # average ReadReq mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 48596.112311                       # average overall mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::total 48596.112311                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 48596.112311                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::total 48596.112311                       # average overall mshr miss latency
 system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.l2c.tags.replacements                        0                       # number of replacements
-system.l2c.tags.tagsinuse                 1943.831902                       # Cycle average of tags in use
-system.l2c.tags.total_refs                        332                       # Total number of references to valid blocks.
+system.l2c.tags.tagsinuse                 1943.822879                       # Cycle average of tags in use
+system.l2c.tags.total_refs                       1068                       # Total number of references to valid blocks.
 system.l2c.tags.sampled_refs                     2932                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     0.113233                       # Average number of references to valid blocks.
+system.l2c.tags.avg_refs                     0.364256                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks      17.239792                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst      265.090633                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data      216.564822                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      265.087863                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      216.562658                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst      265.085095                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data      216.560494                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst      265.082241                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data      216.558304                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::writebacks      17.239740                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst      265.089371                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data      216.563852                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      265.086602                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      216.561689                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst      265.083834                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data      216.559525                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.inst      265.080948                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.data      216.557319                       # Average occupied blocks per requestor
 system.l2c.tags.occ_percent::writebacks      0.000263                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.inst       0.004045                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.data       0.003305                       # Average percentage of cache occupancy
@@ -1208,25 +1208,26 @@ system.l2c.tags.occ_percent::cpu2.inst       0.004045                       # Av
 system.l2c.tags.occ_percent::cpu2.data       0.003304                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu3.inst       0.004045                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu3.data       0.003304                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.029661                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.029660                       # Average percentage of cache occupancy
 system.l2c.tags.occ_task_id_blocks::1024         2932                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::0            4                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::1           24                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::2         2904                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_percent::1024     0.044739                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                    34048                       # Number of tag accesses
-system.l2c.tags.data_accesses                   34048                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.inst                 60                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst                 60                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst                 60                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.inst                 60                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                    276                       # number of ReadReq hits
+system.l2c.tags.tag_accesses                    39936                       # Number of tag accesses
+system.l2c.tags.data_accesses                   39936                       # Number of data accesses
 system.l2c.Writeback_hits::writebacks             116                       # number of Writeback hits
 system.l2c.Writeback_hits::total                  116                       # number of Writeback hits
+system.l2c.ReadCleanReq_hits::cpu0.inst            60                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu1.inst            60                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu2.inst            60                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu3.inst            60                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::total               240                       # number of ReadCleanReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data            9                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data            9                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu2.data            9                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu3.data            9                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total               36                       # number of ReadSharedReq hits
 system.l2c.demand_hits::cpu0.inst                  60                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu0.data                   9                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu1.inst                  60                       # number of demand (read+write) hits
@@ -1245,20 +1246,21 @@ system.l2c.overall_hits::cpu2.data                  9                       # nu
 system.l2c.overall_hits::cpu3.inst                 60                       # number of overall hits
 system.l2c.overall_hits::cpu3.data                  9                       # number of overall hits
 system.l2c.overall_hits::total                    276                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst              403                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data              315                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst              403                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data              315                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst              403                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data              315                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.inst              403                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.data              315                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                 2872                       # number of ReadReq misses
 system.l2c.ReadExReq_misses::cpu0.data            139                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::cpu1.data            139                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::cpu2.data            139                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::cpu3.data            139                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::total                556                       # number of ReadExReq misses
+system.l2c.ReadCleanReq_misses::cpu0.inst          403                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu1.inst          403                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu2.inst          403                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu3.inst          403                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::total            1612                       # number of ReadCleanReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data          315                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data          315                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu2.data          315                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu3.data          315                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total           1260                       # number of ReadSharedReq misses
 system.l2c.demand_misses::cpu0.inst               403                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.data               454                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu1.inst               403                       # number of demand (read+write) misses
@@ -1277,47 +1279,39 @@ system.l2c.overall_misses::cpu2.data              454                       # nu
 system.l2c.overall_misses::cpu3.inst              403                       # number of overall misses
 system.l2c.overall_misses::cpu3.data              454                       # number of overall misses
 system.l2c.overall_misses::total                 3428                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst     21158500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data     16537500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst     21164500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data     16537500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.inst     21169000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.data     16538500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3.inst     21172000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3.data     16539000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total      150816500                       # number of ReadReq miss cycles
 system.l2c.ReadExReq_miss_latency::cpu0.data      7297500                       # number of ReadExReq miss cycles
 system.l2c.ReadExReq_miss_latency::cpu1.data      7297500                       # number of ReadExReq miss cycles
 system.l2c.ReadExReq_miss_latency::cpu2.data      7297500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3.data      7298000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total     29190500                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst     21158500                       # number of demand (read+write) miss cycles
+system.l2c.ReadExReq_miss_latency::cpu3.data      7297500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total     29190000                       # number of ReadExReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu0.inst     21159000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu1.inst     21164000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu2.inst     21168500                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu3.inst     21172500                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::total     84664000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.data     16537500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data     16537500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu2.data     16537500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu3.data     16538000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total     66150500                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst     21159000                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu0.data     23835000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst     21164500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst     21164000                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu1.data     23835000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst     21169000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data     23836000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.inst     21172000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.data     23837000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total       180007000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst     21158500                       # number of overall miss cycles
+system.l2c.demand_miss_latency::cpu2.inst     21168500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data     23835000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.inst     21172500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.data     23835500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total       180004500                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst     21159000                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu0.data     23835000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst     21164500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst     21164000                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu1.data     23835000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst     21169000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data     23836000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.inst     21172000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.data     23837000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total      180007000                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.inst            463                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data            324                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst            463                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data            324                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst            463                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.data            324                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.inst            463                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.data            324                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total               3148                       # number of ReadReq accesses(hits+misses)
+system.l2c.overall_miss_latency::cpu2.inst     21168500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data     23835000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.inst     21172500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.data     23835500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total      180004500                       # number of overall miss cycles
 system.l2c.Writeback_accesses::writebacks          116                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_accesses::total              116                       # number of Writeback accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu0.data          139                       # number of ReadExReq accesses(hits+misses)
@@ -1325,6 +1319,16 @@ system.l2c.ReadExReq_accesses::cpu1.data          139                       # nu
 system.l2c.ReadExReq_accesses::cpu2.data          139                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu3.data          139                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::total              556                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu0.inst          463                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu1.inst          463                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu2.inst          463                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu3.inst          463                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total          1852                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data          324                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data          324                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu2.data          324                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu3.data          324                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total         1296                       # number of ReadSharedReq accesses(hits+misses)
 system.l2c.demand_accesses::cpu0.inst             463                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu0.data             463                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu1.inst             463                       # number of demand (read+write) accesses
@@ -1343,20 +1347,21 @@ system.l2c.overall_accesses::cpu2.data            463                       # nu
 system.l2c.overall_accesses::cpu3.inst            463                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu3.data            463                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total               3704                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.870410                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.972222                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.870410                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.972222                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst      0.870410                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data      0.972222                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.inst      0.870410                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.data      0.972222                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.912325                       # miss rate for ReadReq accesses
 system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.870410                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.870410                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.870410                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.870410                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.870410                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.972222                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.972222                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.972222                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.972222                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.972222                       # miss rate for ReadSharedReq accesses
 system.l2c.demand_miss_rate::cpu0.inst       0.870410                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu0.data       0.980562                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu1.inst       0.870410                       # miss rate for demand accesses
@@ -1375,38 +1380,39 @@ system.l2c.overall_miss_rate::cpu2.data      0.980562                       # mi
 system.l2c.overall_miss_rate::cpu3.inst      0.870410                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu3.data      0.980562                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::total          0.925486                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52502.481390                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data        52500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52517.369727                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data        52500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst 52528.535980                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.data 52503.174603                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.inst 52535.980149                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.data 52504.761905                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52512.708914                       # average ReadReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::cpu0.data        52500                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::cpu1.data        52500                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::cpu2.data        52500                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52503.597122                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 52500.899281                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 52502.481390                       # average overall miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3.data        52500                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total        52500                       # average ReadExReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 52503.722084                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 52516.129032                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 52527.295285                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 52537.220844                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 52521.091811                       # average ReadCleanReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data        52500                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data        52500                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data        52500                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 52501.587302                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 52500.396825                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 52503.722084                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu0.data        52500                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 52517.369727                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 52516.129032                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu1.data        52500                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 52528.535980                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 52502.202643                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.inst 52535.980149                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.data 52504.405286                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52510.793466                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 52502.481390                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 52527.295285                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data        52500                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.inst 52537.220844                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.data 52501.101322                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52510.064177                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 52503.722084                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.data        52500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 52517.369727                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 52516.129032                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.data        52500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 52528.535980                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 52502.202643                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.inst 52535.980149                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.data 52504.405286                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52510.793466                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 52527.295285                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data        52500                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.inst 52537.220844                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.data 52501.101322                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52510.064177                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1415,20 +1421,21 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.ReadReq_mshr_misses::cpu0.inst          403                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data          315                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst          403                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data          315                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.inst          403                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.data          315                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3.inst          403                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3.data          315                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total            2872                       # number of ReadReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::cpu0.data          139                       # number of ReadExReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::cpu1.data          139                       # number of ReadExReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::cpu2.data          139                       # number of ReadExReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::cpu3.data          139                       # number of ReadExReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::total           556                       # number of ReadExReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu0.inst          403                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu1.inst          403                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu2.inst          403                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu3.inst          403                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::total         1612                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.data          315                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data          315                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu2.data          315                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu3.data          315                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total         1260                       # number of ReadSharedReq MSHR misses
 system.l2c.demand_mshr_misses::cpu0.inst          403                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu0.data          454                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu1.inst          403                       # number of demand (read+write) MSHR misses
@@ -1447,52 +1454,54 @@ system.l2c.overall_mshr_misses::cpu2.data          454                       # n
 system.l2c.overall_mshr_misses::cpu3.inst          403                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu3.data          454                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::total            3428                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst     16321500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data     12757500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     16328500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data     12757500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.inst     16333000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.data     12758500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3.inst     16335500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3.data     12758500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total    116350500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      5629500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data      5629500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data      5629500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu3.data      5629500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total     22518000                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst     16321500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data     18387000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst     16328500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data     18387000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst     16333000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data     18388000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.inst     16335500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.data     18388000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total    138868500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst     16321500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data     18387000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst     16328500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data     18387000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst     16333000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data     18388000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.inst     16335500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.data     18388000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total    138868500                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.870410                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.972222                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.870410                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.972222                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.870410                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.972222                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3.inst     0.870410                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3.data     0.972222                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.912325                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      5907500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data      5907500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data      5907500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3.data      5907500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total     23630000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst     17129000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst     17134000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst     17138500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst     17142500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total     68544000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data     13387500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data     13387500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data     13387500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data     13388000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total     53550500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst     17129000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data     19295000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst     17134000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data     19295000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst     17138500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data     19295000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.inst     17142500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.data     19295500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total    145724500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst     17129000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data     19295000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst     17134000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data     19295000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst     17138500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data     19295000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.inst     17142500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.data     19295500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total    145724500                       # number of overall MSHR miss cycles
 system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.870410                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.870410                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.870410                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.870410                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.870410                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.972222                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.972222                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.972222                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.972222                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.972222                       # mshr miss rate for ReadSharedReq accesses
 system.l2c.demand_mshr_miss_rate::cpu0.inst     0.870410                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu0.data     0.980562                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu1.inst     0.870410                       # mshr miss rate for demand accesses
@@ -1511,76 +1520,79 @@ system.l2c.overall_mshr_miss_rate::cpu2.data     0.980562
 system.l2c.overall_mshr_miss_rate::cpu3.inst     0.870410                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu3.data     0.980562                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::total     0.925486                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst        40500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data        40500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40517.369727                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data        40500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40528.535980                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40503.174603                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40534.739454                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40503.174603                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40512.012535                       # average ReadReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data        40500                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data        40500                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data        40500                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data        40500                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total        40500                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst        40500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data        40500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40517.369727                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data        40500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40528.535980                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40502.202643                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40534.739454                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40502.202643                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40510.064177                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst        40500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data        40500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40517.369727                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data        40500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40528.535980                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40502.202643                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40534.739454                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40502.202643                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40510.064177                       # average overall mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data        42500                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data        42500                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data        42500                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data        42500                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total        42500                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42503.722084                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 42516.129032                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 42527.295285                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 42537.220844                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 42521.091811                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data        42500                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data        42500                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data        42500                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 42501.587302                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 42500.396825                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42503.722084                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data        42500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42516.129032                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data        42500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 42527.295285                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data        42500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 42537.220844                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 42501.101322                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 42510.064177                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42503.722084                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data        42500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42516.129032                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data        42500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 42527.295285                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data        42500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 42537.220844                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 42501.101322                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 42510.064177                       # average overall mshr miss latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq                2872                       # Transaction distribution
 system.membus.trans_dist::ReadResp               2872                       # Transaction distribution
 system.membus.trans_dist::ReadExReq               556                       # Transaction distribution
 system.membus.trans_dist::ReadExResp              556                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          2872                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         6856                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                   6856                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.physmem.port       219392                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                  219392                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              3437                       # Request fanout histogram
+system.membus.snoop_fanout::samples              3433                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    3437    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    3433    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                3437                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             3440968                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                3433                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             3438468                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
 system.membus.respLayer1.occupancy           17142500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              2.4                       # Layer utilization (%)
-system.toL2Bus.trans_dist::ReadReq               3148                       # Transaction distribution
 system.toL2Bus.trans_dist::ReadResp              3148                       # Transaction distribution
 system.toL2Bus.trans_dist::Writeback              116                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict             736                       # Transaction distribution
 system.toL2Bus.trans_dist::ReadExReq              556                       # Transaction distribution
 system.toL2Bus.trans_dist::ReadExResp             556                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side          926                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          955                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side          926                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          955                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side          926                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          955                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side          926                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          955                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total                  7524                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.trans_dist::ReadCleanReq          1852                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq         1296                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1078                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          987                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side         1078                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          987                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side         1078                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          987                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side         1078                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          987                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total                  8260                       # Packet count per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        29632                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side        31488                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        29632                       # Cumulative packet size per connected master and slave (bytes)
@@ -1591,7 +1603,7 @@ system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side
 system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side        31488                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size::total                 244480                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.snoops                               0                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples             3820                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::samples             4556                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::mean                   7                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::stdev                  0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
@@ -1602,13 +1614,13 @@ system.toL2Bus.snoop_fanout::3                      0      0.00%      0.00% # Re
 system.toL2Bus.snoop_fanout::4                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::5                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::6                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7                   3820    100.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7                   4556    100.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              7                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              7                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total               3820                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy            2026000                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total               4556                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy            2394000                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.3                       # Layer utilization (%)
 system.toL2Bus.respLayer0.occupancy            694500                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
index 7a136e99f..679d3d472 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
@@ -1,48 +1,50 @@
+Redirecting stdout to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Apr 22 2015 08:08:31
-gem5 started Apr 22 2015 08:17:28
-gem5 executing on phenom
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
+gem5 compiled Jul  3 2015 17:16:20
+gem5 started Jul  3 2015 17:20:44
+gem5 executing on ribera.cs.wisc.edu
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re /scratch/nilay/GEM5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Init done
 [Iteration 1, Thread 1] Got lock
 [Iteration 1, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 1, Thread 2] Got lock
-[Iteration 1, Thread 2] Critical section done, previously next=1, now next=2
 [Iteration 1, Thread 3] Got lock
-[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 1, Thread 2] Got lock
+[Iteration 1, Thread 2] Critical section done, previously next=3, now next=2
 Iteration 1 completed
-[Iteration 2, Thread 2] Got lock
-[Iteration 2, Thread 2] Critical section done, previously next=0, now next=2
 [Iteration 2, Thread 3] Got lock
-[Iteration 2, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 2, Thread 2] Got lock
+[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2
 [Iteration 2, Thread 1] Got lock
-[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1
 Iteration 2 completed
+[Iteration 3, Thread 2] Got lock
+[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2
 [Iteration 3, Thread 3] Got lock
-[Iteration 3, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 3, Thread 3] Critical section done, previously next=2, now next=3
 [Iteration 3, Thread 1] Got lock
 [Iteration 3, Thread 1] Critical section done, previously next=3, now next=1
-[Iteration 3, Thread 2] Got lock
-[Iteration 3, Thread 2] Critical section done, previously next=1, now next=2
 Iteration 3 completed
-[Iteration 4, Thread 2] Got lock
-[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2
 [Iteration 4, Thread 3] Got lock
-[Iteration 4, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 4, Thread 3] Critical section done, previously next=0, now next=3
 [Iteration 4, Thread 1] Got lock
 [Iteration 4, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 4, Thread 2] Got lock
+[Iteration 4, Thread 2] Critical section done, previously next=1, now next=2
 Iteration 4 completed
-[Iteration 5, Thread 1] Got lock
-[Iteration 5, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 5, Thread 2] Got lock
-[Iteration 5, Thread 2] Critical section done, previously next=1, now next=2
 [Iteration 5, Thread 3] Got lock
-[Iteration 5, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 5, Thread 2] Got lock
+[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 5, Thread 1] Got lock
+[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1
 Iteration 5 completed
 [Iteration 6, Thread 3] Got lock
 [Iteration 6, Thread 3] Critical section done, previously next=0, now next=3
@@ -51,12 +53,12 @@ Iteration 5 completed
 [Iteration 6, Thread 2] Got lock
 [Iteration 6, Thread 2] Critical section done, previously next=1, now next=2
 Iteration 6 completed
-[Iteration 7, Thread 2] Got lock
-[Iteration 7, Thread 2] Critical section done, previously next=0, now next=2
 [Iteration 7, Thread 1] Got lock
-[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1
 [Iteration 7, Thread 3] Got lock
 [Iteration 7, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 7, Thread 2] Got lock
+[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2
 Iteration 7 completed
 [Iteration 8, Thread 3] Got lock
 [Iteration 8, Thread 3] Critical section done, previously next=0, now next=3
@@ -65,19 +67,19 @@ Iteration 7 completed
 [Iteration 8, Thread 2] Got lock
 [Iteration 8, Thread 2] Critical section done, previously next=1, now next=2
 Iteration 8 completed
-[Iteration 9, Thread 2] Got lock
-[Iteration 9, Thread 2] Critical section done, previously next=0, now next=2
 [Iteration 9, Thread 1] Got lock
-[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 9, Thread 1] Critical section done, previously next=0, now next=1
 [Iteration 9, Thread 3] Got lock
 [Iteration 9, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 9, Thread 2] Got lock
+[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2
 Iteration 9 completed
-[Iteration 10, Thread 3] Got lock
-[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3
 [Iteration 10, Thread 1] Got lock
-[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 10, Thread 3] Got lock
+[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3
 [Iteration 10, Thread 2] Got lock
-[Iteration 10, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2
 Iteration 10 completed
 PASSED :-)
-Exiting @ tick 107944000 because target called exit()
+Exiting @ tick 107900000 because target called exit()
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr
index 215e9ea82..8a9724ab2 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr
@@ -1,85 +1,80 @@
 warn: rounding error > tolerance
-    0.072760 rounded to 0
+    1.250000 rounded to 1
 warn: rounding error > tolerance
-    0.072760 rounded to 0
+    1.250000 rounded to 1
 warn: rounding error > tolerance
-    0.072760 rounded to 0
-warn: rounding error > tolerance
-    0.072760 rounded to 0
-warn: rounding error > tolerance
-    0.072760 rounded to 0
-warn: rounding error > tolerance
-    0.072760 rounded to 0
-system.cpu2: completed 10000 read, 5361 write accesses @731568
-system.cpu5: completed 10000 read, 5557 write accesses @735340
-system.cpu3: completed 10000 read, 5535 write accesses @738863
-system.cpu6: completed 10000 read, 5476 write accesses @748316
-system.cpu0: completed 10000 read, 5560 write accesses @752250
-system.cpu4: completed 10000 read, 5465 write accesses @757289
-system.cpu7: completed 10000 read, 5564 write accesses @760144
-system.cpu1: completed 10000 read, 5530 write accesses @768416
-system.cpu5: completed 20000 read, 11151 write accesses @1477095
-system.cpu2: completed 20000 read, 10827 write accesses @1478088
-system.cpu3: completed 20000 read, 11078 write accesses @1481757
-system.cpu0: completed 20000 read, 11117 write accesses @1493889
-system.cpu6: completed 20000 read, 11080 write accesses @1512346
-system.cpu1: completed 20000 read, 11091 write accesses @1512763
-system.cpu4: completed 20000 read, 10986 write accesses @1520589
-system.cpu7: completed 20000 read, 11078 write accesses @1523748
-system.cpu5: completed 30000 read, 16568 write accesses @2200051
-system.cpu3: completed 30000 read, 16616 write accesses @2221845
-system.cpu2: completed 30000 read, 16217 write accesses @2232672
-system.cpu0: completed 30000 read, 16692 write accesses @2249618
-system.cpu1: completed 30000 read, 16648 write accesses @2263101
-system.cpu6: completed 30000 read, 16745 write accesses @2274150
-system.cpu4: completed 30000 read, 16620 write accesses @2276386
-system.cpu7: completed 30000 read, 16733 write accesses @2277359
-system.cpu5: completed 40000 read, 21987 write accesses @2947352
-system.cpu3: completed 40000 read, 22027 write accesses @2968674
-system.cpu1: completed 40000 read, 22148 write accesses @2995890
-system.cpu0: completed 40000 read, 22166 write accesses @2998152
-system.cpu2: completed 40000 read, 21828 write accesses @3001342
-system.cpu7: completed 40000 read, 22152 write accesses @3022463
-system.cpu6: completed 40000 read, 22388 write accesses @3028895
-system.cpu4: completed 40000 read, 22197 write accesses @3031091
-system.cpu5: completed 50000 read, 27444 write accesses @3696748
-system.cpu3: completed 50000 read, 27708 write accesses @3723471
-system.cpu1: completed 50000 read, 27649 write accesses @3746058
-system.cpu0: completed 50000 read, 27719 write accesses @3747410
-system.cpu2: completed 50000 read, 27424 write accesses @3760076
-system.cpu7: completed 50000 read, 27568 write accesses @3771426
-system.cpu6: completed 50000 read, 28012 write accesses @3777023
-system.cpu4: completed 50000 read, 27741 write accesses @3802071
-system.cpu5: completed 60000 read, 33062 write accesses @4446684
-system.cpu3: completed 60000 read, 33331 write accesses @4487796
-system.cpu2: completed 60000 read, 33035 write accesses @4498626
-system.cpu0: completed 60000 read, 33211 write accesses @4505229
-system.cpu1: completed 60000 read, 33219 write accesses @4525223
-system.cpu6: completed 60000 read, 33545 write accesses @4528416
-system.cpu7: completed 60000 read, 33210 write accesses @4528425
-system.cpu4: completed 60000 read, 33325 write accesses @4560641
-system.cpu5: completed 70000 read, 38698 write accesses @5188287
-system.cpu2: completed 70000 read, 38579 write accesses @5235379
-system.cpu7: completed 70000 read, 38633 write accesses @5255909
-system.cpu0: completed 70000 read, 38682 write accesses @5255973
-system.cpu6: completed 70000 read, 38964 write accesses @5261147
-system.cpu3: completed 70000 read, 38993 write accesses @5267174
-system.cpu1: completed 70000 read, 38888 write accesses @5283161
-system.cpu4: completed 70000 read, 38789 write accesses @5300670
-system.cpu5: completed 80000 read, 44039 write accesses @5937946
-system.cpu2: completed 80000 read, 43995 write accesses @5990383
-system.cpu7: completed 80000 read, 44179 write accesses @5992827
-system.cpu0: completed 80000 read, 44154 write accesses @6000956
-system.cpu6: completed 80000 read, 44514 write accesses @6013988
-system.cpu3: completed 80000 read, 44595 write accesses @6025710
-system.cpu1: completed 80000 read, 44663 write accesses @6042332
-system.cpu4: completed 80000 read, 44390 write accesses @6048987
-system.cpu5: completed 90000 read, 49553 write accesses @6694237
-system.cpu7: completed 90000 read, 49635 write accesses @6734659
-system.cpu2: completed 90000 read, 49508 write accesses @6735285
-system.cpu0: completed 90000 read, 49652 write accesses @6748849
-system.cpu6: completed 90000 read, 50083 write accesses @6767267
-system.cpu1: completed 90000 read, 50078 write accesses @6778899
-system.cpu3: completed 90000 read, 50108 write accesses @6783497
-system.cpu4: completed 90000 read, 50077 write accesses @6811616
-system.cpu5: completed 100000 read, 55112 write accesses @7430292
+    1.250000 rounded to 1
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
+system.cpu0: completed 10000 read, 5514 write accesses @985789
+system.cpu5: completed 10000 read, 5507 write accesses @985919
+system.cpu6: completed 10000 read, 5525 write accesses @1001074
+system.cpu2: completed 10000 read, 5599 write accesses @1007601
+system.cpu7: completed 10000 read, 5498 write accesses @1017943
+system.cpu4: completed 10000 read, 5572 write accesses @1024769
+system.cpu3: completed 10000 read, 5732 write accesses @1028309
+system.cpu1: completed 10000 read, 5598 write accesses @1041015
+system.cpu6: completed 20000 read, 11013 write accesses @1989998
+system.cpu0: completed 20000 read, 11024 write accesses @2017508
+system.cpu5: completed 20000 read, 11122 write accesses @2018515
+system.cpu2: completed 20000 read, 11126 write accesses @2025419
+system.cpu7: completed 20000 read, 11093 write accesses @2029349
+system.cpu3: completed 20000 read, 11390 write accesses @2036754
+system.cpu4: completed 20000 read, 11097 write accesses @2052341
+system.cpu1: completed 20000 read, 11255 write accesses @2071888
+system.cpu6: completed 30000 read, 16509 write accesses @3011316
+system.cpu2: completed 30000 read, 16563 write accesses @3015985
+system.cpu5: completed 30000 read, 16732 write accesses @3020048
+system.cpu7: completed 30000 read, 16594 write accesses @3039745
+system.cpu0: completed 30000 read, 16606 write accesses @3046317
+system.cpu4: completed 30000 read, 16705 write accesses @3051495
+system.cpu3: completed 30000 read, 17008 write accesses @3067438
+system.cpu1: completed 30000 read, 16891 write accesses @3109610
+system.cpu6: completed 40000 read, 22039 write accesses @4020333
+system.cpu5: completed 40000 read, 22236 write accesses @4027724
+system.cpu0: completed 40000 read, 22043 write accesses @4029762
+system.cpu2: completed 40000 read, 22161 write accesses @4031183
+system.cpu7: completed 40000 read, 22213 write accesses @4045977
+system.cpu4: completed 40000 read, 22298 write accesses @4082210
+system.cpu1: completed 40000 read, 22453 write accesses @4117416
+system.cpu3: completed 40000 read, 22664 write accesses @4121694
+system.cpu0: completed 50000 read, 27441 write accesses @5028972
+system.cpu6: completed 50000 read, 27572 write accesses @5030451
+system.cpu2: completed 50000 read, 27699 write accesses @5051990
+system.cpu5: completed 50000 read, 27966 write accesses @5054641
+system.cpu7: completed 50000 read, 27735 write accesses @5066083
+system.cpu4: completed 50000 read, 27771 write accesses @5088978
+system.cpu1: completed 50000 read, 28051 write accesses @5134928
+system.cpu3: completed 50000 read, 28027 write accesses @5145143
+system.cpu0: completed 60000 read, 32887 write accesses @6041088
+system.cpu6: completed 60000 read, 33047 write accesses @6052178
+system.cpu2: completed 60000 read, 33145 write accesses @6054126
+system.cpu5: completed 60000 read, 33467 write accesses @6058058
+system.cpu7: completed 60000 read, 33424 write accesses @6096363
+system.cpu4: completed 60000 read, 33328 write accesses @6102072
+system.cpu1: completed 60000 read, 33536 write accesses @6144667
+system.cpu3: completed 60000 read, 33718 write accesses @6194345
+system.cpu0: completed 70000 read, 38267 write accesses @7037253
+system.cpu6: completed 70000 read, 38604 write accesses @7069613
+system.cpu2: completed 70000 read, 38746 write accesses @7078099
+system.cpu5: completed 70000 read, 38936 write accesses @7088735
+system.cpu7: completed 70000 read, 39098 write accesses @7112647
+system.cpu4: completed 70000 read, 38903 write accesses @7119773
+system.cpu1: completed 70000 read, 39029 write accesses @7174150
+system.cpu3: completed 70000 read, 39351 write accesses @7212543
+system.cpu0: completed 80000 read, 43876 write accesses @8054755
+system.cpu6: completed 80000 read, 44096 write accesses @8081739
+system.cpu2: completed 80000 read, 44227 write accesses @8083983
+system.cpu5: completed 80000 read, 44434 write accesses @8095705
+system.cpu4: completed 80000 read, 44434 write accesses @8124001
+system.cpu7: completed 80000 read, 44724 write accesses @8128965
+system.cpu1: completed 80000 read, 44680 write accesses @8204951
+system.cpu3: completed 80000 read, 44871 write accesses @8248185
+system.cpu0: completed 90000 read, 49513 write accesses @9064097
+system.cpu2: completed 90000 read, 49820 write accesses @9098554
+system.cpu6: completed 90000 read, 49787 write accesses @9103948
+system.cpu5: completed 90000 read, 49985 write accesses @9122270
+system.cpu4: completed 90000 read, 50071 write accesses @9151457
+system.cpu7: completed 90000 read, 50244 write accesses @9162765
+system.cpu1: completed 90000 read, 50351 write accesses @9237663
+system.cpu3: completed 90000 read, 50544 write accesses @9266852
+system.cpu0: completed 100000 read, 54903 write accesses @10084846
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt
index 4a69b5566..ed5bb3990 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.010085                       # Nu
 sim_ticks                                    10084846                       # Number of ticks simulated
 final_tick                                   10084846                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 135609                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 534216                       # Number of bytes of host memory used
-host_seconds                                    74.37                       # Real time elapsed on the host
+host_tick_rate                                 104409                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 528428                       # Number of bytes of host memory used
+host_seconds                                    96.59                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
 system.mem_ctrls.bytes_read::ruby.dir_cntrl0     39539520                       # Number of bytes read from this memory
@@ -301,12 +301,12 @@ system.cpu6.num_writes                          55095                       # nu
 system.cpu7.num_reads                           99126                       # number of read accesses completed
 system.cpu7.num_writes                          55305                       # number of write accesses completed
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
-system.ruby.delayHist::bucket_size               2048                       # delay histogram for all message
-system.ruby.delayHist::max_bucket               20479                       # delay histogram for all message
+system.ruby.delayHist::bucket_size                 32                       # delay histogram for all message
+system.ruby.delayHist::max_bucket                 319                       # delay histogram for all message
 system.ruby.delayHist::samples                4974912                       # delay histogram for all message
-system.ruby.delayHist::mean                203.140608                       # delay histogram for all message
-system.ruby.delayHist::stdev               582.111066                       # delay histogram for all message
-system.ruby.delayHist                    |     4834308     97.17%     97.17% |      133920      2.69%     99.87% |        6363      0.13%     99.99% |         304      0.01%    100.00% |          15      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
+system.ruby.delayHist::mean                  6.256499                       # delay histogram for all message
+system.ruby.delayHist::stdev                16.952716                       # delay histogram for all message
+system.ruby.delayHist                    |     4677586     94.02%     94.02% |      147880      2.97%     97.00% |      114262      2.30%     99.29% |       31173      0.63%     99.92% |        3456      0.07%     99.99% |         420      0.01%    100.00% |         102      0.00%    100.00% |          25      0.00%    100.00% |           7      0.00%    100.00% |           1      0.00%    100.00% # delay histogram for all message
 system.ruby.delayHist::total                  4974912                       # delay histogram for all message
 system.ruby.outstanding_req_hist::bucket_size            2                      
 system.ruby.outstanding_req_hist::max_bucket           19                      
@@ -942,12 +942,12 @@ system.ruby.network.routers10.throttle9.msg_count.Response_Control::1       3960
 system.ruby.network.routers10.throttle9.msg_bytes.Control::0      4942480                      
 system.ruby.network.routers10.throttle9.msg_bytes.Response_Data::1     15964704                      
 system.ruby.network.routers10.throttle9.msg_bytes.Response_Control::1      3168552                      
-system.ruby.delayVCHist.vnet_0::bucket_size         2048                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::max_bucket        20479                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::bucket_size           32                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::max_bucket          319                       # delay histogram for vnet_0
 system.ruby.delayVCHist.vnet_0::samples       1568858                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::mean       640.119386                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::stdev      891.952930                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0           |     1428254     91.04%     91.04% |      133920      8.54%     99.57% |        6363      0.41%     99.98% |         304      0.02%    100.00% |          15      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::mean        15.791935                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::stdev       27.289154                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0           |     1272075     81.08%     81.08% |      147337      9.39%     90.47% |      114262      7.28%     97.76% |       31173      1.99%     99.74% |        3456      0.22%     99.96% |         420      0.03%     99.99% |         102      0.01%    100.00% |          25      0.00%    100.00% |           7      0.00%    100.00% |           1      0.00%    100.00% # delay histogram for vnet_0
 system.ruby.delayVCHist.vnet_0::total         1568858                       # delay histogram for vnet_0
 system.ruby.delayVCHist.vnet_1::bucket_size            8                       # delay histogram for vnet_1
 system.ruby.delayVCHist.vnet_1::max_bucket           79                       # delay histogram for vnet_1
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini
index 27d9847c3..c0e4f3cf5 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini
@@ -71,7 +71,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -82,7 +82,6 @@ size=32768
 system=system
 tags=system.cpu0.l1c.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.port
 mem_side=system.toL2Bus.slave[0]
@@ -124,7 +123,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -135,7 +134,6 @@ size=32768
 system=system
 tags=system.cpu1.l1c.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.port
 mem_side=system.toL2Bus.slave[1]
@@ -177,7 +175,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -188,7 +186,6 @@ size=32768
 system=system
 tags=system.cpu2.l1c.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.port
 mem_side=system.toL2Bus.slave[2]
@@ -230,7 +227,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -241,7 +238,6 @@ size=32768
 system=system
 tags=system.cpu3.l1c.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.port
 mem_side=system.toL2Bus.slave[3]
@@ -283,7 +279,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -294,7 +290,6 @@ size=32768
 system=system
 tags=system.cpu4.l1c.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu4.port
 mem_side=system.toL2Bus.slave[4]
@@ -336,7 +331,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -347,7 +342,6 @@ size=32768
 system=system
 tags=system.cpu5.l1c.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu5.port
 mem_side=system.toL2Bus.slave[5]
@@ -389,7 +383,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -400,7 +394,6 @@ size=32768
 system=system
 tags=system.cpu6.l1c.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu6.port
 mem_side=system.toL2Bus.slave[6]
@@ -442,7 +435,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -453,7 +446,6 @@ size=32768
 system=system
 tags=system.cpu7.l1c.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu7.port
 mem_side=system.toL2Bus.slave[7]
@@ -494,7 +486,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -505,7 +497,6 @@ size=65536
 system=system
 tags=system.l2c.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[0]
diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
index 5186e7456..7aa95bb02 100644
--- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -82,10 +83,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -96,7 +98,6 @@ size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -122,10 +123,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -136,7 +138,6 @@ size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -170,10 +171,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -184,7 +186,6 @@ size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
@@ -203,8 +204,11 @@ size=2097152
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
@@ -218,7 +222,8 @@ eventq_index=0
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex bendian.raw
-cwd=build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing
+cwd=build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing
+drivers=
 egid=100
 env=
 errout=cerr
@@ -227,6 +232,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/vortex
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -256,11 +262,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt
index f5fe53ea2..7015cfc4c 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.000323                       # Nu
 sim_ticks                                      322881                       # Number of ticks simulated
 final_tick                                     322881                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                2952595                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 447776                       # Number of bytes of host memory used
-host_seconds                                     0.11                       # Real time elapsed on the host
+host_tick_rate                                2211083                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 441516                       # Number of bytes of host memory used
+host_seconds                                     0.15                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
 system.mem_ctrls.bytes_read::ruby.dir_cntrl0        54144                       # Number of bytes read from this memory
@@ -264,12 +264,12 @@ system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       #
 system.mem_ctrls_1.memoryStateTime::ACT             0                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.ruby.clk_domain.clock                        1                       # Clock period in ticks
-system.ruby.delayHist::bucket_size                512                       # delay histogram for all message
-system.ruby.delayHist::max_bucket                5119                       # delay histogram for all message
+system.ruby.delayHist::bucket_size                  4                       # delay histogram for all message
+system.ruby.delayHist::max_bucket                  39                       # delay histogram for all message
 system.ruby.delayHist::samples                   6760                       # delay histogram for all message
-system.ruby.delayHist::mean                 50.962278                       # delay histogram for all message
-system.ruby.delayHist::stdev               238.173200                       # delay histogram for all message
-system.ruby.delayHist                    |        6512     96.33%     96.33% |         158      2.34%     98.67% |          46      0.68%     99.35% |          24      0.36%     99.70% |           9      0.13%     99.84% |           8      0.12%     99.96% |           2      0.03%     99.99% |           0      0.00%     99.99% |           0      0.00%     99.99% |           1      0.01%    100.00% # delay histogram for all message
+system.ruby.delayHist::mean                  0.896450                       # delay histogram for all message
+system.ruby.delayHist::stdev                 2.643920                       # delay histogram for all message
+system.ruby.delayHist                    |        5999     88.74%     88.74% |         459      6.79%     95.53% |         195      2.88%     98.42% |          74      1.09%     99.51% |          23      0.34%     99.85% |           5      0.07%     99.93% |           3      0.04%     99.97% |           2      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
 system.ruby.delayHist::total                     6760                       # delay histogram for all message
 system.ruby.outstanding_req_hist::bucket_size            2                      
 system.ruby.outstanding_req_hist::max_bucket           19                      
@@ -481,12 +481,12 @@ system.ruby.network.routers3.throttle2.msg_count.Response_Control::1           8
 system.ruby.network.routers3.throttle2.msg_bytes.Control::0         6768                      
 system.ruby.network.routers3.throttle2.msg_bytes.Response_Data::1        54216                      
 system.ruby.network.routers3.throttle2.msg_bytes.Response_Control::1          712                      
-system.ruby.delayVCHist.vnet_0::bucket_size          512                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::max_bucket         5119                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::bucket_size            4                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::max_bucket           39                       # delay histogram for vnet_0
 system.ruby.delayVCHist.vnet_0::samples          2420                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::mean       141.339256                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::stdev      381.793770                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0           |        2172     89.75%     89.75% |         158      6.53%     96.28% |          46      1.90%     98.18% |          24      0.99%     99.17% |           9      0.37%     99.55% |           8      0.33%     99.88% |           2      0.08%     99.96% |           0      0.00%     99.96% |           0      0.00%     99.96% |           1      0.04%    100.00% # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::mean         1.485950                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::stdev        3.479612                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0           |        2005     82.85%     82.85% |         204      8.43%     91.28% |         133      5.50%     96.78% |          53      2.19%     98.97% |          17      0.70%     99.67% |           5      0.21%     99.88% |           1      0.04%     99.92% |           2      0.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_0
 system.ruby.delayVCHist.vnet_0::total            2420                       # delay histogram for vnet_0
 system.ruby.delayVCHist.vnet_1::bucket_size            4                       # delay histogram for vnet_1
 system.ruby.delayVCHist.vnet_1::max_bucket           39                       # delay histogram for vnet_1
author	Nilay Vaish <nilay@cs.wisc.edu>	2015-07-04 10:43:47 -0500
committer	Nilay Vaish <nilay@cs.wisc.edu>	2015-07-04 10:43:47 -0500
commit	9954eb74df98c4749651eb78098595f78d642105 (patch)
tree	74766341f05f999e2ad00626284e09dc6d0a2c58 /tests
parent	67925a833445a8b2ddce0fae4c86677ce0f4298d (diff)
download	gem5-9954eb74df98c4749651eb78098595f78d642105.tar.xz