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authorAndreas Hansson <andreas.hansson@arm.com>2012-10-31 08:39:43 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2012-10-31 08:39:43 -0400
commitab0bd51315eed6a7853b9dfa44f9fdbe9399ea85 (patch)
tree33f8522d6f593647ae26a97f14ba67e4c25193f5 /tests
parent10b70d54529f0a44dc088c9271d9ecf3a8ffe68a (diff)
downloadgem5-ab0bd51315eed6a7853b9dfa44f9fdbe9399ea85.tar.xz
config: Fix a typo in the simple-atomic-mp configuration
This patch fixes a minor typo that managed to sneak into the simple-atomic-mp regression configuration.
Diffstat (limited to 'tests')
-rw-r--r--tests/configs/simple-atomic-mp.py4
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py
index 231c4ebe9..966ae24fe 100644
--- a/tests/configs/simple-atomic-mp.py
+++ b/tests/configs/simple-atomic-mp.py
@@ -41,7 +41,7 @@ system = System(cpu = cpus,
# l2cache & bus
system.toL2Bus = CoherentBus(clock = '2GHz')
-system.l2c = L2Caches(clock = '2GHz', size='4MB', assoc=8)
+system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.master
# connect l2c to membus
@@ -49,7 +49,7 @@ system.l2c.mem_side = system.membus.slave
# add L1 caches
for cpu in cpus:
- cpu.addPrivateSplitL1Caches(L1Caches(size = '32kB', assoc = 1),
+ cpu.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
L1Caches(size = '32kB', assoc = 4))
# create the interrupt controller
cpu.createInterruptController()